JPH0553793A - Processor for processing digital signal - Google Patents

Abstract

PURPOSE:To re-write a microprogram or a coefficient at high speed without causing a hindrance to a DSP processing. CONSTITUTION:A coefficient utilizing means processes a digital signal operation corresponding to an algorithm stipulated by the microprogram through the use of the coefficient. A first and the second transfer buffer 1a and 1b temporarily store data for rewriting the microprogram and the coefficient inputted from an external processor so as to output restored data for rewriting to a microprogram storing means 32 and a coefficient storing means 34. Either of the first and second buffer 1a or 1b operates the storage of rewriting data and the other one operates the output of rewriting data. The storing operation and the output operation of the first and second buffer 1a and 1b are executed based on the operation clock of the coefficient utilizing means inside a digital signal processing processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor suitable for digitizing and processing musical tone signals, voice signals and the like.

[0002]

2. Description of the Related Art Digital signal processor (DSP:
Digital Signal Processor)
In the audio field, is used for a reverberator (reverberation adding device), an equalizer, a mixer, etc., or a recursive type (IIR: Infinite Impulse Res.
poser) filter, non-recursive type (FIR: Finit)
It is used to configure various digital filters such as eImpulse Response) filters. The DSP is also used in a sound source of an electronic musical instrument, an envelope generating circuit, a reverb effect device, or the like. In addition to these, they are used in various fields such as precision control devices, high-definition TVs and digital VTRs.

On the other hand, the performance of electronic musical instruments has been greatly improved along with the rapid development of electronic and digital technologies, and the drawback that "electronic musical instruments lack timbre compared to natural musical instruments" has been overcome. , Further progressing and developing. Among them, the appearance of digital signal processors (DSPs) and the high processing speed of the DSPs have made the electronic musical instruments more expressive and capable of synthesizing various musical sounds.

Generally, a DSP has a microprogram register for storing a microprogram as a basic algorithm, a multiplier for accumulating product-sum operations at high speed, an accumulator (accumulator), a shift register, and a data RAM.
And a coefficient register for supplying a predetermined coefficient to the multiplier or the like.

When the DSP is made to function as a digital filter, a sound source, an envelope generating circuit, a reverberation effect device, etc., the contents of the microprogram in the microprogram register and the coefficient in the coefficient register are adapted to the respective functions. In order to set and further change its characteristics with time, it was necessary to sequentially change the coefficient. Conventionally, an external higher-level processor has executed a rewriting process of microprograms and coefficients that determine the function of the DSP.

[0006]

The above-mentioned microprogram and coefficient rewriting processing is usually performed by an external processor. Some microprograms inside the DSP itself perform interpolation processing for smoothly changing the coefficient. When such a DSP is applied to a control device such as a precision machine and the microprogram or coefficient is semi-fixedly used, it is not necessary to frequently rewrite the microprogram or coefficient.

However, when the DSP is used for a digital filter for a voice signal or the like, in order to gradually change the filter characteristic with time, the coefficient is appropriately changed with time, or the filter characteristic is significantly changed. It is necessary to rewrite the microprogram itself to change to. Also, when the DSP is used as a sound source of an electronic musical instrument, the coefficient must be changed every moment, and the microprogram must be rewritten appropriately according to the type of the sound source.

Conventionally, when rewriting a microprogram or coefficient in the DSP, a buffer in the DSP has been used. The rewriting process will be described below. 7 to 10 are views showing the concept of rewriting processing of a microprogram in a DSP which has been conventionally performed.

7 to 10, the micro program storage means 32 is composed of 256 stages of shift registers, and each shift register has program data A00.
0 to A255 are stored. Program data A000 to A25 in the micro program storage means 32
The cycle in which 6 is read out at any time by the internal clock INT CLK corresponds to one sampling cycle of the DSP.

The buffer 71 is composed of a shift register having 128 stages, which is half of the microprogram storage means 32. Program data B000 to B127 for rewriting is stored in each shift register of the buffer 71. Program data B000 to B12 for this rewriting
7 is written as needed at the timing of the operation clock of the external processor. The buffer 71 may be composed of a RAM or the like having a storage area corresponding to a shift register for 128 stages.

The selector circuit 72 is an operation clock (external clock) EXT CL of an external processor (not shown).
Operation clock (internal clock) INT in K and DSP
CLK is selectively switched according to the clock selection signal SC and supplied to the clock input terminal of the buffer 71. Therefore, when the clock selection signal SC is low level "0", the external clock EXT CLK is supplied to the clock input terminal of the buffer 71, and when the clock selection signal SC is high level "1", the internal clock INT CLK is supplied to the clock input terminal of the buffer 71.

The selector circuit 73 stores the rewriting program data stored in the lowermost (0th) shift register of the buffer 71 and the lowermost (0th) shift register of the microprogram storage means 32. The stored program data is selectively switched according to the data selection signal SD and supplied to the uppermost (256th) register of the microprogram storage means 32.

The operation when the external processor rewrites the contents of the microprogram storage means 32 is performed as follows. First, the external processor uses the clock selection signal SC
Outputs a low level “0” to the selector circuit 72 as
External processor operating clock (external clock) EXT
The buffer 71 is operated at the timing of CLK. Figure 7
Program data B00 for rewriting in this way
0 to B127 are written in the buffer 71. At this time, the selector circuit 73 outputs the data selection signal S
Since the low level “0” is input as D, the program data stored in the lowest stage (0th stage) register of the microprogram storage means 32 is the highest stage (256th stage) of the microprogram storage means 32. Are sequentially supplied to the registers of the microprogram storage means 32.
Program data A000 to A256 of 56 steps are sequentially and repeatedly output.

Then, as shown in FIG. 8, the program data A is stored in the lowermost stage (0th stage) of the microprogram storage means 32.
000 is located and the program data A255 is located at the uppermost stage (256th stage) (the start point of the sampling cycle), the clock selection signal SC and the data selection signal S
The high level "1" as D is the selector circuits 72 and 73.
Set to input to. Then, the buffer 71
The program data B000 for rewriting stored in the lowermost register (0th stage) of the above is sequentially supplied to the uppermost register (256th stage) of the microprogram storage means 32, and the program of the microprogram storage means 32 is stored. Data A000 to A126 are rewriting program data B000 to A in the buffer 71 as shown in FIG.
B126 is sequentially rewritten, and finally half of the program data A00 in the microprogram storage means 32 is written.
0 to A127 are program data B0 in the buffer 71
It is rewritten to 00 to B127.

When the transfer of the rewriting program data B000 to B127 in the buffer 71 is completed, there is no more data in the buffer 71, so the clock selection signal S
Low level "0" is input to the selector circuits 72 and 73 as C and the data selection signal SD. Then, as shown in FIG. 10, the external processor uses the external clock EXT CL.
The transfer of the remaining program data B128 to B255 to the buffer 71 is started at a cycle of K. At this time, the micro program storage means 32 stores the internal clock INT C
Program data A128 to A256, B in the cycle of LK
000 to B127 are sequentially and repeatedly output.

Program data B128 is stored in the buffer 71.
After writing B255 to B255, the program data A12 is written in the lowest stage (0th stage) of the micro program storage means 32.
8 is located and the program data B127 is located at the uppermost stage (256th stage) (the start point of the sampling cycle), the clock selection signal SC and the data selection signal SD.
As a result, a high level “1” is input to the selector circuits 72 and 73. Rewriting program data B12 stored in the lowermost (0th) register of the buffer 71
From 8 onward, the uppermost stage (2
It is sequentially supplied to the 56th stage register. Therefore, the program data A12 of the microprogram storage means 32
8 to A255 are sequentially rewritten and replaced by the program data B128 to B255 in the buffer 71,
Finally, all the program data B000 to B255 are written in the micro program storage means 32, and the rewriting of the program data is completed.

However, in the case of the prior art as shown in FIGS. 7 to 10, the external processor is divided into two portions in order to rewrite all the program data A000 to A255 in the micro program storage means 32.
The program data B000 to B255 must be written in the. Then, during the second writing process, mixed program data of the old program data A128 to A255 and the new micro program data B000 to B127 is output from the micro program storage means 32. Since the DSP cannot operate while such mixed program data is being output, the DSP processing is suspended until all the program data are rewritten.

In this way, when it is necessary to rewrite the microprogram and the coefficient in the DSP every moment, if the rewriting is performed via the buffer as in the conventional case, the DS
There is a problem that the processing of P is hindered and the high-speed processing performance of the DSP is deteriorated.

The present invention has been made in view of the above points, and an object of the present invention is to provide a digital signal processor capable of rewriting a microprogram or a coefficient at high speed without hindering the processing of the DSP. And

[0020]

A digital signal processor according to the present invention is defined by a microprogram storing means for storing a microprogram defining an algorithm, a coefficient storing means for storing a coefficient, and the microprogram. Coefficient use means for performing digital signal arithmetic processing according to an algorithm while using the coefficient; and the microprogram and the coefficient rewriting data input from an external processor are temporarily stored and stored. Rewriting data is output to the microprogram storage means and the coefficient storage means, and the first and second storage operations and the output operation are performed based on an operation clock of the coefficient utilization means.
And a buffer means of.

[0021]

In the present invention, the microprogram storage means stores the microprogram which defines the DSP function, that is, the algorithm. The coefficient storage means stores coefficients used when the microprogram is executed. Therefore,
The coefficient utilization means performs digital signal arithmetic processing according to an algorithm defined by the microprogram while utilizing the coefficient. The first and second buffers temporarily store microprogram and coefficient rewriting data input from an external processor, and output the stored rewriting data to the microprogram storage unit and coefficient storage unit. .. Therefore, one of the first and second buffers performs the rewrite data storage operation, and the other performs the rewrite data output operation. As a result, the rewriting of the microprogram and the coefficient can be performed at high speed without disturbing the processing of the digital signal processor. Further, the normal buffer is provided to adjust the difference in the operating clock (operating speed) between the external processor and the digital signal processor. However, in the present invention, the operating clock of the external processor is the same as that of the digital signal processor. Paying attention to being always slower than the operation clock, the storage operation and the output operation of the first and second buffers are executed based on the operation clock of the coefficient utilization means in the digital signal processor. As a result, it is not necessary to adjust the timing of the operation clock, which is conventionally performed, and the rewriting process of rewriting data can be performed at a higher speed.

[0022]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram showing a hardware configuration of an electronic musical instrument when the digital signal processor according to the present invention is used as a sound source. In this embodiment, control of the entire musical tone synthesizer is performed by a microprocessor unit (MPU) 20 and a program memory (ROM) for storing system programs and various parameters.
21 and a working memory (RAM) 22 that temporarily stores various data and is used as a working area.

In the embodiment of FIG. 2, control of the entire electronic musical instrument is performed by a microprocessor unit (MPU) 20,
Program memory for storing system programs (RO
M) 21 and a working memory (RAM) 22 for storing various data. To the microcomputer system, various devices such as a key switch circuit 24, a key touch detection circuit 25, a tone color selection switch circuit 26, and a sound source 27 are connected via a data and address bus 28. Is controlled by a microcomputer.

The keyboard 23 is provided with a plurality of keys for selecting the pitch of a musical tone to be generated, and a key switch circuit 24 and a key touch detection circuit 25 are connected to each key. The key switch circuit 24 is composed of a plurality of key switches provided corresponding to the respective keys of the keyboard 23 for designating the pitch of the musical sound to be generated. The key switch circuit 24 detects the depressed or released state of the keyboard 23 and releases the key. The key-on event signal is output in response to the change from to key press, the key-off event signal is output in response to the change from key press to key release, and the key code signal indicating the key corresponding to each key event is output. Output. Based on each output of the key switch circuit 24, a pressed key detection process and a tone generation assignment process for assigning a depressed key to any of a plurality of tone generation channels are performed by a microcomputer system, and if necessary, a key depression operation at the time of depression. A process of determining the speed and generating initial touch data is also performed.

The key touch detection circuit 25 incorporates an after touch sensor which detects a pressing force when the key is continuously pressed and outputs after touch data in association with each key of the keyboard 23. The timbre selection switch circuit 26
It is provided on the operation panel including various controls for selecting, setting, and controlling pitch, effect, etc., tones and other various sounds corresponding to various natural musical instruments such as piano, organ, violin, brass instrument, guitar, etc. Is selected, and a tone color selection signal is output.

The sound source 27 is capable of simultaneously generating musical tone signals on a plurality of channels, and has a data and address bus 28.
Input the key code, key-on signal, key-off signal, initial touch data, after-touch data, tone color selection signal and other data assigned to each channel via the various tone data signals. To occur.

The digital tone signal generated from the sound source 27 is converted into an analog tone signal by a digital / analog converter (not shown) in the sound system 40. The sound system 40 is composed of a speaker, an amplifier and the like, and generates a musical sound according to a digital musical sound signal from the sound source 27.

In this embodiment, the sound source 27 is composed of a digital signal processor (DSP). Hereinafter, the sound source 27 will be referred to as a sound source DSP 27. The tone generator DSP 27 is composed of an interface circuit 31, a micro program storage means 32, a coefficient utilization section 33 and a coefficient storage means 34.

The interface circuit 31 is an interface for data input / output between the microprocessor system and the tone generator DSP 27, and is composed of first and second transfer buffers. Micro program storage means 32
Is for storing micro programs for sound sources,
It is composed of a multi-stage shift register. The microprogram is written by the external MPU 20 via the data and address bus 28 and the interface circuit 31. The coefficient utilization unit 33 is composed of a multiplier, an accumulator (accumulator), a shift register, a data RAM, a random number generator, and the like for executing the sum of products operation at high speed. Since the configuration of the coefficient utilization unit 33 is the same as the conventional one,
The description is omitted. The coefficient storage means 34 stores the coefficients for the sound source and, like the microprogram storage means 32, is composed of a multi-stage shift register. The microprogram storage means 32 and the coefficient storage means 34 may be composed of RAM.

FIG. 1 is a diagram showing a detailed configuration of the interface circuit 31 of FIG. Interface circuit 31
Are the first and second transfer buffers 1a and 1b, the first and second transfer control registers 2a and 2b, the selector circuit 3,
4, transfer control circuit 5, flip-flop circuits 6a, 6
b, 7a, 7b, 8 and AND circuits 9, 10, 11, 1
2. It is composed of OR circuits 13a and 13b and inverting circuits 14 and 15.

First and second transfer buffers 1a and 1b
Is connected to the external processor 20 via the data and address bus 28, and the data D from the external processor 20 is
The T1 and the address AD1 are directly input, and the write request signal WR is further input via the AND circuits 9 and 10. The first and second transfer buffers 1a and 1b operate at the same clock CL as the operation clocks of the microprogram storage means 32 and the coefficient storage means 34 in the DSP. Therefore,
The first and second transfer buffers 1a and 1b receive the data DT1, the address AD1 and the write request signal WR from the external processor 20 to write the data DT1 to the address AD1 at every timing of the operation clock CL. To be crowded.

Since the operation clock of the external processor 20 is much slower than the operation clock CL in the DSP, the data DT1 is written to the address AD1 many times, but the content itself of the data DT1 is not changed. It doesn't matter because it doesn't. Here, the total number of data DT1 continuously written from the processor 20 cannot exceed the number of words of the first and second transfer buffers 1a and 1b.

First and second transfer buffers 1a and 1b
Is a transfer control circuit 5 and flip-flop circuits 7a, 7
b, the address AD2 from the transfer control circuit 5, which is connected to the microprogram storage means 32 and the coefficient storage means 34.
And the output enable signals OEa and OEb from the flip-flop circuits 7a and 7b are input. Then, the first and second transfer buffers 1a and 1b include the flip-flop circuit 7
By inputting the output permission signals OEa and OEb from a and 7b, the data DT2 corresponding to the address AD2 from the transfer control circuit 5 is stored in the microprogram storage means 3
2 and the coefficient storage means 34.

First and second transfer control registers 2a, 2
Similarly to the first and second transfer buffers 1a and 1b, b is connected to the external processor 20 via the data and address bus 28, and the data D from the external processor 20 is transmitted.
The T1 and the address AD1 are input, and the write request signal WR is further input via the AND circuits 9 and 10. That is, after the transfer of the data DT1 to the first and second transfer buffers 1a and 1b is completed, the data DT1 relating to the transfer is transferred to the first and second transfer control registers 2a and 2b.
Is written. The first and second transfer buffers 1
a, 1b and first and second transfer control registers 2a, 2
Different addresses are assigned to the addresses AD1 input to b.

The first transfer control register 2a stores the data DT.
When the writing process of 1 (data related to transfer) is completed,
At that time, the set signal STa is sent to the flip-flop circuit 6
a and the set terminal of the flip-flop circuit 8,
Flip-flop circuit 6a and flip-flop circuit 8
The output Q of is set to the high level "1". The second transfer control register 2b receives the set signal STb at the time when the writing process of the data DT1 (data related to transfer) is completed.
Is output to the set terminal of the flip-flop circuit 6b, and the output Q of the flip-flop circuit 6b is set to the high level "1". Since the first and second transfer control registers are selectively connected to the transfer control circuit 5 via the selector circuit 4, the data DT1 (data related to transfer) written by the external processor 20 is selectively transfer-controlled. It is output to the circuit 5.

The flip-flop circuits 6a and 6b are the first
And the second transfer control registers 2a and 2b, the flip-flop circuits 7a and 7b and the OR circuits 13a and 13b, and the set signal S of the first transfer control registers 2a and 2b.
Ta and STb are set terminals S, and output enable signals OEa and OEb output from the flip-flop circuits 7a and 7b.
Are input to the reset terminal R, and the output Q is output to the OR circuits 13a and 13b. Therefore, the flip-flop circuits 6a and 6b send data DT1 (data related to transfer) to the first and second transfer control registers 2a and 2b.
When the set signal STa or STb is input after the completion of the writing process of 1 and the output enable signals OEa and OEb of high level “1” are input from the flip-flop circuits 7a and 7b, It is set to low level "0".

The OR circuit 13a inputs the outputs Q of the flip-flop circuits 6a and 7a, and outputs a logical sum signal of both outputs to the inverting circuit 14 and the AND circuit 10. Inversion circuit 1
4 inverts the logical sum signal of the OR circuit 13a and outputs it to the AND circuit 9. The AND circuit 9 is the external processor 2
The write request signal WR of 0 and the inverted output of the logical sum signal of the OR circuit 13a are input. The AND circuit 10 inputs the write request signal WR of the external processor 20 and the logical sum signal of the OR circuit 13a. Therefore, the write request signal WR from the external processor 20 passes through either one of the AND circuits 9 or 10 and the first or second transfer buffer 1a,
Enter in 1b. As a result, the first
And the series of the second transfer buffers 1a and 1b is selected.

The OR circuit 13b inputs the outputs Q of the flip-flop circuits 6b and 7b and outputs a logical sum signal of both outputs to the AND circuit 11. AND circuit 11 is OR circuit 1
The logical sum signal of 3a and 13b is inputted, the logical product of both signals is taken, and the logical product signal is taken as a busy signal BUSY via the data and address bus 28 to the external processor 20.
Output to. High level “1” busy signal BUSY
Is output from the AND circuit 11, the external processor 2
It can be recognized that 0 can not write data to the first and second transfer buffers 1a and 1b.

The AND circuit 11 outputs the high-level "1" AND signal (busy signal) BUSY in the following three cases. First, when the high-level "1" output signal Q is output from the flip-flop circuits 6a and 6b, that is, the first and second transfer buffers 1
a, 1b and first and second transfer control registers 2a, 2
This is a case where the data writing to b is completed and the writing data already exists in the first and second transfer buffers 1a and 1b. Secondly, when the flip-flop circuit 6a outputs the high-level "1" output signal Q and the flip-flop circuit 7b outputs the high-level "1" output signal Q (output enable signal OEb), that is, The data writing to the first transfer buffer 1a and the first transfer control register 2a is completed, the data in the second transfer buffer 1b is being transferred to the microprogram storage means 32 or the coefficient storage means 34, and the data is stored in the first transfer buffer 1a. Is the case where the data for writing already exists.

Third, the flip-flop circuit 6b outputs the high-level "1" output signal Q, and the flip-flop circuit 7a outputs the high-level "1" output signal Q (output enable signal OEa). In the case, that is, the data writing to the second transfer buffer 1b and the second transfer control register 2b is completed, the data of the first transfer buffer 1a is being transferred to the microprogram storage means 32 or the coefficient storage means 34, and the second transfer buffer This is a case where data for writing already exists in 1b. In the above case, the external processor 20 causes the first and second transfer buffers 1a and 1b to
If you write data to, it will malfunction.
The external processor 20 cannot execute the data writing process while the busy signal BUSY is output from the AND circuit 11.

The transfer control circuit 5 is connected to the first and second transfer buffers 1a and 1b, selector circuits 3 and 4, flip-flop circuits 7a, 7b and 8, micro program storage means 32 and coefficient storage means 34. .. The transfer control circuit 5 inputs data relating to the transfer from either one of the first and second transfer control registers 2a and 2b via the selector circuit 4, and based on the data relating to the transfer
And an address A common to the second transfer buffers 1a and 1b
D2, an output enable signal OE to the selector circuit 3, and a write request signal WRP or WRC to either the microprogram storage means 32 or the coefficient storage means 34,
The data in the first and second transfer buffers 1a and 1b is written in the microprogram storage means 32 or the coefficient storage means 34.

Then, when the data writing is completed, the transfer control circuit 5 outputs the flip-flop circuit 7 at that time.
The transfer end signal TE is output to the reset terminals R of a, 7b and 8. The flip-flop circuits 7a, 7b, 8 to which the transfer end signal TE has been input are reset to the low level "0", and the low and "0" output enable signals OEa, 1a, 1b are supplied to the first and second transfer buffers 1a, 1b. OEb is output,
A low level “0” signal is also output to the AND circuit 12. Further, when the flip-flop circuits 7a and 7b are reset and the output Q (output enable signals OEa and OEb) thereof becomes low level "0", the flip-flop circuits 6a and 6b are also reset accordingly and the output Q thereof also becomes low. The level becomes “0”. Then, the AND circuit 11 outputs the busy signal BUSY of low level "0" to the external processor 20 in order to indicate that the data transfer to the first and second transfer buffers 1a and 1b is possible. Further, the AND circuit 9 outputs the write request signal WR of high level “1” to the first transfer buffer 1 a, and the AND circuit 1
Since 0 outputs the write request signal WR of low level "0" to the second transfer buffer 1b, the data write process is executed first from the first transfer buffer 1a.

The flip-flop circuit 8 has a set terminal S.
The set signal STa output from the first transfer control register 2a and the transfer end signal TE of the transfer control circuit 5 are input to the reset terminal R, respectively, and the output Q is output to the AND circuit 1
Output to 2. That is, the flip-flop circuit 8 is
When the writing of the data to the first transfer buffer 1a and the second transfer control register 2a is completed, the output Q is set to the high level "1", and the microprogram storage means 32 or the coefficient storage means 34 from the first transfer buffer 1a.
When the data writing to the data is completed and the transfer end signal TE is input from the transfer control circuit 5, the output Q is reset to the low level "0".

The AND circuit 12 takes the logical product of the output Q of the flip-flop circuit 8 and the inverted output of the output Q of the flip-flop circuit 7b, that is, the inverted output of the inversion circuit 15, and selects the logical product signal as the selection signal SE. Output to the circuits 3 and 4. That is, the AND circuit 12 has the first
When the data writing to the transfer buffer 1a and the first transfer control register 2a is completed, and the data writing from the second transfer buffer 1b to the microprogram storage means 32 or the coefficient storage means 34 is completed,
It outputs a logical product signal of high level "1", and outputs a logical product signal of low level "0" in other cases.

The selector circuit 3 is a flip-flop circuit 7
a, 7b, the AND circuit 12, and the transfer control circuit 5, and outputs the output permission signal OE of the transfer control circuit 5 to the flip-flop circuits 7a, 7 according to the logical product signal of the AND circuit 12.
An output enable signal OE1 is output to one of the set terminals S of b.
Alternatively, it is selectively output as OE2. Therefore, the writing of data to the first transfer buffer 1a and the first transfer control register 2a is completed, and the output Q of the flip-flop circuit 8 is reached.
Is at the high level "1", and the flip-flop circuit 7b
Of the output Q of the low level "0", the selector circuit 3
Outputs the output enable signal OE1 of high level "1" to the set terminal of the flip-flop circuit 7a. The flip-flop circuit 7a receives the output enable signal OE1 and then receives the first
A high level "1" output enable signal O is sent to the transfer buffer 1a.
Ea is output and the first transfer buffer 1a is set in the output enable state. At this time, the output enable signal OEa of high level "1" is also output from the flip-flop circuit 7a to the OR circuit 13a.
Does not output the write request signal WR from the first transfer buffer 1a.

The selector circuit 4 is connected to the first and second transfer control registers 2a and 2b, the AND circuit 12, and the transfer control circuit 5, and the first and second transfer are performed according to the AND signal of the AND circuit 12. Either one of the data (data related to transfer) in the control registers 2a and 2b is selectively output to the transfer control circuit 5.

AND signal of AND circuit 12 (selection signal S
E) becomes high level "1" because the data writing to the first transfer buffer 1a and the first transfer control register 2a is completed and the output Q of the flip-flop circuit 8 is high level "1". Output Q of circuit 7b
Is a low level "0". Therefore, the data in the first transfer buffer 1a is stored in the microprogram storage means 3
2 or the coefficient storage means 34, and when the transfer end signal TE is input from the transfer control circuit 5 to the reset terminal of the flip-flop circuit 8, the AND circuit 12 outputs a logical product signal of low level "0". .. Then, the output enable signal OE of the transfer control circuit 5 is input to the set terminal S of the flip-flop circuit 7b by the selector circuit 3. Therefore, once the flip-flop circuit 7b is set, until the transfer end signal TE of the transfer control circuit 5 is input to the reset terminal R of the flip-flop circuit 7b,
The AND circuit 12 continues to output the logical product signal of low level “0” to the selector circuits 3 and 4.

In the flip-flop circuit 7a, the output enable signal OE1 selectively output from the selector circuit 3 is input to the set terminal S, and the transfer end signal TE output from the transfer control circuit 5 is input to the reset terminal R. Its output Q
Is output as the output enable signal OEa of the first transfer buffer 1a, and is also output to the reset terminal R of the flip-flop circuit 6a and the OR circuit 13a. That is, the flip-flop circuit 7a is set to the high level "1" when transferring the data in the first transfer buffer 1a to the microprogram storage means 32 or the coefficient storage means 34,
When the transfer is completed, it is reset to low level "0".

The flip-flop circuit 7b inputs the output permission signal OE2 selectively output from the selector circuit 3 to the set terminal S and the transfer end signal TE output from the transfer control circuit 5 to the reset terminal R, Its output Q
Is output as the output enable signal OEb of the second transfer buffer 1b, and is also output to the reset terminal R of the flip-flop circuit 6b and the OR circuit 13b. That is, the flip-flop circuit 7b is set to the high level "1" when transferring the data in the second transfer buffer 1b to the microprogram storage means 32 or the coefficient storage means 34,
When the transfer is completed, it is reset to low level "0".

Next, the operation of this embodiment will be described with reference to FIGS. 3 to 6 are views showing the concept of the rewriting process of the microprogram in FIG. 1, and correspond to FIGS. 7 to 10 of the conventional technique. In the figure, the micro program storage means 32 is composed of 256 stages of shift registers. Program data A000 to A255 is stored in each shift register. Program data A00 in the micro program storage means 32
A cycle in which 0 to A256 is read by the internal clock CL of the DSP corresponds to one sampling cycle of the DSP. Regarding the data rewriting process of the coefficient storage means 34, the microprogram storage means 32 shown in FIGS.
The same operation is performed by substituting for the coefficient storage means 34. Therefore, only the data rewriting processing of the microprogram storage means 32 will be described here, and the coefficient storage means 34 will be omitted.

First and second transfer buffers 1a and 1b
Is composed of a RAM having a storage area corresponding to a shift register of 64 stages, which corresponds to about one-fourth of the microprogram storage means 32. In FIG. 3, rewriting program data B000 to B063 are stored in respective address positions of the first transfer buffer 1a, and rewriting program data B064 to B127 are also stored in respective address positions of the second transfer buffer 1b. Has been done.

The selector circuit 16 is stored in the rewriting program data stored in the first and second buffers 1a and 1b and the shift register at the lowest stage (0th stage) of the microprogram storage means 32. The program data is selectively switched according to the write request signal WRP of the transfer control circuit 5, and the micro program storage means 3 is selected.
2 is supplied to the uppermost register (256th stage). Although not shown in FIG. 1, the selector circuit 16 is built in the microprogram storage means 32 or the coefficient storage means 34.

Therefore, when the write request signal WRP is at the high level "1", the first and second buffers 1a and 1b.
The program data for rewriting stored in is stored in the uppermost (256th) register of the microprogram storage means 32. On the contrary, when the write request signal WRP is at the low level “0”, the program data stored in the shift register at the lowermost stage (0th stage) of the microprogram storage means 32 is the microprogram storage means 3.
2 is supplied to the uppermost register (256th stage). On the other hand, although not shown, when the write request signal WRC is at high level "1", the first and second buffers 1a and 1b
The coefficient data for rewriting stored in is stored in the coefficient storage means 34, and conversely, when the write request signal WRC is at the low level "0", the coefficient data is circulated in the coefficient storage means 34.

First, the first and second transfer buffers 1a,
The case of writing rewriting program data in 1b will be described. First and second transfer buffers 1a, 1
When writing the program data for rewriting in b, the first and second transfer buffers 1
Since the program data in a and 1b must have been transferred to the microprogram storage means 32 or the coefficient storage means 34, the flip-flop circuits 7a, 7b and 8 are once set and then reset by the transfer end signal TE. Therefore, the OR circuit 13a outputs a low level "0" logical sum signal to the inverting circuit 14 and the AND circuit 11, and the OR circuit 13b outputs a low level "0" logical sum signal to the AND circuit 11. Therefore, the AND circuit 11 outputs the low level “0” busy signal BUSY to the external processor 20.

The external processor 20 outputs the write request signal WR to the first and second transfer buffers 1a and 1b in response to the input of the low level "0" busy signal BUSY. At this time, a high level “1” signal is input to the AND circuit 9 via the inverting circuit 14,
Since the low-level "0" logical sum signal is directly input to 0 from the OR circuit 13a, the write request signal WR from the external processor 20 is input only to the first transfer buffer 1a and to the second transfer buffer 1b. Do not enter.

In this way, the first transfer buffer 1a becomes the writable state by the input of the write request signal WR. The external processor 20 outputs the rewriting data DT1 and the address AD1 to the first transfer buffer 1a, as shown in FIG.
64 pieces of rewriting data B000 to B063
Are sequentially written. The external processor 20 sends all data B0
When the writing of 00 to B063 is completed, the data relating to the transfer is written to the first transfer control register 2a this time.

When the data writing to the first transfer buffer 1a and the first transfer control register 2a is completed, the set signal STa is output from the first transfer control register 2a to the set terminal S of the flip-flop circuit 6a. The output Q of the circuit 6a becomes a high level "1". A high level "1" output Q of the flip-flop circuit 6a inputs a low level "0" signal to the AND circuit 9 via the inverting circuit 14, and an AND circuit 10 receives a high level "1" from the OR circuit 13a. Since the OR signal of "" is directly input, the write request signal WR from the external processor 20 is only input to the second transfer buffer 1b this time,
No data is input to the first transfer buffer 1a.

In this way, the second transfer buffer 1b is brought into the writable state by the input of the write request signal WR, and the rewriting data DT1 and the address AD1 from the external processor 20 are sequentially written as shown in FIG. Then, the external processor 20 sends all data B06
When the writing of 4 to B127 is completed, the data related to the transfer is written to the second transfer control register 2b.

When the data writing to the second transfer buffer 1b and the second transfer control register 2b is completed, the second transfer control register 2b outputs the set signal STb to the set terminal S of the flip-flop circuit 6b. The output Q of the circuit 6b becomes a high level "1". The output Q of the high level "1" of the flip-flop circuit 6b causes the AND circuit 11 to output the OR circuits 13a, 1
Since the logical sum signal of high level "1" is input from 3b, the AND circuit 11 outputs the busy signal BUSY of high level "1" to the external processor 20. The external processor 20 which receives the busy signal BUSY of the high level "1" recognizes that the data writing to the first and second transfer buffers 1a and 1b is completed.

Next, the first and second transfer buffers 1a,
A case where the program data written in 1b is transferred to the microprogram storage means 32 will be described. When the data writing to the first transfer buffer 1a and the first transfer control register 2a is completed, the first transfer control register 2a outputs the set signal STa to the set terminal S of the flip-flop circuit 6a and at the same time the flip-flop circuit 8 The set signal STa is also output to the set terminal S. Then, the output Q of the flip-flop circuit 8 becomes a high level "1". On the other hand, since the output Q of the flip-flop circuit 7b is low level "0", the AND circuit 12 inputs the high level "1" through the inverting circuit 15. Therefore, the AND circuit 12 outputs the selection signal SE of high level “1” to the selector circuits 3 and 4 as a logical product signal of the signals of high level “1” from the flip-flop circuit 8 and the inverting circuit 15.

In response to the high-level “1” selection signal SE of the AND circuit 12, the transfer control circuit 5 takes in the transfer-related data stored in the first transfer control register 2 a via the selector circuit 4. Therefore, the transfer control circuit 5 determines the address A based on the data related to this transfer.
D2 and the output permission signal OE are output. Address AD2
Is commonly input to the first and second transfer buffers 1a and 1b, but the output enable signal OE is output by the selector circuit 3 as the output enable signal OE1.
Since it is input to the set terminal S of a, the flip-flop circuit 7a outputs the output enable signal OEa of high level "1" to the first transfer buffer 1a. Further, since the high level "1" output enable signal OEa of the flip-flop circuit 7a is simultaneously output to the reset terminal R of the flip-flop circuit 6a and the OR circuit 13a, the output Q of the flip-flop circuit 6a is low level "0". It is reset to ". However, the logical sum signal of the OR circuit 13a remains at the high level "1", and the AND circuit 11 continues to output the busy signal BUSY of the high level "1".

In this way, the high level "1" output enable signal OEa is input to the first transfer buffer 1a, and the second transfer buffer 1a
Output enable signal O of low level "0" to transfer buffer 1b
When Eb is input as shown in FIG. 4, the program data A000 is located at the bottom (0th stage) and the program data A255 is located at the top (256th stage) of the microprogram storage means 32. At the start of the sampling cycle, the transfer control circuit 5 outputs the write request signal WRP of high level “1” to the selector circuit 16.
Then, the program data B000 and subsequent data for rewriting in the first transfer buffer 1a are stored in the microprogram storage means 3
2 are sequentially supplied to the uppermost register (256th stage). Therefore, as shown in FIG. 5, the program data A000 to A062 in the micro program storage means 32 are the program data B for rewriting in the first transfer buffer 1a.
000 to B062 are sequentially rewritten, and finally, a quarter of the program data A000 to A063 in the micro program storage means 32 is replaced with the program data B000 to B063 in the first transfer buffer 1a.

When the transfer of the rewriting program data B000 to B063 in the first transfer buffer 1a is completed,
The transfer control circuit 5 outputs the transfer end signal TE of high level "1".
Is output to the reset terminal R of the flip-flop circuits 7a, 7b and 8. Then, the flip-flop circuit 7a is reset, its output Q becomes low level "0", and the low level "0" output enable signal OEa is output to the first transfer buffer 1a, the flip-flop circuit 6a and the OR circuit 13a. .. Therefore, the output of the first transfer buffer 1a is disabled, and the OR circuit 13a outputs a logical sum signal of low level "0". The low level “0” output of the OR circuit 13 a causes the AND circuit 11 to output the low level “0” busy signal BUSY to the external processor 20. The external processor 20 outputs the write request signal WR in response to the input of the low level “0” busy signal BUSY. This write request signal is input to the first transfer buffer 1a via the AND circuit 9.

On the other hand, since the flip-flop circuit 8 is reset to the low level "0" by the input of the transfer end signal TE, the logical product signal of the AND circuit 12 also becomes the low level "0" and the low level "0". The selection signal SE is input to the selector circuits 3 and 4. When the selection signal SE of low level “0” is input to the selector circuit 4, the transfer control circuit 5 takes in the data relating to the transfer stored in the second transfer control register 2 b via the selector circuit 4. The transfer control circuit 5 outputs the address AD2 and the output permission signal OE based on the data related to this transfer.
This output permission signal OE is input to the set terminal S of the flip-flop circuit 7b as the output permission signal OE2 by the selector circuit 3, so that the flip-flop circuit 7b outputs the output permission signal OEb of high level "1" to the second transfer buffer 1b. Output to. Also, the flip-flop circuit 7b
The output enable signal OEb of high level "1" is also simultaneously output to the reset terminal R of the flip-flop circuit 6b and the OR circuit 13b, so that the output Q of the flip-flop circuit 6b is reset to low level "0". But,
The OR signal of the OR circuit 13b is the flip-flop circuit 7
It remains at the high level "1" by the output permission signal OEb of the high level "1" of b.

In this way, the high level "1" output enable signal OEb is input to the second transfer buffer 1b, and
Output enable signal O of low level "0" to transfer buffer 1a
By inputting Ea, the program data A064 to A127 in the micro program storage means 32 are sequentially rewritten into the program data B064 to B127 for rewriting in the second transfer buffer 1b as shown in FIG. 4 in the microprogram storage means 32
One-half of the program data A064 to A127 is the program data B064 to B12 in the second transfer buffer 1b.
Rewritten to 7.

The AND circuit 11 outputs the low-level "0" busy signal BUSY to the external processor 20 while the rewriting program data B064 to B127 in the second transfer buffer 1b is being transferred. Therefore, the external processor 20 outputs the write request signal WR to the first transfer buffer 1a, and writes the remaining rewrite program data B128 to B191 to the first transfer buffer 1a. That is, the transfer control circuit 5 writes the program data in the second transfer buffer 1b into the microprogram storage means 32, and the external processor 2
The process of 0 writing the next data in the first transfer buffer 1a is executed in parallel.

Since the internal clock CL is faster than the write processing clock of the external processor 20, the processing of transferring the data in the second transfer buffer 1b to the microprogram storage means 32 is completed first. Then, the transfer control circuit 5 outputs the transfer end signal TE of high level “1” to the reset terminals R of the flip-flop circuits 7 a and 7 b and the flip-flop circuit 8. At this point, the flip-flop circuit 7a and the flip-flop circuit 8 have already been reset, so there is no change, but the flip-flop circuit 7b is reset to the low level "0" by the transfer end signal TE. In this way, the interface circuit 31 returns to the initial state.

When the external processor 20 writes the next program data B128 to B191 to the first transfer buffer 1a at the timing of the write clock of the external processor 20, the data write to the first transfer buffer 1a is completed. , This time external processor 2
0 is the program data B for the second transfer buffer 1b.
192 to B255 are written, and at the same time, the transfer control circuit 5 writes the program data B12 in the first transfer buffer 1a.
8 to B191 are written in the microprogram storage means 32. That is, this time, the transfer control circuit 5 writes the program data B128 to B191 in the first transfer buffer 1a to the micro program storage means 32, and the external processor 20 writes the program data B192 to B255 in the second transfer buffer 1b. Processing is executed in parallel. The timing of the write clock of the external processor 20 is the clock when the address AD1 and the program data DT1 are supplied to the first transfer buffer 1a.
The clock for writing data to a and 1b is the timing of the internal clock CL.

As described above, the microprogram storage means 32 is loaded from either the first transfer buffer or the second transfer buffer.
Alternatively, while the data is being transferred to the coefficient storage means 34, new data is written to the other transfer buffer from the external processor, so that the data writing time can be shortened. Further, both the first and second transfer buffers perform the writing and reading processes in synchronization with the operation clock inside the DSP, so that it is not necessary to adjust the timing of the operation clocks, and the rewriting process of the rewriting data can be performed more efficiently. It can be done at high speed.

Although the sound source DSP of the electronic musical instrument has been described as an example in the above embodiment, the application of the present invention is not limited to this, and envelope generation for audio, various digital filters, and electronic musical instrument is generated. It goes without saying that it can be applied to DSPs used in various fields such as circuits, precision control devices, high-definition TVs, and digital VTRs.

[0071]

As described above, according to the present invention, rewriting of microprograms and coefficients can be performed at high speed without hindering DSP processing.

[Brief description of drawings]

FIG. 1 is a diagram showing a detailed configuration of an interface circuit of FIG.

FIG. 2 is a block diagram showing a hardware configuration of an embodiment of an electronic musical instrument when the digital signal processor according to the present invention is used as a sound source.

FIG. 3 is a diagram showing a concept of a rewriting process of the microprogram in FIG. 1, and a diagram showing a first state thereof.

FIG. 4 is a diagram showing a concept of a rewriting process of the microprogram in FIG. 1, and a diagram showing a second state thereof.

5 is a diagram showing a concept of a rewriting process of the microprogram in FIG. 1, and a diagram showing a third state thereof.

FIG. 6 is a diagram showing a concept of a rewriting process of the microprogram in FIG. 1, and a diagram showing a fourth state thereof.

FIG. 7 is a diagram showing a concept of a rewriting process of a microprogram in a conventional technique, and a diagram showing a first state thereof.

FIG. 8 is a diagram showing a concept of a rewriting process of a microprogram in a conventional technique, and a diagram showing a second state thereof.

FIG. 9 is a diagram showing a concept of a rewriting process of a microprogram in a conventional technique, and a diagram showing a third state thereof.

FIG. 10 is a diagram showing a concept of a rewriting process of a microprogram in a conventional technique, and a diagram showing a fourth state thereof.

[Explanation of symbols]

1a ... 1st transfer buffer, 1b ... 2nd transfer buffer, 2
a ... 1st transfer control register, 2b ... 2nd transfer control register, 3, 4 ... Selector circuit, 5 ... Transfer control circuit, 6a,
6b, 7a, 7b, 8 ... Flip-flop circuit, 9, 1
0, 11, 12 ... AND circuit, 13a, 13b ... OR circuit, 14, 15 ... Inversion circuit, 16 ... Selector circuit, 20
... Microprocessor unit, 21 ... Program memory (ROM), 22 ... Working memory (RAM), 2
3 ... Keyboard, 24 ... Key switch circuit, 25 ... Key touch detection circuit, 26 ... Tone selection switch circuit, 27 ... Sound source D
SP, 28 ... Data and address bus, 31 ... Interface circuit, 32 ... Micro program storage means, 3
3 ... Coefficient utilization unit, 34 ... Coefficient storage means, 40 ... Sound system

Claims (1)

[Claims] 1. A microprogram storage means for storing a microprogram defining an algorithm, a coefficient storage means for storing a coefficient, and a digital signal arithmetic processing according to an algorithm defined by the microprogram using the coefficient. While using the coefficient utilization means, the microprogram and the coefficient rewriting data input from an external processor are temporarily stored, and the stored rewriting data is stored in the microprogram storage means and the coefficient storage means. And a first and second buffer means for performing the storage operation and the output operation based on the operation clock of the coefficient utilization means.