JP2765470B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for executing delay processing and various numerical calculation processing on an input digital signal by executing a plurality of microprograms.

[0002]

2. Description of the Related Art In recent years, the technology of a digital signal processor (digital signal processor (DSP)) for executing various numerical programs on an input digital signal by executing a plurality of microprograms has been advanced. At the same time, advancements in semiconductor manufacturing technology have made DSPLSI readily available.

[0003] For this reason, in recent electronic musical instruments, an effect imparting means for imparting one acoustic effect to a musical tone is defined as one block (hereinafter, referred to as an effector block), and an effect imparting device which is an aggregate of the effector blocks. To DSP
Some are built in and built in LSI. In such an electronic musical instrument, a player operates a panel switch or the like during a performance to set an arbitrary sound effect type in each effector block and to select a connection between each effector block. Can be.

[0004] The setting of the sound effect type and the selection of the connection between the effector blocks are performed in the electronic musical instrument by the C
A PU (Central Processing Unit) that configures the above-described effect imparting device in response to a player's operation of a panel switch or the like.
This is realized by setting or changing the type of the sound effect of each effector block used in the LSI and the microprogram relating to the connection between the effector blocks and transferring the program to DSPLSI.

[0005]

In the above-mentioned conventional DSPLSI, it is impossible to change only a part of the microprogram. Even if a part of the corresponding microprogram is changed, all microprograms including the changed part are DSPLS.
I had to be transferred anew.

The above-mentioned sound effects include modulation-type sound effects for modulating musical sounds such as distortion and reverberation-type sound effects for reverberating musical sounds such as reverb. In this case, it is necessary to delay digital musical sound data, and it is general to use an external delay RAM. In this case, as shown in FIG. 8A, the delay RAM is divided into a plurality of areas and used in correspondence with each effector block, and addresses are sequentially transferred from the address MAX of the delay RAM to the address 0. While changing, the tone data is delayed for each effector block, so that FIG.
As shown by the arrows, the boundaries of the use area of the delay RAM corresponding to each effector block also move sequentially.

Therefore, when the DSPLSI microprogram is changed, for example, when only the sound effect of a certain effector block is changed from chorus to distortion, all areas of the delay RAM have to be cleared. Thus, the delay RA
There is a disadvantage that it takes a long time to clear M, and that a tone cannot be generated while the delay RAM is being cleared.

The present invention has been made under such a background, and uses a storage means divided into a plurality of areas corresponding to a plurality of microprograms and executes each of the plurality of microprograms. Thus, in a signal processing device that performs delay processing and various numerical calculation processing on an input digital signal, when a part of a microprogram is changed, the signal is stored in an area of a storage unit corresponding to the changed microprogram. It is an object of the present invention to provide a signal processing device capable of erasing only a digital signal.

[0009]

According to the first aspect of the present invention,
A signal processing apparatus that performs a delay process and various numerical calculation processes on an input digital signal by executing a plurality of microprograms each including a plurality of steps in a time-division manner at a predetermined cycle has a plurality of addresses. ,
Storage means divided into a plurality of areas corresponding to the plurality of microprograms, and storage and reading of the digital signal in each area of the storage means provided for each of the plurality of divided areas of the storage means Address management means for managing the microprograms, etc .; instruction means for instructing a change of at least one microprogram of the plurality of microprograms; and information stored in the storage means area corresponding to the microprogram instructed by the instruction means. The digital signal from the microphone in the predetermined period.
B) During the execution time of the program,
Erase only the addresses corresponding to the number of steps in the
All the digital signals stored in the area are
If the erasure was not completed within one of the predetermined cycles,
Control means for controlling the address management means so as to erase the digital signal over the predetermined period .

According to a second aspect of the present invention, in the first aspect of the invention, the address management means has an address counter for delaying the input digital signal, and the address counter is provided with the digital signal. When erasing is performed, an address of an area where a digital signal to be erased is stored is specified . According to a third aspect of the present invention, in the first aspect of the invention, when changing the microprogram instructed by the instructing means, the mute means for muting the digital signal processed by the microprogram before the change is provided. Mute is released after the change.

[0011]

According to the first aspect of the invention, when the change of the microprogram is instructed by the instruction means, the control means is stored in the area of the storage means corresponding to the microprogram instructed by the instruction means. Digital signals of the microprogram in the predetermined cycle are
In the execution time, the steps of the microprogram
Address management so that only the addresses corresponding to the number
Control means. And at this time, it is stored in the area
All digital signals within one predetermined period.
If the erasure is not possible, the control means
To delete the digital signal over time.
Control the security management means. As a result, the
By only digital signals that have been erased Runode, it is not necessary to erase all digital signals all stored in the area storage means, it does not take time to erase the digital signal.

According to the second aspect of the present invention, in the first aspect of the present invention, the address of the digital signal to be erased is designated by the address counter. Only the digital signal stored in the area is deleted .
Further, according to the third aspect of the present invention, in the first aspect of the present invention, when changing the microprogram designated by the indicating means, the mute means changes the digital program processed by the microprogram before the change. Since the signal is muted and the muting is released after the microprogram is changed, there is no possibility that noise is output.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an effect imparting device to which a signal processing device according to an embodiment of the present invention is applied. In this figure, reference numeral 1 denotes an effect imparting device. In this embodiment, the effect imparting device 1 is built in an electronic musical instrument, and is configured to impart various sound effects such as reverb and chorus to a plurality of tone data output from a tone generator circuit. The electronic musical instrument includes, in addition to the effect imparting device 1 and the tone generator circuit, a CPU (central processing unit) 2 (see FIG. 1) for controlling each part in the electronic musical instrument, a keyboard, a ROM, a RAM,
A panel switch, a display, and a sound system for selecting and setting sound effects and the like, and a CPU bus 3 (see FIG. 1) for the CPU 2 to exchange data with the effect imparting device 1 and other units are provided. I have. Also, in FIG. 1, reference numeral 4 is externally attached to the effect applying device 1,
This is a delay RAM for delaying input tone data by a predetermined time and outputting the delayed tone data.

In the effect applying apparatus 1, reference numeral 5 denotes a microprogram memory in which a plurality of microprograms corresponding to a plurality of types of sound effects are stored, and reference numeral 6 denotes a low-frequency signal for controlling modulation of musical sound data such as vibrato and tremolo. Low frequency oscillator (LFO) for generating the modulation data (address modulation data for delay and amplitude modulation data)
O data register, LF related to control of LFO6
O data is transferred from the CPU 2 via the CPU bus 3 and stored.

Numeral 8 denotes an arithmetic unit, which is output from the tone generator circuit of the electronic musical instrument during one sampling time (hereinafter referred to as 1 DAC cycle) of the DA converter provided in the above-mentioned sound system of the electronic musical instrument, and performs data management. Part 9
In response to the musical tone data supplied through the CPU 2, the microprogram memory 5 is output from the CPU 2 based on the coefficient data supplied through the CPU bus 3 and the coefficient register 10 and the amplitude modulation data output from the LFO 6.
Microprograms for providing five types of sound effects supplied from the five effector blocks EF1 to EF5
(Not shown) in time division. The coefficient data includes an effect balance of each sound effect, a coefficient of a filter in a sound effect such as reverb, and the like. Here, the effect balance means the ratio of adding the musical sound data to which the sound effect is added (wet sound) and the musical sound data to which the sound effect is not added (dry sound).

FIG. 2A shows an example of the operation timing of the effect imparting device 1. In this embodiment, 1
The DAC cycle is composed of 0 to 255 steps (one step is the operation time of one control code of the microprogram). As described above, the calculation unit 8 executes five sound effects in the five effector blocks EF1 to EF5 during one DAC cycle. The program sizes of the five effector blocks EF1 to EF5 are fixed, and the effector blocks EF1 to EF5 are fixed.
Up to 5, there are 56 steps, 56 steps, 24 steps, 24 steps, and 96 steps.

Then, as shown in FIG.
In the C cycle, processing of the effector block EF1 is performed in steps 0 to 55, and steps 56 to 111 are performed.
Processing of effector block EF2 by step, 11
Processing of the effector block EF3 from 2 steps to 135 steps, processing of the effector block EF4 from steps 136 to 159, 160 steps to 2
The processing of the effector block EF5 is executed by 55 steps.

In FIG. 1, the data management unit 9
In addition to managing the input timing of the musical tone data output from the tone generator circuit of the electronic musical instrument and the output timing of the musical tone data to which the sound effect has been added to the sound system in the arithmetic section 8, the above-described five effector blocks EF1 to EF5 are used. Manage connections between. Reference numeral 11 denotes a 256-stage delay address register. Delay address data corresponding to the address of the delay RAM 4 is transferred from the CPU 2 via the CPU bus 3 and stored.

The delay address register 11,
LFO data register 7 and coefficient register 1 described above
0 has an address of 0 to 255, and each data stored at each address is always read in accordance with the operation of the arithmetic unit 8 described above. Further, as the data of the address “0” is used in the 0 step of the operation unit 8, the step of the operation unit 8 and the address of each register have a one-to-one correspondence. Further, each register is used by being divided into five areas corresponding to the effector blocks EF1 to EF5.

Reference numeral 12 denotes a delay address management unit which is written to the delay RAM 4 based on the delay address data stored in the delay address register 11 and the delay address modulation data output from the LFO 6.
Alternatively, it manages an address to which musical tone data read from the delay RAM 4 should be written or read. Reference numeral 13 denotes a memory control unit that controls writing and reading of musical sound data to and from the delay RAM 4.

In this embodiment, the microprogram memory 5 stores microprograms corresponding to a total of 11 types of acoustic effects such as chorus, flanger, and symphonic, as shown at the left end of FIG. When the player selects five sound effects from the total of eleven kinds of sound effects for each of the effector blocks EF1 to EF5, a microprogram corresponding to the selected five sound effects is stored. If each head address of the memory 5 is CP
Each of the effector blocks E is transferred from the U2 via the CPU bus 3 and stored in the head address register 14 shown in the right end of FIG.
Register areas 14a to 14e corresponding to F1 to EF5
Is temporarily stored. FIG. 3 shows the effector block EF1.
, Chorus as the sound effect of the effector block EF2,..., Reverb as the sound effect of the effector block EF5, and the respective start addresses are stored in the corresponding register areas 14a to 14e. It is shown that.

As described above, since the program size of each of the effector blocks EF1 to EF5 is fixed, the performer can select each of the effector blocks EF1 to EF5.
5, not all sound effects corresponding to the eleven kinds of microprograms stored in the microprogram memory 5 can be selected, but some sound effects corresponding to microprograms each having a corresponding program size. You will have to choose from the effects.

In FIG. 3, reference numeral 15 denotes an address counter. When each head address is read from each of the register areas 14a to 14e of the head address register 14 and supplied, the counting is started from the head address. The count value is supplied to the microprogram memory 5 as address data. As a result, the corresponding microprogram is read from the microprogram memory 5 and supplied to the arithmetic unit 8 described above.

Here, the operation of this embodiment will be briefly described. Tone data input from a sound source circuit (not shown) to the effect imparting device 1 includes a delay by the delay RAM 4,
A predetermined calculation or the like is performed by the calculation unit 8 to give a desired sound effect. As shown in FIG. 8 (b), the delay RAM 4 has 5 corresponding to the effect blocks EF1 to EF5.
One memory bank 4 is divided into _{1-4 5} used, but the boundaries of the banks 41 _{to 5} is fixed. That, TAD1～TA the start address of each bank ₄₁ to _5, respectively
When D5, bank 4 ₁ TAD1 (address 0) to
TAD2-1, bank 4 ₂ TAD2~TAD3-1,
Bank 4 ₃ TAD3~TAD4-1, bank 4 ₄ TA
D4~TAD5-1, bank 4 ₅ is a TAD5~ address MAX.

The banks 4 ₁ to 4 _{5 of} the delay RAM 4 are also provided.
Is the number of data that can be stored, respectively, TAD2-TAD
1, TAD3-TAD2, TAD4-TAD3, TAD
5--TAD4, address MAX-TAD5 + 1. Here, for the convenience of the circuit of the delay address management unit 12, the bank size value obtained by subtracting 1 from the number of storable data in each bank 41 _{to 5} delay RAM 4 BS1～B
Defined as S5. Thereby, the bank sizes BS1 to B
S5 is BS1 = (TAD2-TAD1)-
1, BS2 = (TAD3-TAD2) -1, BS3 =
(TAD4-TAD3) -1, BS4 = (TAD5-T
AD4) -1, BS5 = address MAX-TAD5.

The writing of the tone data into the delay RAM 4 is performed by writing the tone data supplied from the data management unit 9 to the write address designated by the delay address management unit 12, and reading the tone data. Is performed by reading out the tone data stored at the read address specified by the delay address management unit 12 and outputting the data to the data management unit 9.

The delay address management unit 12 stores the write address and the read address in the effector block EF.
Independently managed for each of 1 to EF5. Write address, the last address of each bank ₄₁ to ₅ (e.g., bank 4 ₁
For, counts down from address TAD2-1) per 1DAC cycle, the start address (e.g., if the bank 4 ₁ and is counted down to address TAD1), the following back to the last address, and is counted down as well.

FIG. 4 is a block diagram showing the configuration of the delay address management section 12. As shown in FIG. In this figure, 16 ₁
To 16 ₅ are five effecter blocks EF1~
EF5 to a memory bank address counter provided corresponding functions as an address counter for each bank ₄₁ to ₅ in the normal mode, the memory clear mode, to clear the memory bank to be clear of the subject Generate address. Also, each memory bank address counter 16 ₁ to 16 _5, based on the memory clear instruction CLR1~CLR5 like supplied for each effector blocks EF1~EF5 via the CPU bus 3 from CPU 2, the effector block EF1~ each bank of delay RAM4 corresponding to EF5 4 ₁ to 4 ₅ memory clear signal for clearing the data (FIG. 8 (b) refer) MC
It outputs LR and the like.

Address counter 1 for memory bank in FIG.
In 6 ₁ , reference numeral 17 denotes a differentiating circuit for differentiating the memory clear instruction CLR 1 shown in FIG. 5B to output a negative logic differential signal DEF shown in FIG. 5C, and 18 a last step of one DAC cycle 255. The last step signal LSTP (see FIGS. 2B and 5 (10)) which becomes “1” only at the time of the step is an input terminal supplied from the CPU 2 via the CPU bus 3.

Reference numeral 19 denotes a differential signal DEF, a last step signal LSTP, and an output signal of an AND gate 26, which will be described later, and a negative logic in synchronization with the rise of the last step signal LSTP input after the output signal of the AND gate 26 is input. The clear circuit 20 outputs the clear signal CLO (see FIG. 5 (5)), and outputs a clear enable signal CLE of "1" in synchronization with the rise of the differential signal DEF, and in synchronization with the rise of the clear signal CLO. This is a memory clear mode register that outputs a clear enable signal CLE1 of “0” (see FIG. 5 (6)).

Reference numeral 21 denotes a selector, to which the last step signal LSTP is inputted to the A input terminal and 1DA is inputted to the B input terminal.
In the C cycle, only the processing steps of the effector block EF1, that is, a period of 0 to 55 steps, "
The effector bank number EBN1 which becomes 1 "(FIG. 2
(C) and FIG. 5 (7)) are inputted from the CPU 2 via the CPU bus 3, and the clear enable signal CLE1 is inputted.
Is "1", the effector bank number EBN1 is selected, and when the clear enable signal CLE1 is "0", the last step signal LSTP is selected, and the counter enable signal CE (enables the counting operation of the counter 24 described later). 5 (8)).

Reference numeral 22 denotes a NAND gate to which a clear enable signal CLE1 is input to a first input terminal and an output signal of an AND gate 26 to be described later is input to a second input terminal.
The first input terminal receives the output signal of the NAND gate 22, the second input terminal receives the differential signal DEF, the third input terminal receives the clear signal CLO, and the negative clear signal NCR (see FIG. 4) is an AND gate that outputs (1).

A clock 24 (see FIG. 5 (1)), one cycle of which is equal to the above-described one step, output from a clock generation circuit (not shown) is input to a delay RAM 4 corresponding to the effector block EF1. Bank 4 ₁ (FIG. 10)
(See (b)). The counter counts the relative address of the counter. The counting operation is enabled by the counter enable signal CE, and the negative clear signal N
The count value is cleared by CR.

A comparator 25 compares the count value of the counter 24 input to the first input terminal with the above-mentioned bank size BS1 input to the second input terminal, and compares these values. When they match, a match signal EQ (see FIG. 5 (9)) is output. As shown in FIG. 2 (h), the bank size BS1 is obtained from a 5-stage shift register (not shown) by 1D
In the AC cycle, it is output only for the processing step of the effector block EF1, that is, for the period of 0 to 55 steps. The same applies to other bank sizes BS2 to BS5.

An AND gate 26 receives an effector bank number EBN1 from a first input terminal and a match signal EQ from a second input terminal. 27 denotes a three-state buffer, and a clear enable signal CLE1 and a counter 24. , And output in three states, that is, a state of “1”, a state of “0”, and a high impedance state. The output signal corresponding to the clear enable signal CLE1 is output as the memory clear signal MCLR, and the count value of the counter 24 is output as count data CD1. Also,
The three-state buffer 27 has an effector bank number E
When BN1 is not input, the state becomes a high impedance state. Thus, the effector bank number EB
While N1 is being input (that is, steps 0 to 55)
The memory clear signal MCLR and the count data CD1 are output from the three-state buffer 27 only during the step). The memory bank address counter 1
6 _{2-16 5,} the address for the memory bank counter 16 ₁
Since it has the same configuration and the same function as described above, the description thereof is omitted.

In FIG. 4, reference numeral 28 adds the delay address data AD output from the delay address register 11 shown in FIG. 1 and the delay address modulation data AMD output from the LFO 6 shown in FIG. Adder, 2
9 is the output data of the adder 28 and the bank sizes BS1-B.
This is a remainder computing unit that performs remainder computation with S5.

In the remainder arithmetic unit 29, reference numeral 30 denotes an inverter for inverting the bits of the bank sizes BS1 to BS5;
Reference numeral 1 denotes an adder to which "0" is input to the carry data input terminal CI and that adds the output data of the adder 28 and the output data of the inverter 30.
Are based on the output data of the adder 28,
A subtractor for subtracting BS5 is configured. It should be noted that the carry data input terminal CI of the adder 31 should have "
1 "must be entered, but the bank size BS1
Since BS5 is smaller than the original bank size by one, by inputting "0" to the carry data input terminal CI of the adder 31, subtraction of the output data of the adder 28 from the original bank size is realized. ing.

Reference numeral 32 denotes a selector. The output data of the adder 28 is input to the A input terminal, the output data of the adder 31 is input to the B input terminal, and "1" is output from the carry data output terminal CO of the adder 31. Is output, the adder 3
The output data of the adder 28 is selected and output. Otherwise, the output data of the adder 28 is selected and output. Remainder 29
In short, if the output data of the adder 28 is smaller than the value of the original bank size BS1 to BS5, the output data of the adder 28 is output as it is, and the output data of the adder 28 becomes the original bank size. If the value is equal to or larger than the value of BS1 to BS5, the output data of the adder 31 is output.

In this embodiment, as described above, each of the effector blocks EF1 to EF5 includes a corresponding _{one of the} banks 4 ₁ to ₄ 4 of the delay RAM 4 as shown in FIG.
The address is sequentially changed from the last address to the first address, and when the address is changed to the first address, the address jumps to the last address, and the address is sequentially changed again toward the first address. . Also, to clear the respective bank ₄₁ to ₅ a corresponding delay RAM4 when switching the sound effect of the effector block EF1～EF5, the same address and if we delay the tone data described above Make changes. The remainder arithmetic unit 29 and the remainder arithmetic unit 37 described later are provided for performing the address change described above.

Reference numeral 33 denotes an inverter for inverting the memory clear signal MCLR. Reference numeral 34 denotes an output data of the remainder operation unit 29 when the output data of the inverter 33 is "1", that is, when the memory clear signal MCLR is "0" (normally). In the mode), a gate to be passed through is a subtractor 35, and A is obtained from bank sizes BS1 to BS5 input from the B input terminal.
The count data CD1 to CD5 input from the input terminal are subtracted.

36 is the output data of the subtractor 35 and the gate 3
An adder 37 for adding the output data of No. 4 is provided with a remainder arithmetic unit 37 having the same configuration and the same function as the remainder arithmetic unit 29. Numeral 38 denotes an adder, which outputs the output data of the remainder arithmetic unit 37 and FIG.
As shown in (i), start address data TAD output from a delay RAM start address register (not shown) (five stages) for a period corresponding to the processing steps of each of the effector blocks EF1 to EF5 in one DAC cycle.
1 to TAD5, and the result of addition is supplied to the address terminal ADS of the delay RAM 4 as corrected address data MAD. Note that, as described above (see FIG. 8B), the delay RAM 4 stores the effector blocks EF1 to EF.
5 is divided into five banks ₄₁ to ₅ correspond been used, the start address data TAD1~ of the banks ₄₁ to ₅
The TAD 5 is stored in the delay RAM start address register described above in advance.

FIG. 6 is a block diagram showing the structure of the memory control unit 13. In this figure, reference numeral 39 denotes a selector, which inputs the tone data MTD output from the data management unit 9 to the A input terminal, inputs "0" to the B input terminal, and sets the memory clear signal MCLR to "1". ,
"0" is selected and supplied to the data input terminal DTA of the delay RAM 4. Reference numeral 40 denotes a selector, which receives a control code CCD constituting a microprogram from the A input terminal, and outputs "0" from the B input terminal. When the input memory clear signal MCLR is "1", "0", that is, data write is selected and supplied to the write / read control terminal NW / R of the delay RAM 4. Further, as described above. Then, the corrected address data MAD output from the delay address management unit 12 is supplied to the address terminal ADS of the delay RAM 4. As a result, the memory clear signal MCLR becomes "1".
At this time, the data at the address specified by the modified address data MAD is cleared.

In such a configuration, an outline of the operation when the sound effect of the effector block EF1 is switched from symphonic to pitch change, for example, as shown in FIG. 7, will be described. When the player operates a panel switch or the like (not shown) during the performance to instruct the effector block EF1 to switch the sound effect type from symphonic to pitch change,
First, the CPU 2 of the electronic musical instrument instructs the data management unit 9 to mute the output level of the effector block EF1, as shown in FIG. Thereby, the data management unit 9
By the interpolation function, the output level of the effector block EF1 is gradually reduced as shown in FIG. Since the output level can be muted for each effector block, when simultaneously switching the effects of a plurality of effector blocks, the output levels of the corresponding effector blocks are muted.

Next, the CPU 2 executes the effector block E
When the output level of F1 becomes “0”, the memory clear instruction CLR1 corresponding to the effector block EF1 is issued to the CPU.
After the transfer to the delay address management unit 12 via the bus 3, the sound effect is switched. More specifically, the symphonic start address written in the register area 14a of the start address register 14 shown in FIG.
The effector block E of the LFO data register 7, coefficient register 10, and delay address register 11 shown in FIG.
In the bank corresponding to F1, LF related to pitch change
O data, coefficient data and address data for delay are written.

On the other hand, the delay address management unit 12
When the memory clear instruction CLR1 is input, as described below, clearing written into bank 4 ₁ of the delay RAM4 data. Further, the CPU 2 outputs the clear enable signal CLE1 output from the delay address management unit 12.
There periodically scans whether or not it is "0", if it has been clear enable signal CLE1 is "0", it is determined that the clearing of the bank 4 ₁ of the delay for RAM4 has been completed, Unmute. As a result, as shown in FIG. 7, the output level of the pitch change gradually increases immediately after the mute is released.

Next, the delay address management unit clears the written in the bank 4 ₁ of the delay RAM4 data 12
Will be described. First, when a clear instruction CLR1 (see FIG. 5 (2)) is transferred from the CPU 2 via the CPU bus 3, the differentiating circuit 17 differentiates the clear instruction CLR1 and differentiates the negative logic shown in FIG. 5 (3). The signal DEF is output. Next, the memory clear mode register 20 outputs a clear enable signal CLE1 (see FIG. 5 (6)) of “1” in synchronization with the rise of the differential signal DEF.
The “1” clear enable signal CLE1 is supplied to the “1” memory clear signal MC via the three-state buffer 27.
Since it is output as LR, the delay address management unit 12 enters the memory clear mode, as shown in the lowermost part of FIG. Further, the output signal of the AND gate 23, that is, the negative clear signal NCR also falls in synchronization with the fall of the differential signal DEF, so that the count value of the counter 24 is cleared.

In this state, one DAC cycle ends after a lapse of time, and after the last step signal LSTP shown in FIG. 5 (10) is input, the effector bank number EBN1 corresponding to the effector block EF1 is obtained.
When (see FIG. 5 (7)) is input, the selector 21
Now, with the clear enable signal CLE1 of “1”, B
The input end side, that is, the effector bank number EBN1
Is selected, the effector bank number EBN1
Is output as a counter enable signal CE to enable the counting operation of the counter 24. This allows
The counter 24 starts a counting operation in synchronization with the clock φ, and outputs the count value (value 1 at the time of the first clock φ) as count data CD1 to the A input terminal of the subtractor 35 via the three-state buffer 27. Supply.

Now, since the memory clear signal MCLR is "1", the output data of the inverter 33 is "0" and the gate 34 is closed. Meanwhile, FIG.
As shown in (h), a five-stage shift register (not shown) outputs an effector block E in one DAC cycle.
The bank size BS1 is output only for the processing steps of F1, that is, for the period of 0 to 55 steps, and is supplied to the delay data management unit 12.

Therefore, the count data CD1 (value 0 at the first clock φ from the start of memory clear) is subtracted from the bank size BS1 in the subtracter 35,
The result of the subtraction is input to the remainder calculator 37 via the adder 36. Next, the remainder operation unit 37 performs a remainder operation on the subtraction result of the subtractor 35 and the bank size BS1. In the memory clear mode, since the gate 34 is closed as described above, the subtraction result of the subtractor 35 is smaller than the bank size BS1, and the subtracter 3
5 (the first clock φ from the start of memory clear)
Value corresponding to the bank 4 ₁ of the last address (TAD2-1) of delay RAM 4) is directly output when,
The data is input to the adder 38, and the adder 38 adds the head address data TAD1 (address 0) output from the delay RAM head address register (not shown) to output the corrected address data MAD.

Next, the corrected address data MAD is
Is input to the memory control unit 13 shown in FIG. In this case, since the memory clear signal MCLR is input to the memory control unit 13, the selectors 39 and 4
0 selects both "0" input from the B input terminal and supplies them to the data input terminal DTA and the write / read control terminal NW / R of the delay RAM 4, respectively. At the first clock φ from the start of memory clear, the delay RAM
4 banks 4 ₁ of the last address (TAD2-1) to data "0" is written, i.e., tone data bank 4 ₁ of the final address of the delay for RAM4 (TAD2-1) is cleared.

The above-described operation is performed a period in which the effector bank number EBN1 delay address management unit 12 is inputted (see FIG. 5 (7) and (8)), the bank 4 ₁ of the delay RAM4 final Address (TAD2-
After the tone data for a total of 56 addresses from 1) to the address having a value smaller by 55 is cleared and the effector bank number EBN1 is no longer input to the delay address management unit 12, the count enable signal CE becomes "0".
Therefore, the counter 24 stops the counting operation. Thus, the memory clear operation stops.

When one DAC cycle ends after a lapse of time and the effector bank number EBN1 is again input to the delay address management unit 12, the counter 2
4, from the count value obtained by counting the memory clear operation immediately before the end of the previous 1DAC cycle, since starts counting again, between the new 1DAC cycle, the last address of the bank 4 ₁ of the delay RAM4 (TAD2-
The tone data for a total of 56 addresses from the address whose value is smaller by 1 to value 56 from the last address (TAD2-1) to the value which is smaller by value 111 is cleared.

[0053] Thus, in the 1DAC cycle, since the address component corresponding to the number of each step of the effector block EF1~EF5 only each bank ₄₁ to ₅ delay RAM4 not clear, several DAC cycles, All tone data in the bank of the delay RAM 4 corresponding to the effector block EF for which the switching of the sound effect has been instructed is cleared.

In the memory clear mode,
When the count value of the counter 24 becomes equal to the bank size BS1 while the effector bank number EBN1 is being input, the value is supplied to the A input terminal of the subtractor 35 as count data CD1. Therefore, the count data CD1 (bank size BS1) is subtracted from the bank size BS1 in the subtracter 35, and the result of the subtraction (value 0) is input to the remainder calculator 37 via the adder 36. Next, in the remainder operation unit 37, the remainder operation of the subtraction result (value 0) of the subtractor 35 and the bank size BS1 is performed. In this case, the subtraction result (value 0) of the subtractor 35 is
Since the size is smaller than the bank size BS1, the subtracter 3
5 (value 0) is output as it is, and
And a delay RAM (not shown) in the adder 38.
Is added to the start address data TAD1 output from the start address register for
Is output as the modified address data MAD.

Next, the corrected address data MAD (head address data TAD1) is input to the memory control unit 13 shown in FIG. In this case, since the memory clear signal MCLR is input to the memory control unit 13, the selectors 39 and 40 both select “0” input from the B input terminal, and respectively select the delay R
AM4 data input terminal DTA and write / read control terminal N
W / R. Thus, data "0" is written to the start address of the bank 4 ₁ of the delay RAM 4. Namely, the tone data of all the addresses of the banks 4 ₁ of the delay RAM4 is cleared.

When the count value of the counter 24 becomes equal to the bank size BS1, the comparator 45 outputs the coincidence signal EQ as shown in FIG. 5 (9), so that the output signal of the AND gate 26 becomes "0". To "1", and this signal is input to the second input terminal of the NAND gate 22. On the other hand, a clear enable signal CLE1 of “1” output from the memory clear mode register 20 is input to a first input terminal of the NAND gate 22. Therefore, the output signal of the NAND gate 22 becomes "
From 1 "to" 0 ", the output signal of the AND gate 23, that is, the negative clear signal N
Since the CR also falls as shown in FIG. 5D, the count value of the counter 24 is cleared.

The output signal of the AND gate 26 is input to the clear circuit 19. The clear circuit 19 stores the coincidence signal EQ, and outputs a clear signal CLO in synchronization with the rise of the last step signal LSTP when the current one DAC cycle ends. Therefore, the output signal of the AND gate 23, that is, the negative clear signal NCR also falls in synchronization with the fall of the clear signal CLO as shown in FIG.
The count value of the counter 24 is cleared.

[0058] As described above, the time since the tone data of the bank 4 ₁ of the delay RAM4 over several DAC cycles is cleared, the tone data of all the addresses of the banks 4 ₁ of the delay RAM4 is cleared, That is, the point at which the comparator 25 outputs the coincidence signal EQ is when the effector bank number EBN1 is "1", as shown in FIG. At this time, since the microprogram is executing the effector block 1,
If the mode is immediately switched from the memory clear mode to the normal mode for accessing the delay RAM 4 by a microprogram, noise may be output.

[0059] Therefore, in this embodiment, as shown in FIG. 5, and continues the memory clear mode even tone data is cleared of all the addresses of the banks 4 ₁ of the delay RAM 4, indicating the end of 1DAC cycle When the last step signal LSTP is input, the clear circuit 19 outputs the clear signal CLO, and based on the clear signal CLO, the memory clear mode register 20 changes the clear enable signal CLE1 from "1" to "0". Lower, and shift from the memory clear mode to the normal mode.

Thus, the clear enable signal CLE
As described above, when the clear enable signal CLE1 is "0", the CPU 2, which periodically scans whether 1 is "0" or not, determines whether the delay RA
It is determined that the clearing bank 4 ₁ M4 is completed, since unmute, as shown in FIG. 7, the output level of the pitch change immediately after unmute gradually increases. Above description relates clear tone data stored in the bank 4 ₁ of the delay RAM 4,
It is of course carried out similar processing with regard clear tone data stored in the other bank 4 _{2-4 5.}

Next, the operation of the delay address management section 12 in the normal mode will be described. In the normal mode, each memory bank address counter 16 _{1 to} 16
Reference numeral _{5 functions} as an address counter for counting addresses of the respective bank sizes BS1 to BS4. That is, the memory bank address counters 16 _{1 to} 16 ₅ are respectively 0 to BS1, 0 to BS2, 0 to BS3, 0 to BS4,
The address of 0 to BS5 is output. The total number of addresses to be output is equal to the original bank size because each of the bank sizes BS1 to BS5 is smaller than the original bank size by one.

In the normal mode, the clear commands CLR1 to CLR5 supplied from the CPU 2 are always "0" (FIG. 5).
(2)), the differential signal DEF output from the differentiating circuit 17 is always "1" (see FIG. 5C), and the clear enable signal CLE1 output from the memory clear mode register 20 is also "1". 0 "(see FIG. 5 (6)). As a result, in the normal mode, the selector 21
Always supplies the last step signal LSTP input from the A input terminal to the count enable input terminal CE of the counter 24 as the counter enable signal CE.

Thus, the counting operation of the counter 24 is enabled only when the last step signal LSTP is "1", so that the counter 24 counts up in synchronization with the rise of the clock φ. Last step signal LST
When P is "1", there is only one rise of the clock φ, and as a result, the counter 24 counts up by 1 at the end of one DAC cycle (see FIGS. 5 (1) and (10)).

[0064] The comparator 25 of the memory bank address counter 16 _1, and the count value of the counter 24, which compares the bank size BS1 supplied in this count value and the time division, the count value of the counter 24 is a bank When the size becomes equal to the size BS1, the comparator 45 raises the coincidence signal EQ from "0" to "1" as shown in FIG. 5 (9) and supplies the same to the second input terminal of the AND gate 26. On the other hand, since the effector bank number EBN1 is supplied to the first input terminal of the AND gate 26, the output signal of the AND gate 26 becomes "1" while the effector bank number EBN1 is "1". That is, the coincidence signal E
Q becomes "1", and the output signal of the AND gate 26 becomes "1" only when the microprogram is executing the processing of the effector block EF1.

Next, the clear circuit 19 includes the AND gate 2
After the output signal of No. 6 becomes "1", the clear signal CLO falls from "1" to "0" in synchronization with the rise of the last step signal LSTP, as shown in FIG. Therefore, the output signal of the AND gate 23, that is, the negative clear signal NCR also falls in synchronization with the fall of the clear signal CLO, as shown in FIG. 5D, so that the count value of the counter 24 is cleared.
Since the counter 24 continues the counting operation even after being cleared, in the normal mode, the counter 24 repeats the counting operation between the count value 0 and BS1. The operation described above is performed by the memory bank address counter 16 ₂
It performed also in to 16 _5.

The count value of the counter 24 passes through the three-state buffer 27 only when the effector bank number EBN1 input to the three-state buffer 27 is "1" (that is, during the period of steps 0 to 55). It is input to the A input terminal of the subtractor 35 as CD1. Meanwhile, effector bank number EBN1
Subtraction but when it is "0", the 3-state buffer 27 is a high impedance state, among the other memory bank address counter 16 _{2-16 5,} any one of outputs count data CD2~CD5 To the A input of the unit 35. That is, the count data CD1 to CD5 are supplied to the A input terminal of the subtractor 35 in a time sharing manner.

The subtractor 35 counts the count data CD1 to CD5 from the bank sizes BS1 to BS5 supplied in a time-division manner.
5 is sequentially subtracted and output within one DAC cycle. The function of the subtractor 35 is to count data CD1 to CD5.
In the opposite direction. That is, the count value 0 → BS1, 0 → BS2, 0 → BS3, 0 → BS4
Change 0 → BS5, BS1 → 0, BS2 → 0, BS3
→ 0, BS4 → 0, BS5 → 0.

On the other hand, the adder 28 receives the delay address data AD and the delay address modulation data AMD and adds them. The remainder operation unit 29 compares the output data of the adder 28 with the bank sizes BS1 to BS5, and outputs the output data of the adder 28 to the original bank sizes BS1 to BS5.
If the output data of the adder 28 is smaller than the original bank size BS1 to BS5, the output data of the adder 31 is output. That is, a result obtained by subtracting the value of the original bank size from the output data of the adder 28 is output.

The function of the remainder operation unit 29 is to control input data output from the adder 28, that is, address data, so as not to be larger than the bank size. This processing is performed so that the delay address data AD is set in advance so as not to exceed the bank size. However, the addition result of the delay address data AD and the delay address modulation data AMD exceeds the bank size. This is because there are times when it does.

Similarly, the remainder operation unit 37 controls the addition result of the output data of the subtractor 35 and the output data of the remainder operation unit 29 so as not to be larger than the bank size. Finally, the output data of the remainder operation unit 29 is added to the top address data TAD1 to TAD5 supplied in a time division manner in the adder 38, and the corrected address data M
The signal AD is supplied to the address terminal ADS of the delay RAM 4 through the memory control unit 13 shown in FIG.

In the memory control section 13 shown in FIG. 6, the memory clear signal MCLR is set to "
Since the value is "0", the selectors 39 and 40 respectively select the data input from the A input terminal.
The tone data MTD supplied from the data management unit 9 is supplied to a data input terminal DTA of the delay RAM 4, and the control code CCD read from the microprogram memory 5 shown in FIG. End NW /
Supplied to R.

As described above, in the normal mode, the memory bank address counters 16 _{1 to} 16 ₁
Reference numeral _{5 functions} as an address counter for counting each bank size every DAC cycle. And the subtractor 35
, Each memory bank address counter 16 ₁ to 16
16 ₅ traveling direction of the count value is changed in the opposite direction, in the adder 38, by being added to the start address data TAD1~TAD5 of the banks ₄₁ to _5, FIG. 8
The change of the address shown in (b) is realized.

The principle of various types of sound effect processing performed in the normal mode is well known, and a description thereof will be omitted. For example, a modulation type sound effect such as a chorus is disclosed in US Pat. No. 4,569,268. Please refer to US Pat. No. 4,570,523 for reverberation type sound effects such as reverb.

As described above, according to the above-described embodiment, the memory clear address used in memory clear and the address used in normal mode are set to the same memory bank address counter 16.
Since occurred in ₁ to 16 _5, it is possible to suppress an increase in circuit scale. In addition, since the memory clear is executed by hardware without preparing a microprogram for memory clear, the load on the CPU 2 can be reduced. Furthermore, when the sound effect is changed, the execution period of the microprogram of the target effector block is used to clear the memory, so that the memory can be cleared in a minimum time.

In the circuit shown in this embodiment, the corresponding memory block is cleared while the microprogram of the effector block for changing the effect is being executed.
This clearing speed is one address for one step execution. This means that writing to the delay RAM 4 is 1
This is because the speed is completed in the execution time of the step.
By the way, a RAM having a slow writing speed, for example, a RAM which takes two or more steps to clear one address may be used as the delay RAM 4, but the present invention is also applied to such a case. it can.
In short, it is only necessary to use the execution time of the microprogram to be changed in one DAC cycle to clear a plurality of addresses of the corresponding memory block, thereby completing the clearing of the memory block in the minimum time. it can.

In the above-described embodiment, the same number of memory bank address counters 16 as the effector blocks EF1 to EF5 are provided, and the memory clear signal M is provided.
Although an example in which CLRs and the like are generated in parallel is shown, one memory bank address counter 16 is operated in a time-division manner,
The memory clear signal MCLR and the like may be generated in a time division manner.

Further, in the above-described embodiment, the case where the effect of one effector block is changed has been described. However, the present invention is not limited to this, and the case where the effect of two or more effector blocks is changed at the same time is also described. This can be explained by the circuit of this embodiment.

[0078]

As described above, according to the present invention,
When a part of the microprogram is changed, there is an effect that only the digital signal stored in the area of the storage means corresponding to the changed microprogram can be erased. Therefore, when the signal processing device according to the present invention is used as an effect imparting device for an electronic musical instrument, there is no need to clear the storage means corresponding to the microprogram that has not been changed, and the time for erasing the digital signal in the storage means is eliminated. In addition, since the microprogram that has not been changed is running, there is an effect that the musical sound is not interrupted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an effect applying device to which a signal processing device according to an embodiment of the present invention is applied.

FIG. 2 is a diagram illustrating an example of various data and signals supplied to each unit of an operation timing and delay address management unit 12 of the effect imparting device 1.

FIG. 3 is a block diagram showing a more detailed configuration of a microprogram memory 5, a head address register 14, and an address counter 15 of FIG.

FIG. 4 is a block diagram illustrating a configuration of a delay address management unit 12 of FIG.

5 is a diagram illustrating an example of various data and signals supplied to and output from each unit of the delay address management unit 12 in FIG.

FIG. 6 is a block diagram illustrating a configuration of a memory control unit 13 of FIG.

FIG. 7 is a diagram for explaining an outline of an operation when switching sound effects in one embodiment of the present invention.

FIG. 8 is a diagram for explaining inconveniences of the conventional technology and features of the present invention.

[Explanation of symbols]

1 ...... effect imparting device, 2 ...... CPU, 3 ...... CPU bus, 4 ...... delay for RAM, 4 ₁ ~4 ₅ ...... bank, 5 ......
Microprogram memory, 6 LFO, 7 LF
O data register, 8 arithmetic section, 9 data management section, 10 coefficient register, 11 address register for delay, 12 address management section for delay, 13 memory control section, 14 Start address register, 1
4a to 14e: Register area, 15: Address counter, 16 _{1 to} 16 _5: Address counter for memory bank, 17: Differentiating circuit, 18: Input terminal, 19 ...
Clear circuit, 20: Memory clear mode register, 2
1, 32, 39, 40 ... selector, 22 ... NAND gate, 23, 26 ... AND gate, 24 ... counter, 25 ... comparator, 27 ... 3-state buffer, 2
8, 31, 36, 38 ... adder, 29, 37 ... remainder operation unit, 30, 33 ... inverter, 34 ... gate,
35 ... Subtractor.

Claims (3)

(57) [Claims] By running in time division 1. A plurality of micro-program of each plurality of steps every predetermined period, the signal processing apparatus for performing a delay process and various numerical processing on the input digital signal, a plurality has address, the plurality of micro-program storing means being divided into a plurality of areas in correspondence with the provided plurality of divided the each region of said storage means, each of said storage means of said digital signal Address management means for managing storage and readout to and from the area; instruction means for instructing a change of at least one of the plurality of microprograms; and storage corresponding to the microprogram instructed by the instruction means said digital signal stored in the area of the means, the micro in the predetermined period Log
During the execution time of the program,
Erase by the address corresponding to the number of steps
All the stored digital signals are
If the erasure was not completed within a predetermined period,
Control means for controlling the address management means so as to erase the digital signal over a period . 2. The address management means has an address counter for delaying the input digital signal. The address counter stores a digital signal to be erased when the digital signal is erased. 2. The signal processing apparatus according to claim 1, wherein an address of the area in which the signal is written is indicated. 3. The method according to claim 1, further comprising: when changing the microprogram instructed by said instruction means, mute means for muting the digital signal processed by the microprogram before the change, and canceling the mute after said change. The signal processing device according to claim 1, wherein: