JPH0553667A - Voltage level decision circuit for semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the waiting power consumption by stopping the operation of the voltage level decision means when a driving pulse becomes inactive and an input voltage level is judged not exceeding the reference level. CONSTITUTION:In the case of the driving pulse of a pulse generation circuit 5 becomes inactive, a driving control circuit 6 stops the operation of the VBB level decision circuit 1 when a VBB level decision circuit 1 judges that a VBB level does not exceed the reference level. Even when the driving pulse becomes inactive, the operating of the VBB level decision circuit 1 is continued and a VBB power supply generation circuit 2 continues generation of the VBB power supply when the VBB level decision circuit 1 judges that the VBB level exceeds the reference level. Thus, the VBB level of a VBB power supply terminal 3 reduces, and the driving control circuit 6 stops the operation of the VBB level decision circuit 1 when the VBB level decision circuit 1 judges that the VBB level does not exceed the reference level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage level determination circuit such as a V _BB level determination circuit used in a V _BB power supply device for a semiconductor device.

[0002]

2. Description of the Related Art A conventional V _BB power supply device for a semiconductor device is composed of a V _BB level determination circuit 11 and a V _BB power supply generation circuit 12, as shown in FIG. V _BB level judgment circuit 1
1 is the input circuit 11a for the V _BB level of the V _BB power supply terminal 13.
Is used as one input of the differential amplifier 11b. The reference level determined by the reference level circuit 11c is input to the other input of the differential amplifier 11b. Therefore, V _BB level determining circuit 11, V when V _BB level _BB power source terminal 13 exceeds the reference level, V _BB level determining pin 14 connected to the output of the differential amplifier 11b
To L level.

The V _BB power supply generation circuit 12 comprises a ring oscillator 12a and a charge pump circuit 12b. The ring oscillator 12a operates when the V _BB level determination terminal 14 becomes L level, and the charge pump circuit 12b becomes H level.
It is a circuit that alternately supplies the / L level. Also, the charge pump circuit 12b, by being alternately supplied to the one end H / L level of the capacitor, lowering thrust potential of the other end of the capacitor, the circuit supplies V _BB power V _BB supply terminal 13 Is.

[0004] Therefore, the V _BB power supply, monitors the V _BB level of the semiconductor device by V _BB level determining circuit 11, operates the V _BB voltage generator 12 when the V _BB level exceeds the reference level, It can be ensured that the V _BB level is kept below the reference level at all times.

[0005]

However, in the V _BB power supply device, since the V _BB level determination circuit 11 constantly monitors the V _BB level, the differential amplifier 11b and the input circuit 11 are provided.
The drive current is constantly kept flowing in the a and the reference level circuit 11c. However, particularly in recent semiconductor devices, there are cases where it is required to reduce the power consumption during standby as much as possible because of battery driving and the like.

Therefore, the conventional V _BB power supply device is
There has been a problem that the drive current of the _BB level determination circuit 11 becomes an obstacle when trying to reduce the power consumption of the semiconductor device during standby.

In view of the above circumstances, it is an object of the present invention to provide a voltage level determination circuit for a semiconductor device which can reduce power consumption during standby.

[0008]

The voltage level determination circuit of the present invention comprises a voltage level determination means for inspecting whether an input voltage exceeds a predetermined reference level, and a pulse for generating a drive pulse which becomes intermittently active. The operation of the generating means and the voltage level determining means is started when the drive pulse becomes active, the drive pulse becomes inactive, and the input voltage level exceeds the reference level by the voltage level determining means. If it is determined that there is no
And a drive control means for stopping the operation of the voltage level determination means, whereby the above object is achieved.

The input voltage is V used in a semiconductor device.
Can be _BB level.

It is preferable that the pulse generating means generate a drive pulse having a constant length at constant time intervals.

[0011]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows a schematic configuration when the embodiment of the present invention is applied to a V _BB power supply device. This V _BB power supply is V
It is composed of a _BB level determination circuit 1, a V _BB power supply generation circuit 2, a pulse generation circuit 5 and a drive control circuit 6. When the drive pulse of the pulse generation circuit 5 becomes active, the drive control circuit 6 starts the operation of the V _BB level determination circuit 1. When the V _BB level determination circuit 1 starts operating, it is determined whether or not the V _BB level of the V _BB power supply terminal 3 exceeds the reference level, and when it is determined that the V _BB level exceeds the reference level. When V _BB level determination terminal 4 is activated and it is determined that the reference level is not exceeded, V
_{Set the BB} level judgment terminal 4 to inactive.

The drive control circuit 6 is a V _BB level judgment circuit 1
Is operating, the determination result output to the V _BB level determination terminal 4 is directly output to the V _BB power supply generation circuit 2. Therefore, if it is determined that V _BB level exceeds the reference level by V _BB level determining circuit 1, V
BB power generator 2 to generate the V _BB supply lower the V _BB level V _BB supply terminal 3. However, when it is determined that the V _BB level does not exceed the reference level, the V _BB power supply generation circuit 2 does not operate.

[0014] When the driving pulse of the pulse generating circuit 5 is no longer active, when the V _BB level has been determined not to exceed the reference level by V _BB level determining circuit 1 in this case, the drive control circuit 6 The operation of this V _BB level determination circuit 1 is stopped. However, even if the drive pulse is no longer active, if the V _BB level determination circuit 1 still determines that the V _BB level exceeds the reference level, the operation of the V _BB level determination circuit 1 is continued. , V _BB power supply generation circuit 2 also continues to generate V _BB power supply. And thereby reduces the V _BB level V _BB supply terminal 3, V _BB level determining when the circuit 1 is V _BB level will be determined not to exceed the reference level, the drive control circuit 6 is V _BB level The operation of the determination circuit 1 is stopped. Note that when the drive control circuit 6 stops the operation of the V _BB level determination circuit 1, the V _BB power supply generation circuit 2 also does not operate.

As a result, according to the present embodiment, the operation of the V _BB level determination circuit 1 is started only when the pulse generation circuit 5 intermittently activates the drive pulse, so that the V _BB level determination circuit is started. It is possible to reduce the power consumption of the semiconductor device in the standby state, since the drive current does not always flow in the semiconductor device 1. Further, when the driving pulse of the pulse generating circuit 5, such as than V _BB voltage generator 2 only while the active occurs the V _BB power becomes left V _BB level exceeds the reference level, this Since the V _BB level determination circuit 1 continues to operate and the V _BB power supply generation circuit 2 continues to generate the V _BB power supply even after the drive pulse is no longer active, the V _BB power supply terminal 3
The V _BB level of can be certainly lower than the reference level.

The configuration of the V _BB power supply device of FIG. 1 will be described in more detail with reference to FIG.

The pulse generator 5 is a ring oscillator 5
a and four toggle flip-flop circuits 5b to 5e
And a NAND circuit 5f. Ring oscillator 5
Reference numeral a denotes an oscillator in which a plurality of inverters are connected in a ring shape, and sequentially outputs pulses having the same duty ratio, as shown in FIG. Each toggle flip-flop circuit 5b
5e, as shown in FIG. 3, each time the input H / L level is switched, the output of one of the two inverter circuits is input to the other of the two inverter circuits, or the other of the two inverter circuits. Is a flip-flop circuit that repeats the operation of inverting the output of the above and inputting it to one of the two inverter circuits. Therefore, these toggle flip-flop circuits 5
For b to 5e, as shown in FIG. 4, the input is from L level to H level.
A toggle operation is performed in which the output H / L level is switched each time the level is switched to the input pulse, and the input pulse is sequentially divided by half. The NAND circuit 5f is configured to output the NAs of the toggle flip-flop circuits 5b to 5e.
As shown in FIG. 4, it is a circuit for performing ND calculation, and outputs a drive pulse that becomes active (L level) for one cycle of this pulse every 16 cycles of the pulse oscillated by the ring oscillator 5a.

The drive pulse output from the NAND circuit 5f of the pulse generation circuit 5 is input to the NAND circuit 6a of the drive control circuit 6. A forced operation signal (L active) is input to the other input of the NAND circuit 6a, which allows the V _BB level determination circuit 1 to operate regardless of the output of the pulse generation circuit 5. Is possible. The output of the NAND circuit 6a is input to the dual inverter circuit 6c via the switch circuit 6b.
The switch circuit 6b includes the NAND circuit 6a and the dual inverter circuit 6 only when the V _BB level determination terminal 4 is at the H level.
It is a circuit that connects to c. Double inverter circuit 6
Reference numeral c is a flip-flop circuit that stores the input level. The FETs 6d and 6e are turned on and power is supplied to the V _BB level determination circuit 1 only when the output of the double inverter circuit 6c is at the L level. Further, when the output of the dual inverter circuit 6c becomes H level and the supply of power to the V _BB level judgment circuit 1 is stopped, the FET 6f is turned ON and the V _BB level judgment terminal 4 is fixed at H level. To do.

The operation of the V _BB power supply device having the above configuration will be described.

When an L-active drive pulse is input from the pulse generation circuit 5 to the drive control circuit 6, the output of the NAND circuit 6a is, as shown in FIGS. 5 and 6, a short period during which the drive pulse is active. Only goes to H level. Further, at this time, as will be described later, since the FET 6f is turned on and the V _BB level determination terminal 4 is at the H level, the switch circuit 6b is opened and the H level of the output of the NAND circuit 6a is double inverter circuit. 6c is input. Two
When the H level is input, the serial inverter circuit 6c holds the H level and maintains the L level output. When the output of the dual inverter circuit 6c becomes L level, the FETs 6d and 6e are turned ON and the V _BB level determination circuit 1 starts operating. At this time, the FET 6f is OF
Since it becomes F, the V _BB level determination terminal 4 depends only on the output of the V _BB level determination circuit 1.

Here, as shown in FIG. 5, if the V _BB level of the V _BB power supply terminal 3 exceeds the reference level of the V _BB level determination circuit 1, the V _BB level determination terminal 4 switches to the L level. .. Then, since the V _BB supply generating circuit 2 supplies the V _BB supply to V _BB power supply terminal 3 to start the operation, the V _BB level gradually decreases. However, when this V _BB level immediately becomes lower than the reference level, the V _BB level determination terminal 4 returns to the H level, and the V _BB power supply generation circuit 2 also stops operating. After that, when the drive pulse from the pulse generation circuit 5 becomes inactive, the NAND circuit 6a outputs L
The level output is sent to the double inverter circuit 6c via the switch circuit 6b, the V _BB level determination circuit 1 also stops operating, and the FET 6f is turned on to fix the H level of the V _BB level determination terminal 4. Return to the initial state.

However, in FIG. 5, even if the drive pulse from the pulse generating circuit 5 becomes inactive, the V _BB level still exceeds the reference level. Therefore, since the V _BB level determination terminal 4 also remains at the L level and the switch circuit 6b is closed, the drive pulse becomes inactive and the output of the NAND circuit 6a becomes the L level, but the dual inverter circuit The L level output of 6c is maintained and the V _BB level determination circuit 1 continues to operate. Moreover, to continue this by V _BB voltage generating circuit 2 also operates, V _BB
Levels continue to decline. Then, when this V _BB level becomes lower than the reference level of the V _BB level determination circuit 1,
The V _BB level determination terminal 4 returns to the H level, and the V _BB power supply generation circuit 2 stops operating. Further, as a result, the L level output from the NAND circuit 6a before the switch circuit 6b is opened is input to the dual inverter circuit 6c.
Therefore, the V _BB level determination circuit 1 also stops its operation, the FET 6f is turned on, the H level of the V _BB level determination terminal 4 is fixed, and the initial state is restored.

When the drive pulse is input from the pulse generation circuit 5, the V _BB power supply terminal 3 is connected as shown in FIG.
If the V _BB level of V _BB does not exceed the reference level of the V _BB level determination circuit 1, the V _BB level determination terminal 4 remains at the H level and the V _BB power supply generation circuit 2 does not operate.
Then, since the switch circuit 6b is also kept open, when the drive pulse becomes inactive, the NAND circuit 6a becomes L level.
The output of the level is input to the double inverter circuit 6c,
The V _BB level determination circuit 1 also stops operating and the FET
6f is turned on, the H level of the V _BB level determination terminal 4 is fixed, and the state returns to the initial state.

As a result, the V _BB level determination circuit 1 starts its operation intermittently only when the drive pulse from the pulse generation circuit 5 becomes active, so that the current always flows even when the semiconductor device is on standby. It is possible to reduce power consumption. Further, when the V _BB voltage generator 2 is V _BB level V _BB supply terminal 3 be operated does not become immediately lower than the reference level, even after the drive pulse is no longer active, followed by the V _BB Since the power supply generation circuit 2 can be operated, the V _BB level can be reliably made lower than the reference level.

[0025]

As is apparent from the above description, according to the present invention, it is possible to reduce the power consumption of the semiconductor device during standby by operating the voltage level determination means intermittently. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration when an embodiment of the present invention is applied to a V _BB power supply device.

FIG. 2 is a circuit diagram showing the configuration of the V _BB power supply device of FIG. 1 in more detail.

3 is a circuit diagram showing a configuration of a toggle flip-flop circuit in the pulse generation circuit of FIG.

FIG. 4 is a time chart showing waveforms of various parts in the pulse generation circuit of FIG.

FIG. 5 is a time chart showing waveforms of respective parts when the V _BB level exceeds the reference level in the V _BB power supply device of FIG.

6 is a time chart showing waveforms of various portions when the V _BB level does not exceed the reference level in V _BB supply device of FIG.

FIG. 7 is a circuit diagram showing a configuration of a conventional V _BB power supply device.

[Explanation of symbols]

1 V _BB level determination circuit 2 V _BB power supply generation circuit 5 pulse generation circuit 6 drive control circuit

Claims (1)

[Claims] 1. A voltage level determination means for inspecting whether or not an input voltage exceeds a predetermined reference level, a pulse generation means for generating a drive pulse which becomes intermittently active, and a pulse generation means when the drive pulse becomes active. When the operation of the voltage level determination means is started, the drive pulse becomes inactive, and the voltage level determination means determines that the input voltage level does not exceed the reference level, the voltage level determination means A voltage level determination circuit for a semiconductor device, comprising: