JPH05205468A - Substrate voltage generation circuit for dynamic ram - Google Patents

Abstract

PURPOSE:To reduce the current consumption in a stand-by time by operating it intermittently even when source voltage is lowered. CONSTITUTION:This circuit is provided with two sets (1A, 1B) of substrate voltage level decision circuits of which setting of the decision level of substrate voltage operating intermittently has been previously changed. Source voltage is detected by a source voltage level detection circuit and the substrate voltage level decision circuit 1A whose decision level is set deeply is operated when source voltage is high and the substrate voltage level decision circuit 1B whose decision level is set in shallow when source voltage is low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate voltage generating circuit for a low voltage dynamic RAM having a small standby current.

[0002]

2. Description of the Related Art The structure of a conventional dynamic RAM substrate voltage generating circuit will be described with reference to FIG. Figure 6
It is a circuit diagram which shows the substrate voltage generation circuit of the conventional dynamic RAM.

In FIG. 6, reference numeral 1 is a substrate voltage level determination circuit, and 2 is a NAN connected to the substrate voltage level determination circuit 1.
D gate, 3 is a timer circuit connected to the NAND gate 2, 4 is a NAND gate connected to the substrate voltage level determination circuit 1 and the timer circuit 3, and 5 is a NAND gate 4
The oscillator circuit connected to the oscillator circuit 6 is a pump circuit connected to the oscillator circuit 5. In addition, V1 is a substrate voltage, V2 is a power supply voltage, and V3 is GND. Further, the NAND gate 2 controls the operation of the timer circuit 3, and the timer circuit 3 operates the oscillation circuit 5 for a certain period of time.

In the substrate voltage level determination circuit 1, 7 is a clamp circuit composed of three stages of N-type MOS transistors, 8 is a precharge circuit, 9 is a node, and 10 is for driving the circuit of the next stage. Is an inverter.

The oscillation circuit 5 includes inverters 11, 12, 1
NAND gate 3 and 14 and a NAND gate 15
The operation is controlled by the gate 15.

The pump circuit 6 includes a capacitor 17 and an N-type M
It is composed of OS transistors 19 and 20, and supplies electrons to the substrate to generate a substrate voltage. In addition, 16 is an inverter which drives the capacitor 17, and 18 is a node.

Next, the above-mentioned conventional dynamic RA
The operation of the M substrate voltage generating circuit will be described with reference to FIG. FIG. 7 is a timing chart showing the operation of the substrate voltage generation circuit of the conventional dynamic RAM. In FIG. 7, (a) is the output signal S3 of the NAND gate 4,
(B) is the oscillation signal S4 of the oscillation circuit 5, VL of (c) is the determination level for stopping the substrate voltage generation circuit, V1 is the substrate voltage, and the determination level VL is the N-type MO of the clamp circuit 7.
The threshold value Vth of the clamp circuit 7 is set by the S transistor.
Is set to four times the value of. The substrate voltage V1 and the determination level VL are negative values.

As shown in FIG. 7C, if the substrate voltage V1 is deeper than the judgment level VL, the clamp circuit 7 lowers the substrate voltage V1 and the node 9 becomes a level slightly deeper than the threshold Vth. And precharge circuit 8
N-type MOS transistor has a source-gate voltage V
Since SG becomes equal to or higher than the threshold value Vth, it is turned on and the output of the precharge circuit 8 becomes low level, and the output signal S1 of the substrate voltage level determination circuit 1 becomes high level. Further, since the output signal S2 of the timer circuit 3 is set to the high level at this time, the output signal S3 of the NAND gate 4 becomes the low level. As a result, the oscillation circuit 5
It is fixed at a low level by the AND gate 15. Since the oscillation circuit 5 is not operating, the pump circuit 6 does not supply the substrate voltage V1.

Since the substrate voltage generating circuit is stopped, the substrate voltage V1 gradually becomes shallow due to leakage from the circuit on the substrate to the substrate. When the substrate voltage V1 becomes shallower than the judgment level VL, the clamp circuit 7 causes the node 9 to have a threshold value Vth.
Since it becomes shallower, the N-type MOS transistor of the precharge circuit 8 is turned off, the output of the precharge circuit 8 becomes high level by the P-type MOS transistor, and the output signal S1 of the substrate voltage level determination circuit 1 becomes low level. N
The output signal S3 of the AND gate 4 becomes high level.

The NAND gate 15 of the oscillating circuit 5 waits for the inputs of the inverters 11 to 14 and generates the oscillating signal S4 as the oscillating circuit 5 composed of odd-numbered inverters. The oscillation signal S4 of the oscillation circuit 5 is input to the pump circuit 6, and when the oscillation signal S4 is at a high level, the coupling of the capacitor 17 raises the node 18 to VCC, but the N-type transistor 19 raises it to the threshold value Vth. Go down. When the oscillation signal S4 goes low in this state, the node 18 becomes a negative voltage of (Vth-power supply voltage) due to the coupling of the capacitor 17, and the substrate voltage V1 is supplied by the N-type transistor 20.

At this time, since the low level of the output signal S1 of the substrate voltage level determination circuit 1 is input to the NAND gate 2, the timer circuit 3 does not receive the oscillation signal S4 and remains stopped. The output signal S2 of the timer circuit 3 at this time is set to a low level by the output of the NAND gate 2.

When the substrate voltage V1 is supplied by the pump circuit 6, the substrate voltage V1 also becomes deeper and becomes deeper than the determination level VL, the output of the substrate voltage level determination circuit 1 becomes high level, and the timer circuit 3 outputs the oscillation signal S4. It works because it is input. Since the substrate voltage V1 becomes shallower immediately when it becomes deeper than the determination level VL, the period during which the substrate voltage generation circuit stops is shortened.
Even if it becomes deeper than L, the timer circuit 3 operates for a certain period to make it deeper.

When the timer circuit 3 operates for a certain period of time, its output signal S2 also goes high. Therefore, N
Since a high level is input to the two input terminals of the AND gate 4, its output signal S3 becomes low level, the oscillation signal S4 of the oscillation circuit 5 becomes low level, and the substrate voltage generating circuit is stopped.

[0014]

In the conventional dynamic RAM substrate voltage generating circuit as described above, an intermittent operation is performed in which the substrate voltage generating circuit is operated for a certain period of time. Since the capacity of the pump circuit 6 decreases as the power supply voltage decreases, as shown in FIG. 8, the substrate voltage V1 becomes shallower than the determination level VL, the substrate voltage level determination circuit 1 stops operating, and the substrate voltage generation circuit continues to operate. To work. Therefore, the substrate voltage generating circuit has a problem in that it operates continuously with a low power supply voltage and consumes a large amount of power.

The present invention has been made in order to solve the above-mentioned problems, and a dynamic RAM capable of reducing power consumption during standby by enabling intermittent operation even when the power supply voltage is low. The purpose is to obtain a substrate voltage generation circuit.

[0016]

A dynamic RAM substrate voltage generating circuit according to a first aspect of the present invention includes the following means. [1] A first substrate voltage level determination circuit in which the determination level of the substrate voltage for intermittent operation is set deep. [2] A second substrate voltage level determination circuit in which the determination level is set shallow. [3] A power supply voltage level detection circuit that operates the first substrate voltage level determination circuit when the power supply voltage is high, and operates the second substrate voltage level determination circuit when the power supply voltage is low.

Dynamic R according to claim 2 of the present invention
The substrate voltage generation circuit of AM is equipped with the following means. [1] A substrate voltage level determination circuit capable of varying the determination level of the substrate voltage for intermittent operation. [2] When the power supply voltage is high, the judgment level is set deep to operate the substrate voltage level judgment circuit, and when the power supply voltage is low, the judgment level is set shallow to operate the substrate voltage level judgment circuit. Judgment level setting means.

Dynamic R according to claim 3 of the present invention
The AM substrate voltage generating circuit includes the following means, and the first pump circuit operates when the power supply voltage is high, and the first and second pump circuits operate when the power supply voltage is low. .. [1] First and second pump circuits for supplying a substrate voltage. [2] A power supply voltage level detection circuit that operates the second pump circuit when the power supply voltage is low.

[0019]

A dynamic RAM according to claim 1 of the present invention.
In the substrate voltage generation circuit of No. 1, when the power supply voltage is high, the first substrate voltage level determination circuit in which the determination level of the substrate voltage for intermittent operation is set deep is operated by the power supply voltage level detection circuit, When the power supply voltage is low, the determination level is set to be shallow.
The substrate voltage level determination circuit is operated.

Dynamic R according to claim 2 of the present invention
The AM substrate voltage generation circuit is provided with a substrate voltage level determination circuit that can vary the determination level of the substrate voltage for intermittent operation, and the determination level setting means deeply sets the determination level when the power supply voltage is high. The substrate voltage level determination circuit is operated, and when the power supply voltage is low, the determination level is set shallow and the substrate voltage level determination circuit is operated.

Dynamic R according to claim 3 of the present invention
In the AM substrate voltage generation circuit, the substrate voltage is supplied by the first and second pump circuits. Further, the power supply voltage level detection circuit operates the second pump circuit when the power supply voltage is low. Then, when the power supply voltage is high, the first pump circuit is operated, and when the power supply voltage is low, the first and second pump circuits are operated.

[0022]

【Example】

Example 1. The configuration of the first embodiment of the present invention will be described with reference to FIGS. First Embodiment FIG. 1 is a circuit diagram showing a part of a first embodiment of the present invention. NAND gates 2 and 4, a timer circuit 3, a clamp circuit 7, a precharge circuit 8, a node 9 and an inverter 10, and not shown. The oscillator circuit 5 and the pump circuit 6 are the conventional dynamic R described above.
It is the same as that of the AM substrate voltage generation circuit. Figure 2
It is a circuit diagram which shows the power supply voltage level detection circuit 24 of Example 1 of this invention. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, 1A is a substrate voltage level determination circuit when the power supply voltage is high, that is, the determination level is set deep, and 1B is a substrate when the power supply voltage is low, that is, the determination level is set shallow. It is a voltage level determination circuit. It should be noted that 7A in the substrate voltage level determination circuit 1B is a clamp circuit composed of two stages of N-type MOS transistors, and 21, 22, and 23 are NAND gates.

In FIG. 2, 25 is a level-down circuit composed of two-stage N-type MOS transistors, 26 is a resistor, 27 is a node, and 28 and 29 are inverters.

Next, the operation of the above-described first embodiment will be described with reference to FIG. FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention. In FIG.
The output signal S3 of the NAND gate 4 is shown in (a), the oscillation signal S4 of the oscillation circuit 5 is shown in (b), and VL1 in FIG. 8 (c) is a deeply set determination level, and VL2 is a shallowly set determination level.

The node 27 of the power supply voltage level detection circuit 24 shown in FIG.
The level of the power supply voltage -2Vth of the N-type MOS transistor of the stage appears, but if the power supply voltage is higher than twice the threshold value Vth, the node 27 becomes high level even if the level is lowered, and the output signal S5 of the inverter 28 becomes low. Become a level. Further, the output signal S6 of the inverter 29 becomes high level.

The low-level output signal S5 is input to the NAND gate 22 of the substrate voltage level determination circuit 1B, and N is output regardless of the output of the substrate voltage level determination circuit 1B.
The output of the AND gate 22 remains high level. The high-level output signal S6 is output to the substrate voltage level determination circuit 1
This is input to the NAND gate 21 of A, and this NAN
The output of the D gate 21 conveys the output of the substrate voltage level determination circuit 1A. Therefore, the power supply voltage is equal to the threshold value Vth of 2
If it is more than twice, the substrate voltage level determination circuit 1A which makes the set value of the substrate voltage determination level deep is operated, and the substrate voltage determination level is the level VL1 shown in FIG. Type threshold voltage Vth of the MOS transistor becomes four times.

If the power supply voltage is less than twice the threshold value Vth, the node 27 becomes low level by the level down circuit 25, the output signal S5 of the inverter 28 becomes high level, and the output signal S6 of the inverter 29 becomes. Become low level. The NAND gate 22 of the substrate voltage level determination circuit 1B transmits the output of the substrate voltage level determination circuit 1B by the high level output signal S5, and the NAND gate 21
Is fixed to a high level by the low level output signal S6. Therefore, if the power supply voltage is less than twice the threshold value Vth, the substrate voltage level determination circuit 1B having a shallow determination level is operated to determine the substrate voltage determination level as shown in FIG. VL2, which is set to three times the threshold value Vth of the N-type MOS transistor. The following operation is the same as the conventional example.

The first embodiment of the present invention, as described above,
When two sets (1A, 1B) of substrate voltage level determination circuits in which the set value of the determination level of the substrate voltage for the intermittent operation is changed are provided and the power supply voltage is detected by the power supply voltage level detection circuit 24, and the power supply voltage is high Operates the substrate voltage level determination circuit 1A whose determination level is deeply set and operates the substrate voltage level determination circuit 1B whose determination level is set shallow when the power supply voltage is low. Since the intermittent operation is performed, the current consumption during standby can be reduced.

Example 2. Although the two substrate voltage level determination circuits are provided in the first embodiment described above, the same effect can be obtained by providing the substrate voltage level determination circuit 1C and the latch circuit 30 as shown in FIG.

The configuration of the second embodiment of the present invention will be described with reference to FIG. Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment of the present invention, which has NAND gates 2 and 4, a timer circuit 3, an oscillation circuit 5, and a pump circuit 6 which are the same as those of the conventional circuit described above, though not shown. The same power supply voltage level detection circuit 24 as that of the first embodiment is also provided. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 4, 31 is an N-type MOS transistor, 32 and 33 are P-type MOS transistors, 34 and 3
Reference numeral 5 is an N-type MOS transistor, and 36 and 37 are nodes.

By the way, the judgment level setting means according to claim 2 of the present invention comprises the power supply voltage level detection circuit 24 and the latch circuit 30 in the second embodiment of the present invention.

Next, the operation of the above-described second embodiment will be described. If the power supply voltage is more than twice the threshold value Vth, the P-type MOS transistor 33 is turned on by the high-level signal S6 to bring the node 37 to the high level, the N-type MOS transistor 34 is turned on, and the node 36 is the substrate. Become a voltage. The N-type MOS transistor 31 is turned off because the gate and source voltages become the substrate voltage and the voltage VSG is 0V. Therefore, the clamp circuit 7 has three stages of N-type MO.
It will be composed of S transistors.

If the power supply voltage is less than twice the threshold value Vth, the P-type MOS transistor 32 is turned on by the high-level signal S5, the node 36 is set to the high level, and the N-type MOS transistor 31 is turned on. Since the substrate voltage is input to the second-stage N-type MOS transistor of the clamp circuit 7, the clamp circuit 7 is composed of two-stage N-type MOS transistors and changes the determination level of the substrate voltage.

The second embodiment of the present invention, as described above,
A substrate voltage level determination circuit 1C and a latch circuit 30 capable of changing the set value of the determination level of the substrate voltage for performing the intermittent operation are provided, the power source voltage is detected by the power source voltage level detection circuit 24, and when the power source voltage is high, Since the determination level is set deep and the determination level is set shallow when the power supply voltage is low, even if the power supply voltage becomes low, the intermittent operation is performed, so that the current consumption during standby can be reduced.

Example 3. Further, in the above-described first embodiment, two sets of substrate voltage level determination circuits are provided, but even if two sets (6, 6A) of pump circuits having the same configuration are provided as shown in FIG. 5, the intended purpose is achieved. obtain.

The configuration of the third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a circuit diagram showing a third embodiment of the present invention. Although not shown, the same substrate voltage level determination circuit 1, NAND gate 2, and the same as those of the conventional circuit described above are provided.
4. The timer circuit 3 is provided, and the same power supply voltage level detection circuit 24 as that of the first embodiment is also provided.

In FIG. 5, reference numeral 38 denotes a NAND gate having one input terminal connected to the oscillation circuit 5 and the other input terminal connected to the power supply voltage level detection circuit 24, and 6A connected to the NAND gate 38 for pumping. This is a pump circuit having the same configuration as the circuit 6.

A NAND gate 38 is provided on the input side of the newly added pump circuit 6A, and the oscillation signal S4 of the oscillation circuit 5 and the output signal S5 of the power supply voltage level detection circuit 24 are provided at one input terminal of the NAND gate 38. It has been entered.
If the power supply voltage is at least twice the threshold value Vth, the output signal S5 is at the low level, and the output of the NAND gate 38 remains at the high level, so that the pump circuit 6A stops operating and only the pump circuit 6 operates. is doing. If the power supply voltage is less than twice the threshold value Vth, the output signal S5 becomes high level, and the output of the NAND gate 38 becomes low level when the oscillation signal S4 of the oscillation circuit 5 is input, and the two sets of pump circuits 6 are provided. , 6A operates to deepen the substrate voltage to the determination level.

The third embodiment of the present invention, as described above,
Two sets of pump circuits for supplying the substrate voltage V1 (6, 6A)
Since the power supply voltage is detected by the power supply voltage level detection circuit 24 and the pump circuit 6A is also operated when the power supply voltage is low, even if the power supply voltage becomes low, the intermittent operation is performed, so that the current consumption during standby is reduced. The effect that it can be made small is exhibited.

[0042]

As described above, the substrate voltage generation circuit for the dynamic RAM according to the first aspect of the present invention is the first substrate voltage level determination circuit in which the determination level of the substrate voltage for the intermittent operation is set deep. And a second substrate voltage level determination circuit in which the determination level is set shallow, and the first substrate voltage level determination circuit when the power supply voltage is high, and the second substrate voltage level determination circuit in which the power supply voltage is low. Since the power supply voltage level detection circuit for operating the substrate voltage level determination circuit is provided, it is possible to reduce power consumption during standby by enabling intermittent operation even when the power supply voltage is low.

Dynamic R according to claim 2 of the present invention
As described above, the AM substrate voltage generation circuit includes a substrate voltage level determination circuit that can vary the determination level of the substrate voltage that causes the intermittent operation, and a deeper determination level when the power supply voltage is high, and the substrate voltage level is set. Since the determination circuit is provided and the determination level setting means for operating the substrate voltage level determination circuit by setting the determination level shallow when the power supply voltage is low, intermittent operation is possible even when the power supply voltage is low. With this, it is possible to reduce the power consumption during standby.

Dynamic R according to claim 3 of the present invention
As described above, the AM substrate voltage generation circuit includes the first and second pump circuits that supply the substrate voltage and the power supply voltage level detection circuit that operates the second pump circuit when the power supply voltage is low. When the power supply voltage is high, the first pump circuit operates, and when the power supply voltage is low, the first and second pump circuits operate, so that intermittent operation is possible even when the power supply voltage is low. By doing so, it is possible to reduce the power consumption during standby.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a power supply voltage level detection circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a substrate voltage generation circuit of a conventional dynamic RAM.

FIG. 7 is a timing chart showing an operation of a substrate voltage generating circuit of a conventional dynamic RAM.

FIG. 8 is a timing chart showing an operation of a substrate voltage generating circuit of a conventional dynamic RAM.

[Explanation of symbols]

 1, 1A, 1B, 1C Substrate voltage level determination circuit 2, 4, 38 NAND gate 3 Timer circuit 5 Oscillation circuit 6, 6A Pump circuit 24 Power supply voltage level detection circuit 30 Latch circuit

Claims (3)

[Claims] 1. A first substrate voltage level determination circuit in which a determination level of a substrate voltage for intermittent operation is set deeply,
A second substrate voltage level determination circuit in which the determination level is set shallow, and the first substrate voltage level determination circuit is operated when the power supply voltage is high, and the second substrate voltage level determination circuit is operated when the power supply voltage is low. A substrate voltage generation circuit for a dynamic RAM, comprising a power supply voltage level detection circuit for operating a level determination circuit. 2. A substrate voltage level judgment circuit capable of varying a judgment level of a substrate voltage for intermittent operation, and when the power supply voltage is high, the judgment level is deeply set to operate the substrate voltage level judgment circuit to operate the power supply. A substrate voltage generation circuit for a dynamic RAM, comprising: determination level setting means for operating the substrate voltage level determination circuit by setting the determination level shallow when the voltage is low. 3. A first and second pump circuit for supplying a substrate voltage, and a power supply voltage level detection circuit for operating the second pump circuit when the power supply voltage is low, and when the power supply voltage is high, the power supply voltage level detection circuit is provided. A dynamic RA characterized in that the first pump circuit operates and the first and second pump circuits operate when the power supply voltage is low.
Substrate voltage generation circuit of M.