JPH0553332B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wireless communication system, and more particularly to an orthogonal polarization digital wireless communication system equipped with a cross-polarization interference removal circuit.

[Conventional technology]

In microwave and sub-millimeter wave band digital wireless communication lines, bipolar digital multiplexed signals sent from multiplexing terminal equipment are processed as follows. That is, the signal is first converted into a unipolar signal in a transmission signal processing device provided at the transmitting end station, speed-converted, and additional bits such as a parity check bit for wireless section monitoring and a frame synchronization signal are inserted. Furthermore, it undergoes scrambling processing to flatten the transmission spectrum and facilitate bit synchronization recovery on the receiving side.
It is sent out to the modulator of the transmitting device. This scrambling process is generally performed by calculating the modulo-2 sum of an input signal and a pseudorandom code obtained from an m-sequence (longest linear code sequence) code sequence generator using a shift register. On the other hand, on the receiving end station side, descrambling processing is performed using the same pseudorandom code as on the transmitting end station side to restore the original signal.

In conventional digital wireless communication systems, an interleaved frequency arrangement is used in which the carrier frequencies of two orthogonal polarized waves are arranged so that the carrier frequency of each polarized wave is midway between the carrier frequencies of mutually opposite polarized waves. There is. In order to simplify the device configuration and improve mass productivity, the same transmission signal processing device is used for each digital multiplexed signal, and therefore the same pseudo-random code is used for scrambling.

In recent years, in order to make the use of frequency bands even more effective, cochannel frequency allocation using orthogonal polarization has attracted attention, and research and development for its practical use has been actively conducted. One such problem is the problem of eliminating cross-polarization interference that occurs between orthogonal polarizations due to rainfall, etc., and various methods have been proposed. Among them, the method proposed in Japanese Unexamined Patent Publication No. 133156/1983 is attracting attention as a method suitable for digital wireless communication systems. This method does not use a pilot signal, but instead detects cross-polarization interference by determining the correlation between demodulated baseband signals of two polarizations. It is based on the assumption that the signals are mutually independent and uncorrelated. This precondition is satisfied when data signals are normally input to the two polarized waves, and therefore the interference cancellation circuit operates normally.

[Problem that the invention seeks to solve]

However, if the same scrambling process as in the conventional method is performed, there may be cases where the digital multiplexed signals from the multiplexing terminal equipment for both V (vertical) and H (horizontal) polarizations are disconnected, A problem occurs when all inputs to the network terminal equipment become "0" (this condition occurs even during line operation, but it becomes a particular problem during line tests during construction). That is, as will be described in detail later, in the above case, the same code sequence is sent to both V and H polarizations from the transmission signal processing device that performs scrambling processing, causing the receiving system including the interference cancellation circuit to malfunction. There is a point.

An object of the present invention is to eliminate the above-mentioned problems, and to prevent the same code sequence from being outputted in the same phase from the transmission signal processing device for both V and H polarization under any circumstances.
It is an object of the present invention to provide a digital wireless communication system in which malfunction does not occur in a receiving system including an interference cancellation circuit.

[Means for solving problems]

The present invention provides a multi-phase multi-level digital wireless communication system using two mutually orthogonal polarized waves, in which at least one series of baseband signals of at least one set of n series of baseband signals is transmitted to a transmitting side. Then, by arbitrarily delaying the mutually orthogonal multiphase multilevel digital modulation signals, the relationship between the mutually orthogonal multiphase multilevel digital modulation signals is made uncorrelated, and on the receiving side, the demodulated baseband signal is sent to the delay circuit as a set of n sequences complementary to the delay applied on the transmitting side. are provided and configured to correct the phase relationship of each of the n series of baseband signals that are orthogonal to each other.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

First, the configuration and operation of the transmitter and receiver devices to which the present invention is applied will be explained. FIG. 1 is a block diagram showing an example of the configuration of a transmitting signal processing device on the transmitting end station side in an orthogonally polarized digital wireless communication line.
FIG. 2 is a block diagram showing an example of the configuration of an interference cancellation and waveform equalization circuit on the receiving end station side. In the following description, the vertical system will be denoted by v, and the horizontal system will be denoted by h.

In FIG. 1, 1v and 1h are bipolar signals 10 input from a multiplex terminal equipment (not shown).
0v, 100h as unipolar signal 101v, 10
1h, and 2v and 2h are parity counting circuits that count the number of "1" or "0" in the unipolar signal and determine whether an odd number is an even number.
3v, 3h are speed conversion circuits that insert frame synchronization signals, parity check bits, etc. by staff operations, 4v, 4h are speed converted signals 1
This is a scrambling circuit that performs scrambling processing on 02v and 102h, respectively. Furthermore, 5v, 5h
is a code sequence generator that generates pseudo-random codes (m-sequence linear codes) for scrambling processing. Scrambled modulated input signal 103
v, 103h is sent to a modulator of a transmitting device (not shown) for each polarized wave. The transmission signal processing devices 6v, 6h for the V and H polarizations and the transmission signal processing devices (not shown) for other carrier frequencies are controlled by a common bit clock generator 7 and frame clock generator 8. . In the conventional method, each code sequence generator 5
v and 5h are all the same, and the same pseudo-random code is used for scrambling processing of each polarization of V and H.

Figure 2 shows Japanese Patent Application Laid-Open No. 55-1981, which removes cross-polarization interference using the correlation of demodulated baseband signals.
133156 is a block diagram of a configuration example of a receiving circuit equipped with an interference cancellation circuit using the correlation method proposed in Publication No. 133156. FIG.
In FIG. 2, the detection outputs 104v and 104h of the V and H polarizations detected by the detectors 9v and 9h are as follows:
Identification judgment circuit 1 passes through waveform equalizers 10v and 10h each consisting of a transversal filter.
1v and 11h, and is decoded here to become baseband signals 105v and 105h and sent to a received signal processing device (not shown). On the other hand, the detected outputs 104v and 104h of each polarized wave are branched and coupled to the oppositely polarized signal through interference removal circuits (comprised of transversal filters) 12h and 12v, respectively. Waveform equalization correlator 13
The inputs of the interference control correlators 14v and 14h are the baseband signals 105 of each polarization.
v, 105h and its ±k bits (k is an integer 1,
2,..., and the upper limit is determined by the number of stages of the transversal filter), and the error signal 106 from the identification judgment circuits 11v and 11h.
By determining the correlation with v and 106h, waveform distortion and cross-polarization interference components are detected, respectively.
The waveform equalizer and interference removal circuit are configured to be controlled so that each error component is minimized.
That is, the waveform distortion component included in the error signal 106v of the V-polarized wave identification/judgment circuit 11v is detected by the waveform equalization correlator 13v using the V-polarized baseband signal 105v and its reference signal shifted by ±k bits. The waveform equalizer 10v is controlled and equalized using the detection signal. On the other hand, the interference component from the H-polarized wave is detected by the interference control correlator 14v using the H-polarized baseband signal 105h and the reference signal shifted by ±k bits, and is removed by controlling the interference cancellation circuit 12v. Ru.

Here, if the baseband signals 105v and 105h of both polarizations are uncorrelated, the error signal 1
It is possible to separate and detect waveform distortion components and cross-polarization interference components from 0.06v. However, as mentioned above, signals 105v and 105h have the same code series and have almost the same phase (within 2k bit shift).
In this case, since the waveform equalization correlator 13v and the interference control correlator 14v use the same reference signal, it becomes impossible to separate and detect the waveform distortion component and the cross-polarization component, and normal operation will not be performed. . Such a state is represented by the bipolar signal 10 in FIG.
This occurs when both 0v and 100h are disconnected. At this time, the inputs 102v and 102h of the scramble circuits 4v and 4h both become "0" or "1" continuously. Therefore, the scramble circuit 4v, 4
The pseudorandom code is output as is from h,
If the pseudorandom codes generated by the code sequence generators 5v and 5h are the same, the modulated input signals 103v,
103h are the same.

In order to prevent such a situation from occurring, in FIG. 1, at least one sequence (out of n sequences) of the scrambled modulated input signals 103v and 103h is arbitrarily delayed so that they are orthogonal to each other. The relationship between the modulated signals may be uncorrelated. In addition, bipolar signal 100
Even if both v and 100h are not disconnected, a similar situation will occur if the same code sequence is input. Even in multiplex terminal equipment that sends out bipolar formation 100V and 100h, scrambling processing is normally performed to facilitate the reproduction of bit synchronization signals when there is no input signal. When the line is not in use, the same code sequence for scrambling processing may be sent.

Figures 3 and 4 show four sequences scrambled using the same pseudorandom code (n=
This is an embodiment in which the signals of 4) are set to be uncorrelated with respect to two orthogonal polarized waves.

In Figure 3a, 103v and 103h are the first numbers scrambled with the same pseudo-random code.
~4 series of modulation input signals, and in Fig. 3b, 103'h indicates one flip-flop F as a delay circuit for the second series of each signal line of the four series. , by connecting two flip-flops F in series to the third series and three flip-flops F in series to the fourth series, the input signal 103v
is a modulated input signal processed to be uncorrelated with . These flip-flops F are provided in the scramble circuit shown in FIG. 1 or on the output side. The signals 103v, 103'h are sent to a modulator (not shown) of the transmitting device.

In FIGS. 4a and 4b, 105v and 105h are demodulated baseband signals of 4 series decoded by the identification judgment circuit of FIG.
For 5v, 3 for each of the 1st to 4th series.
On the other hand, in order to compensate for the delay given by the delay circuit of FIG. 3b on the transmitting side, for the demodulated baseband signal 105h, a
flip-flops F connected in series are inserted, and two flip-flops F are inserted in the second series.
are connected in series, and 1 is inserted in the third series.
By inserting flip-flops F,
Signals processed so as to be in the same sequence as the signals of 103v and 104h are obtained, and each signal is sent to a reception code processing device (not shown). Also, 10
7, 108, and 109 are bit clock signals for the respective signals.

Now, modulated input signals 103v, 103 scrambled with the same random code on the transmitting side
Before h is sent out to the modulator of the transmitter of the respective polarization, the signal 103h is transmitted as shown in FIG. 3b.
By delaying each signal sequence by 0 bits, 1 bit, 2 bits, and 3 bits, the signal 103
The code sequences of v and 103'h are assumed to be uncorrelated. After this, the signals 103v and 103'h are sent to the modulator of the transmitter of each polarization.

Next, before the baseband signals 105v and 105h decoded by the identification determination circuit on the receiving side are sent to the received signal processing device, each signal sequence is converted into 3 bits for 105h, as shown in FIGS. 4a and 4b. , 2 bits, 1 bit, 0 bits delayed, 1
By delaying each signal sequence by 3 bits with respect to 05v, 105'v and 105'h become 103
It is possible to correct the phase relationship between v and 103h. Thereafter, signals 105'v and 105'h are sent to the received signal processing device.

It goes without saying that the number of stages and connections of flip-flops are set depending on the modulation method, the number of multi-values, and the like.

In addition, in the above explanation, on the receiving side, the signal 10
All signal sequences are delayed by 3 bits with respect to 5V, but this is necessary for synchronous switching.
It is not necessary if synchronous switching is not performed.

〔Effect of the invention〕

As explained above, according to the present invention, in an orthogonally polarized digital wireless communication line equipped with a cross-polarized interference cancellation circuit using a correlation method, when input signals of both V and H polarizations are disconnected at the same time, Even if signals of the same code sequence are input, there is no risk of malfunction on the receiving end station side, and normal operation is guaranteed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the configuration of a transmission signal processing device on the transmitting end station side of an orthogonally polarized digital wireless communication line to which the present invention is applied, and Fig. 2 shows interference cancellation and waveform equalization on the receiving end station side. A block diagram showing an example of the circuit configuration. Figures 3a and 3b are examples of the configuration of a process for making orthogonal modulated signals uncorrelated on the transmitting side. Figures 4a and b are the phases of the demodulated baseband signal on the receiving side. FIG. 3 is a diagram illustrating a configuration example of a process for correcting a relationship. In the figure, 1v, 1h... code conversion circuit, 2v, 2
h...Parity counting circuit, 3v, 3h...Speed conversion circuit, 4v, 4h...Scramble circuit, 5
v, 5h... code sequence generator, 6v, 6h... transmission signal processing device, 7... bit clock generator,
8...Frame clock generator, 9v, 9h...
Detector, 10v, 10h... Waveform equalizer, 11
v, 11h...Identification judgment circuit, 12v, 12h...
...Interference cancellation circuit, 13v, 13h...Waveform equalization correlator, 14v, 14h...Interference control correlator, F...
…flipflop.

Claims (1)

[Claims] 1. In a multiphase multilevel digital radio communication system that has at least one set of transmitting devices that transmit n-sequence signals using two mutually orthogonal polarizations, the transmission side has n-sequence signals of one polarization. A delay circuit that delays at least one series of baseband signals among the baseband signals is provided to make the relationship between mutually orthogonal multiphase multilevel digital modulation signals uncorrelated, and the receiving side corresponds to one of the polarizations. Compensating for the delay applied to the n-series demodulated baseband signals on the transmitting side, the n-series demodulated baseband signals are made to be the same sequence as the n-series baseband signals before the delay on the transmitting side. 1. A digital wireless communication system, characterized in that a delay circuit is provided to perform processing such that the phase relationship between each n series of baseband signals is corrected.