JP2023092671A - Clock recovery method and wireless communication system - Google Patents

Abstract

To provide a clock recovery method which can improve the pull-in performance of clock timing synchronization and a wireless communication system that implements the clock recovery method.SOLUTION: In a wireless communication system, a clock recovery method executed by a transmission device 2 includes: transmitting a data pattern having the same symbol point for two consecutive symbols as a synchronizing signal; a receiving device receiving the synchronizing signal and synchronizing clock timing by using the synchronizing signal; and the receiving device synchronizing clock timing by using a phase error stored before the line disconnection, when a line disconnection occurs after the clock timing synchronization is established.SELECTED DRAWING: Figure 1

Description

The present invention relates to a clock recovery method for performing clock recovery applied to wireless communication performed via a communication satellite, for example, and a wireless communication system for executing such a clock recovery method.

In a receiving device of a wireless communication system, processing is performed to synchronize the timing of a clock used when demodulating a modulated signal transmitted from a transmitting device with the timing of a clock when modulated by the transmitting device. As a method of synchronizing clock timing, there is a method of estimating the phase at the time of modulation in the transmitting device from the analog signal received by the receiving device and establishing clock timing synchronization based on the estimated phase.

As a conventional mechanism for estimating the phase of the clock used for demodulation, limiter processing is performed individually for the in-phase and quadrature components of the signal used for estimating the clock phase among the signals after quadrature detection of the received signal. By performing waveform shaping using limiter means and a filter with a higher roll-off rate than normal communication, clock component extracting means for individually extracting clock components from each signal after limiter processing, and clock component extracting means a clock phase estimation signal calculating means for squaring each of the extracted clock components, adding the squared values, and using the result as a clock phase estimation signal; and a phase estimating means for estimating the clock phase is known (see Patent Document 1).

JP 2010-88035 A

By the way, narrowing the interval between communication channels is an effective means for realizing effective use of frequencies. In digital modulation, the channel spacing can be narrowed by lowering the roll-off rate as the adjustment of the channel spacing. However, if the roll-off rate is low, the detection accuracy of the clock timing is lowered, so there is a problem that the synchronization performance of the clock timing is degraded. In particular, in an environment with a low C/N (Carrier to Noise ratio), there is a problem that the pull-in performance of clock timing synchronization is greatly degraded.

In the technique disclosed in Patent Document 1, a limiter is inserted into the detection signal of the clock timing to equalize variations in timing, thereby improving the detection accuracy. There is a problem that the degree of improvement for noise is small.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a clock recovery method and a wireless communication system that implements such a clock recovery method, which can improve the pull-in performance of clock timing synchronization.

In order to solve the above-mentioned problems, the clock recovery method according to the present invention is such that a transmitting device transmits a data pattern having the same symbol point for two consecutive symbols as a synchronization signal, and a receiving device receives the synchronization signal. Then, synchronization of clock timing is performed using the synchronization signal.

In the clock recovery method according to the present invention, when line disconnection occurs after synchronization of the clock timing is established, the receiving-side device reproduces the clock using the phase error stored before the line disconnection. Timing synchronization processing may be performed.

In the clock recovery method according to the present invention, when synchronization of clock timing cannot be established even after a predetermined period of time has elapsed since the line disconnection occurred, the receiving side device may to request transmission of the synchronization signal.

In the clock recovery method according to the present invention, the transmitting device may filter the synchronization signal.

A radio communication system according to the present invention is characterized by executing the clock recovery method described above.

According to the clock recovery method and the radio communication system according to the present invention, the clock timing synchronization processing is performed using the data pattern that has the same symbol point for two consecutive symbols. is a signal that is less susceptible to the difference in the roll-off ratios of the roll-off filters, it is possible to improve the pull-in performance of clock timing synchronization.

According to the clock recovery method and the wireless communication system according to the present invention, if the phase error stored before the line disconnection is used to perform the clock timing synchronization processing, it is possible to perform the clock timing synchronization at the time of the line disconnection. Clock synchronization processing can be performed quickly.

According to the clock recovery method and the wireless communication system according to the present invention, when the synchronization signal is transmitted when a predetermined time has elapsed after the occurrence of the line disconnection, the clock at the time of the line disconnection synchronous processing can be performed appropriately without taking unnecessary time.

According to the clock recovery method and the radio communication system according to the present invention, when the synchronization signal is subjected to filtering, the data pattern having the same symbol point for two consecutive symbols is transmitted. It becomes possible to improve the spectral mask.

1 is a functional block diagram showing a schematic configuration of a transmission-side device that constitutes a radio communication system that executes a clock recovery method according to an embodiment of the present invention; FIG. 1 is a functional block diagram showing a schematic configuration of a receiving-side device that constitutes a radio communication system that executes a clock recovery method according to an embodiment of the present invention; FIG. FIG. 3 is a diagram for explaining an outline of a procedure of clock synchronization processing between the transmitting side device in FIG. 1 and the receiving side device in FIG. 2; FIG. 10 is a diagram showing an example of a data pattern in which two consecutive symbols are the same symbol point; FIG. 10 is a diagram showing an example of a typical waveform diagram of an output eye pattern after quadrature detection processing; (A) is an example of a waveform diagram of an eye pattern when the roll-off rate is 0.5. (B) is an example of a waveform diagram of an eye pattern when the roll-off rate is 0.05. FIG. 10 is a diagram showing a difference in frequency characteristics of roll-off filters due to a difference in roll-off rate; FIG. 10 is a diagram showing an example of a waveform diagram of an output eye pattern after quadrature detection processing when a data pattern having the same symbol point for two consecutive symbols is used; (A) is an example of a waveform diagram of an eye pattern when the roll-off rate is 0.5. (B) is an example of a waveform diagram of an eye pattern when the roll-off rate is 0.05. FIG. 3 is a diagram for explaining an outline of a procedure of clock synchronization processing at the time of line disconnection between the transmission-side device in FIG. 1 and the reception-side device in FIG. 2 ; FIG. 9 is a functional block diagram for explaining the processing contents in the receiving-side device of FIG. 2 related to the clock synchronization processing at the time of line disconnection of FIG. 8; FIG. 4 is a diagram showing a frequency spectrum shape of a signal output from a roll-off filter; (A) is a diagram showing a general frequency spectrum shape. (B) is a diagram showing a frequency spectrum shape when a data pattern in which two consecutive symbols are the same symbol point is used. FIG. 10 is a functional block diagram showing another example of the schematic configuration of a transmission-side device that constitutes a wireless communication system that executes the clock recovery method according to the present invention;

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on the illustrated embodiments.

In this embodiment, between the transmitting side device 2 and the receiving side device 3 (including between two communication devices capable of transmitting and receiving and performing two-way communication) via a communication satellite (in other words, A case where the clock recovery method is executed in a radio communication system 1 that performs radio communication (using a satellite communication line) will be described as an example. Illustrations and explanations of circuit elements that are not related to the gist of the present invention will be omitted. It is assumed that the circuit element to be used is appropriately provided.

FIG. 1 is a functional block diagram showing a schematic configuration of a transmission-side device 2 that constitutes a radio communication system 1 that executes a clock recovery method according to an embodiment of the present invention.

The transmitting device 2 has a synchronizing data generating section 21, a changeover switch 22, a header attaching section 23, a mapping section 24, and a modulating section 25 as components particularly related to the present invention.

The synchronization data generator 21 performs a process of synchronizing the timing of the clock used for demodulation by the receiving device 3 with the timing of the clock used when the transmitting device 2 modulates (referred to as “clock synchronization processing”). It generates and outputs a signal to be used (called a "synchronization signal").

One end (specifically, the output side) of the switch 22 is connected to the header adding section 23, and the other end (specifically, the input side) is connected to the synchronization data generating section 21, or is connected to the normal signal. (that is, a transmission signal composed of information/data transmitted from the transmitting side device 2 to the receiving side device 3).

The header addition unit 23 adds a synchronization signal to a signal frame transmitted from the transmission-side device 2 to the reception-side device 3 when the signal frame is data output from the synchronization data generation unit 21. a header (including a unique word) containing information identifying the , and information identifying that the signal frame is a normal signal when the signal frame is information/data from a normal signal transmission system ( In other words, a header (including a unique word) containing information similar to that of a normal signal is added and output.

It should be noted that it is not essential that the header contains the information identifying the synchronization signal, and the header may not contain the information identifying the synchronization signal.

The mapping unit 24 converts the signal frame (bit string signal) output from the header attaching unit 23 into a unit of symbol having a predetermined number of bits, for example, QPSK (Quadrature Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). Mapping processing is performed by mapping to signal points on a constellation determined by a predetermined digital quadrature modulation method, and symbols as a result of the mapping processing are output in units of signal frames.

The modulation unit 25 modulates an analog signal obtained by digital-analog conversion of the signal frame output from the mapping unit 24 into a radio frequency (RF) radio signal and outputs the radio signal.

The radio signal output from the modulation unit 25 is subjected to amplification processing or the like as necessary, is input to an antenna (not shown), and is radiated into space as radio waves via the antenna.

FIG. 2 is a functional block diagram showing a schematic configuration of the receiving side device 3 that constitutes the wireless communication system 1 that executes the clock recovery method according to the embodiment of the present invention.

The receiving device 3 includes a roll-off filter 31, a phase error detector 32, a low-pass filter 33, a numerically controlled oscillator 34, a multiplier 35, a demapping unit 36, and a synchronization detector 37 as components particularly related to the present invention. have.

The roll-off filter 31, the phase error detector 32, the low-pass filter 33, the numerically controlled oscillator 34, and the multiplier 35 of the receiving device 3 demodulate the received signal (that is, the modulated signal transmitted from the transmitting device 2). A clock recovery circuit is configured to recover a clock signal (in other words, a sampling clock) to be used at the time from a received signal.

The clock recovery circuit (the multiplier 35 thereof) receives, for example, an intermediate frequency (IF In-phase baseband signal and Quadrature-phase baseband signal with phases orthogonal to each other, which are obtained by subjecting the signal to quadrature detection processing, are input. (both are analog signals). In the description of the embodiments, the in-phase component and the quadrature component are not distinguished from each other, and the contents are common to both. In the drawings, the in-phase component signal and the quadrature component signal are represented by one signal line.

The roll-off filter 31 (ROF: Roll-Off Filter) is composed of a low-pass filter (LPF: Low Pass Filter) realized as a finite-length impulse response, and digitally converts the in-phase and quadrature components output from the multiplier 35. A signal input is received, and band limitation processing is applied to each of the digital signals before output.

The phase error detector 32 receives the digital signals of the in-phase component and the quadrature component output from the roll-off filter 31, and detects the phase error of each of the digital signals (that is, the phase error of the digital signal with respect to the ideal phase). /shift) and outputs a signal indicating the phase error.

Specifically, the phase error detection unit 32 detects the timing at which the amplitude of the signal amplitude eye pattern (also called “eye diagram”; see FIG. 5) passes through zero (in other words, the timing at which the sign of the baseband signal is inverted). ; also called "zero-cross point"), the deviation of the sampling phase at the multiplier 35 from the optimum point is detected as a phase error, and a signal indicative of the phase error is output. The phase error detector 32 uses the midpoint of a predetermined time interval (that is, one symbol period) as a zero-crossing point, and adjusts the sampling timing so that the zero-crossing point comes to an amplitude of zero (or near zero). Synchronize symbol timing.

A low-pass filter 33 (LPF) receives the signal indicating the phase error output from the phase error detecting section 32, applies band-limiting processing to the signal indicating the phase error, and outputs the signal (specifically, essentially removes the high frequency components and allows only the low frequency components to pass).

A numerically controlled oscillator (NCO) receives a signal indicating the phase error output from the low-pass filter 33 and outputs a clock having a frequency corresponding to the value of the phase error as a sampling clock.

The multiplier 35 receives the in-phase component and quadrature component baseband signals (which are analog signals) input to the clock recovery circuit, and receives the sampling clock output from the numerically controlled oscillator 34, Based on the sampling clock, each of the baseband signals is subjected to sampling processing, converted into digital signals of in-phase components and quadrature components, and output.

The demapping unit 36 receives the input of the digital signal output from the clock recovery circuit (the roll-off filter 31 therein), and converts the digital signal into a constellation determined by a predetermined digital quadrature modulation method. Demapping processing (that is, inverse processing of the mapping processing in the mapping unit 24 of the transmitting device 2) is performed, demodulation processing is performed, and a signal frame (bit string signal) is output.

The synchronization detection unit 37 receives the input of the signal frame output from the demapping unit 36, and detects a known pattern such as a unique word (UW) for clock synchronization processing included in the header of the signal frame. A process of detecting and judging phase synchronization/asynchronization is performed.

(Clock synchronization processing)
In the clock recovery method according to the embodiment, the transmitting device 2 transmits a data pattern having the same symbol point for two consecutive symbols as a synchronization signal, and the receiving device 3 receives the synchronization signal and reproduces the synchronization signal. The signal is used to perform clock timing synchronization processing.

FIG. 3 is a diagram for explaining an outline of the procedure of clock synchronization processing between the transmitting side device 2 and the receiving side device 3 that constitute the wireless communication system 1 that executes the clock recovery method according to the embodiment.

The synchronization data generator 21 of the transmission-side device 2 generates and outputs a data pattern in which two consecutive symbols have the same symbol point as a synchronization signal during clock synchronization processing.

FIG. 4 shows an example of a data pattern in which two consecutive symbols have the same symbol point. As in the example shown in FIG. 4, the synchronization data generator 21 includes, for example, a signal generator 211 that generates data that enables symbol mapping once every two symbol periods, and an S/P converter 212 (Serial- to-Parallel converter). Specifically, a PN (Pseudo random Noise) code generator may be used as the signal generator 211 in consideration of randomization.

The changeover switch 22 has its input side connected to the synchronization data generation unit 21 during clock synchronization processing.

Then, a synchronization signal is transmitted from the transmitting device 2 to the receiving device 3 .

The reception-side device 3 performs clock synchronization processing using the synchronization signal transmitted from the transmission-side device 2, and when the synchronization detection unit 37 determines that the phases are synchronized, the transmission-side device 2: A signal (referred to as a "synchronization completion notification signal") is transmitted to notify that the synchronization of the clock in the receiving device 3 has been completed.

By establishing clock synchronization, the receiving device 3 can acquire the information in the header of the received signal. Therefore, the header of the received signal contains information for identifying the synchronization signal. In this case, the receiver device 3 may transmit a synchronization completion notification signal to the transmitter device 2 assuming that clock synchronization has been completed by receiving the synchronization signal.

Here, the receiving device 3 detects the timing at which the signal amplitude eye pattern (see FIG. 5) crosses amplitude=0 (in other words, the timing at which the sign of the baseband signal is inverted; referred to as the “zero crossing point”). Establish symbol synchronization by a zero-crossing detection method. Specifically, the phase error detector 32 of the receiving device 3 sets the midpoint of a predetermined time interval (that is, one symbol period) as a zero-crossing point, and the zero-crossing point becomes amplitude=0 (or near zero). Synchronization of the symbol timing is established by adjusting the sampling timing so that the

The zero-crossing point is well-defined and can be easily detected with a high roll-off rate, as shown in FIG. 5(A). On the other hand, as shown in FIG. 4B, when the roll-off rate is low, the zero-crossing point becomes unclear due to large fluctuations in the zero-crossing point due to the occurrence of jitter, making it difficult to detect. symbol synchronization may not be obtained.

FIG. 6 shows the difference in the frequency characteristics of the roll-off filter (specifically, the difference in the shape of the frequency function H(f)) due to the difference in the roll-off rate. From FIG. 6, it is confirmed that the influence of the roll-off factor α is small when the frequency component of the signal pattern is 1/2 or less of the symbol frequency f ₀ (that is, from -f ₀ /2 to f ₀ /2). . It is also advantageous for noise.

According to the characteristics shown in FIG. 6, when a data pattern with the same symbol point for two consecutive symbols is transmitted from the transmitting device 2 as a synchronization signal, the signal with the same symbol point for two consecutive symbols has a frequency shown in FIG. Since the signal in the vicinity of the frequency f of zero becomes the main signal, even if it is filtered by the roll-off filter, the cut area is small and does not cause a large change. is a signal. That is, by transmitting a data pattern having the same symbol point for two consecutive symbols as a synchronization signal from the transmitting device 2, the frequency component of 1/2 of the symbol frequency _f0 is affected by the low roll-off rate α. Since it is a difficult signal, it is possible to easily detect the zero-crossing point without depending on the roll-off rate α.

Specifically, for example, when a data pattern having the same symbol point for two consecutive symbols is transmitted from the transmitting apparatus 2 as a synchronization signal, the zero-crossing points differ depending on the roll-off rate, as shown in FIG. is small and the roll-off rate is high (see (A) in the same figure) and low (see (B) in the same figure).

FIG. 7 shows the frequency spectrum shape of the signal output from the roll-off filter. FIG. 1(A) is a diagram showing a general frequency spectrum shape. FIG. 2B is a diagram showing the shape of the frequency spectrum when a data pattern that has the same symbol point for two consecutive symbols is used. Note that the roll-off rate is 0.05 in both (A) and (B) of FIG.

When the transmission side device 2 receives the synchronization completion notification signal transmitted from the reception side device 3, the connection on the input side of the changeover switch 22 is changed from the connection with the synchronization data generation unit 21 to the connection with the normal signal transmission system. switch to

Note that the changeover switch 22 may be switched to the connection with the normal signal transmission system after a predetermined time has elapsed since the connection with the synchronization data generation unit 21 . In this case, the predetermined time is an appropriate length of time [seconds] after taking into consideration the length of time [seconds] assumed as the time required for clock synchronization in the receiving device 3, for example. is set appropriately. Also, in this case, the header may not include information for identifying the synchronization signal.

A normal signal is then transmitted from the transmitting device 2 to the receiving device 3 .

The clock synchronization process may be performed for each communication only at the start of the communication, or may be performed repeatedly at predetermined time intervals set in advance in addition to the start of the communication. .

(Synchronization of clock when line is disconnected)
In the clock recovery method according to the embodiment, when line disconnection occurs after clock timing synchronization is established, the reception-side device 3 restores the clock timing using the phase error stored before the line disconnection. I'm trying to do the synchronization process.

FIG. 8 illustrates the case of line disconnection (for example, momentary disconnection) between the transmitting device 2 and the receiving device 3 constituting the wireless communication system 1 that executes the clock recovery method according to the embodiment (specifically, For example, when the information of the header of the received signal cannot be acquired), it is a diagram for explaining the outline of the procedure of clock synchronization processing.

FIG. 9 is a functional block diagram for explaining the contents of processing, especially in the receiving device 3, which is related to the clock synchronization processing at the time of line disconnection shown in FIG.

The receiving device 3 also has a memory 38 and a changeover switch 39 as components for synchronizing the clock especially when the line is disconnected.

Low-pass filter 33 includes multiplier 331 , adder 332 and delay device 333 .

The multiplier 331 receives the signal indicating the phase error output from the phase error detector 32, multiplies the signal indicating the phase error by a predetermined filter coefficient, and outputs the result.

The adder 332 receives the signal output from the multiplier 331 and the signal output from the delay device 333 via the switch 39, adds the two signals, and outputs the result.

Alternatively, the adder 332 receives the input of the signal output from the multiplier 331 and the input of the signal stored in the memory 38 via the switch 39, adds the two signals, and outputs the result. .

The delay device 333 receives the signal output from the adder 332, delays the signal by a predetermined time, and outputs the delayed signal. The predetermined time is set, for example, to a time length corresponding to one sampling period/one symbol period based on the sampling clock.

The memory 38 receives the signal output from the delay device 333 and stores the signal.

One end (specifically, the output side) of the switch 39 is connected to the adder 332 , and the other end (specifically, the input side) is connected to the output side of the delay device 333 or connected to the memory 38 . Switch to connect.

The changeover switch 39 has its input side connected to the output side of the delay device 333 and connects the output side of the delay device 333 and the adder 332 when clock synchronization processing is performed.

When clock synchronization is established by the clock synchronization process (specifically, for example, the header information of the received signal can be acquired), the receiving-side device 3 receives a value output from the low-pass filter 33 (specifically, Specifically, the phase error) is stored in the memory 38 .

The value (specifically, the phase error) to be stored in the memory 38 is obtained by performing clock synchronization processing using a synchronization signal transmitted from the transmitting device 2 at the start of each communication. The hour value is stored.

The value (specifically, the phase error) to be stored in the memory 38 is also set in advance by a normal clock synchronization process (that is, without using a synchronization signal transmitted from the transmission-side device 2). It may be stored at predetermined time intervals and updated at the predetermined time intervals.

The value (specifically, the phase error) to be stored in the memory 38 is set in advance for each communication when the clock synchronization process using the synchronization signal transmitted from the transmission-side device 2 is added at the start of the communication. In the case where the operation is performed repeatedly at predetermined time intervals, the value each time the operation is performed at the predetermined time intervals may be stored and updated.

When line disconnection occurs after clock synchronization is established, the receiving device 3 performs clock synchronization processing using the value (specifically, phase error) stored in the memory 38 to reproduce the clock. try. At this time, the input side of the switch 39 is connected to the memory 38, and the value stored in the memory 38 is supplied to the low-pass filter 33 (specifically, the adder 332).

Although the clock synchronization processing is performed using the values stored in the memory 38, even if a predetermined time has passed since the line disconnection occurred, the clock synchronization may not be possible depending on the processing using the values stored in the memory 38. cannot be established (specifically, for example, the header information of the received signal cannot be acquired), the receiving device 3 requests the transmitting device 2 to transmit a synchronization signal.

When receiving the synchronization signal transmission request from the reception side device 3, the transmission side device 2 changes the connection on the input side of the changeover switch 22 from the connection with the normal signal transmission system to the synchronization data generation section 21. switch to a connection with

Then, a synchronization signal is transmitted from the transmitting device 2 to the receiving device 3 .

The reception-side device 3 performs clock synchronization processing using the synchronization signal transmitted from the transmission-side device 2, and when the synchronization detection unit 37 determines that the phases are synchronized, the transmission-side device 2: Send a synchronization completion notification signal.

When the transmission side device 2 receives the synchronization completion notification signal transmitted from the reception side device 3, the connection on the input side of the changeover switch 22 is changed from the connection with the synchronization data generation unit 21 to the connection with the normal signal transmission system. switch to

A normal signal is then transmitted from the transmitting device 2 to the receiving device 3 .

According to the clock recovery method and the wireless communication system 1 according to the embodiment, the clock timing is synchronized using a data pattern that has the same symbol point for two consecutive symbols. Since the signal at the symbol point is a signal that is not easily affected by the difference in the roll-off rate of the roll-off filter, it is possible to improve the pull-in performance of clock timing synchronization.

According to the clock recovery method and the wireless communication system 1 according to the embodiment, the clock timing is synchronized using the phase error stored before the line disconnection occurs. clock synchronization processing can be performed quickly.

According to the clock recovery method and the wireless communication system 1 according to the embodiment, since the synchronization signal is transmitted when a predetermined time has passed since the line disconnection occurred, It is possible to appropriately perform clock synchronization processing without spending unnecessary time.

Although the embodiments of the present invention have been described above, the specific configuration is not limited to the above-described embodiments. Included in the invention.

For example, in a data pattern in which two consecutive symbols have the same symbol point, the out-of-band characteristics are slightly raised as shown in FIG. MHz] range, the power [dBm] rises slightly), so if the transmission spectrum mask is not satisfied as a wireless communication system, a filter may be added to the transmission system. Specifically, for example, as shown in FIG. 11, the modulating section 25 of the transmitting device 2 may be configured to include a roll-off filter 251, a low-pass filter 252, a switch 253, and a quadrature modulator 254. be done. The roll-off filter 251 applies band-limiting processing to the signal output from the mapping unit 24 and outputs the result. Low-pass filter 252 is configured to suppress out-of-band characteristics of the signal output from roll-off filter 251 to improve the spectral mask (in other words, satisfy the spectral mask). The change-over switch 253 connects the output side of the low-pass filter 252 and the input side of the quadrature modulator 254 during the clock synchronization process (that is, when transmitting the synchronization signal) (state shown in FIG. 11). When the synchronization is completed and the normal signal is transmitted, the output side of the roll-off filter 251 and the input side of the quadrature modulator 254 are connected. The quadrature modulator 254 quadrature-modulates the signal output from the roll-off filter 251 or the low-pass filter 252 and outputs the modulated signal. By configuring the modulation unit 25 of the transmission-side device 2 in this way, the synchronization signal is filtered by the low-pass filter 252, so that a data pattern having the same symbol point for two consecutive symbols is transmitted. The spectral mask at the time is improved.

1 wireless communication system 2 transmitting device 21 synchronization data generation unit 211 signal generator 212 S/P converter 22 changeover switch 23 header addition unit 24 mapping unit 25 modulation unit 251 roll-off filter 252 low-pass filter 253 changeover switch 254 quadrature modulation Unit 3 Receiving side device 31 Roll-off filter 32 Phase error detector 33 Low-pass filter 331 Multiplier 332 Adder 333 Delay device 34 Numerically controlled oscillator 35 Multiplier 36 Demapping unit 37 Synchronization detector 38 Memory 39 Switch

Claims (5)

A transmitting device transmits a data pattern having the same symbol point for two consecutive symbols as a synchronization signal,
the receiving device receives the synchronization signal and uses the synchronization signal to perform clock timing synchronization processing;
A clock recovery method characterized by: When line disconnection occurs after synchronization of the clock timing is established,
The receiving-side device performs clock timing synchronization processing using the phase error stored before the line disconnection occurs.
2. The clock recovery method according to claim 1, wherein: When clock timing synchronization cannot be established even after a predetermined period of time has elapsed since the line disconnection occurred,
the receiving device requests the transmitting device to transmit the synchronization signal;
3. The clock recovery method according to claim 2, wherein: Filtering is performed on the synchronization signal in the transmitting device.
4. The clock recovery method according to any one of claims 1 to 3, characterized in that: performing the clock recovery method according to any one of claims 1 to 4;
A wireless communication system characterized by:

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