JPH0553267U - High density multilayer circuit board - Google Patents
High density multilayer circuit boardInfo
- Publication number
- JPH0553267U JPH0553267U JP11053291U JP11053291U JPH0553267U JP H0553267 U JPH0553267 U JP H0553267U JP 11053291 U JP11053291 U JP 11053291U JP 11053291 U JP11053291 U JP 11053291U JP H0553267 U JPH0553267 U JP H0553267U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- board
- circuit
- multilayer circuit
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】
【構成】 基板両面に回路パターンを形成した複数の印
刷回路樹脂基板を半田バンプ6を介して積層した多層回
路基板において、あらかじめ内装材1のバンプ接合面と
反対の面にそれと対応して回路パターン2より厚めの金
属箔からなる半田バンプ衝合用均圧パッド10を形成し
ておき、加圧・昇温時に圧力の均衡を図る。
【効果】 基板の貼り合わせの面すべてにわたり歪の少
ない半田バンプ接合体が得られ、熱衝撃の繰り返しにも
破損を生じない高信頼性多層回路基板が得られる。
(57) [Summary] [Structure] In a multilayer circuit board in which a plurality of printed circuit resin boards having circuit patterns formed on both surfaces of the board are laminated via solder bumps 6, the surface opposite to the bump bonding surface of the interior material 1 is previously prepared. Correspondingly, the solder bump abutting pressure equalizing pad 10 made of a metal foil thicker than the circuit pattern 2 is formed in advance, and the pressure is balanced at the time of pressurizing / heating. [Effect] A solder bump bonded body having less distortion over the entire bonding surface of the boards can be obtained, and a highly reliable multilayer circuit board that does not suffer damage even when repeated thermal shock is obtained.
Description
【0001】[0001]
本考案は、複数の回路基板を半田バンプで接合する高密度多層回路基板に関す る。 The present invention relates to a high-density multilayer circuit board in which a plurality of circuit boards are joined by solder bumps.
【0002】[0002]
図2は従来例の断面説明図で、内装材1の裏面側の回路パターン2及び表面側 の回路パターン3と表装材4の裏面側の回路パターン5を半田バンプ6を介して 押圧7a、7bを加えながら昇温して内装材1と表装材4とを接合していた。 FIG. 2 is a cross-sectional explanatory view of a conventional example, in which a circuit pattern 2 on the back side of the interior material 1, a circuit pattern 3 on the front side, and a circuit pattern 5 on the back side of the cover material 4 are pressed via solder bumps 7a, 7b. The interior material 1 and the exterior material 4 were joined by raising the temperature while adding.
【0003】[0003]
しかしながら、この種の構成体は熱衝撃を加えた場合に一部の半田バンプ接合 体の剥離、または半田層内で結晶粒界に亀裂が生じ易いという欠点があった。 However, this type of structure has a drawback in that when a thermal shock is applied, a part of the solder bump joint is peeled off, or a crack is likely to occur at a crystal grain boundary in the solder layer.
【0004】 不具合を発生した試料を調査した結果、半田バンプを押圧接合する際の印刷回 路基板の樹脂層の変位量に関係することがわかった。すなわち、多数の半田バン プ接合体の一部には内装材1の裏面側に回路パターン2を形成していない押圧低 下領域8が存在している。このような裏面側に回路パターンを有しない領域では 、加圧・昇温により接合する場合に次のような歪が起こる。As a result of investigating the sample in which the defect has occurred, it has been found that it is related to the amount of displacement of the resin layer of the printed circuit board when the solder bumps are pressure bonded. That is, a part of the large number of solder bump joints has a pressure lowering area 8 in which the circuit pattern 2 is not formed on the back surface side of the interior material 1. In such an area having no circuit pattern on the back surface side, the following distortion occurs when joining is performed by pressurization / heating.
【0005】 裏面側の回路パターンを構成している銅箔とその厚さ18μmに相当する空隙 部分とが同時に押圧されると、樹脂層の軟化に伴い、内装材1の圧縮、引張りに よって変形し、半田の固化接合領域に歪域9が生じる。このため、低温域から高 温域にわたる温度範囲で熱衝撃を加えた場合(熱衝撃試験等)、半田界面に応力 が蓄積され、そこに微少亀裂が生じ破損の原因となった。When the copper foil forming the circuit pattern on the back surface side and the void portion corresponding to the thickness of 18 μm are pressed at the same time, the interior material 1 is deformed by compression and tension due to softening of the resin layer. However, a strain region 9 is generated in the solidified joining region of the solder. Therefore, when a thermal shock was applied in a temperature range from a low temperature range to a high temperature range (such as a thermal shock test), stress was accumulated at the solder interface, causing microcracks to cause damage.
【0006】[0006]
本考案は、これらの課題を解決することを目的とし、目的を達成するために基 板両面に回路パターンを形成した複数の印刷回路樹脂基板を半田バンプを介して 積層して成る多層回路基板において、印刷回路樹脂基板のバンプ接合面と異なる 面に、半田バンプに対応させて金属箔を設け、かつ金属箔の厚さを同じ面上の回 路パターンの厚さ以上に形成したことを特徴とするもので、以下実施例につき図 面により詳細に説明する。 The present invention is intended to solve these problems, and in order to achieve the purpose, a multilayer circuit board is formed by laminating a plurality of printed circuit resin boards having circuit patterns formed on both sides of a substrate through solder bumps. The printed circuit resin board is provided with a metal foil corresponding to the solder bump on a surface different from the bump bonding surface, and the thickness of the metal foil is formed to be equal to or larger than the circuit pattern thickness on the same surface. However, the embodiments will be described in detail below with reference to the drawings.
【0007】[0007]
図1は本考案の実施例の断面説明図で、内装材1の裏面側に回路パターン2と 共に金属箔からなる半田バンプ衝合用均圧パッド10を設ける。内装材1の表面 側の回路パターン3と表装材4の裏面側の回路パターン5を半田バンプ6を介し て押圧7a、7bを加えながら昇温して内装材1と表装材4とを接合する。 FIG. 1 is a cross-sectional explanatory view of an embodiment of the present invention, in which a circuit pattern 2 and a solder bump abutting pressure equalizing pad 10 made of metal foil are provided on the back surface side of an interior material 1. The circuit pattern 3 on the front surface side of the interior material 1 and the circuit pattern 5 on the back surface side of the exterior material 4 are heated while applying pressure 7a and 7b via the solder bumps 6 to bond the interior material 1 and the exterior material 4 to each other. ..
【0008】 このような構成にした場合、半田バンプ衝合用均圧パッド10と回路パターン 2に背位する表面側の回路パターン3と3´は、均一な押圧条件が満たされた半 田バンプ接合を行うことができる。In the case of such a configuration, the solder bump abutting pressure equalizing pad 10 and the circuit patterns 3 and 3 ′ on the front side which are behind the circuit pattern 2 are solder bump bonding in which uniform pressing conditions are satisfied. It can be performed.
【0009】 この結果、圧縮、押圧の終了後も張力作用が発生せず、接合部分は低歪となり 、熱衝撃の繰り返しにも十分耐えられる。次にさらに詳しく説明する。As a result, no tension action is generated even after the completion of compression and pressing, the joint portion has low strain, and it is sufficiently durable against repeated thermal shock. Next, a more detailed description will be given.
【0010】 厚さ18μmの銅箔による回路パターンが両面にある内装材1の1つの面に、 表装材4と接合する1mm径のバンプランドを設ける。バンプランドの背面側で それと対応する位置に1.5mm径の半田バンプ衝合用均圧パッド10を設ける 。表装材4と接合する側の面に錫・鉛共晶半田クリームを印刷し、窒素雰囲気の リフロー処理を行い半田バンプ6を形成する。Bump lands having a diameter of 1 mm to be joined to the covering material 4 are provided on one surface of the interior material 1 having a circuit pattern of a copper foil having a thickness of 18 μm on both surfaces. A 1.5 mm diameter solder bump abutting pressure equalizing pad 10 is provided on the back side of the bump land at a position corresponding thereto. A tin / lead eutectic solder cream is printed on the surface to be joined to the surface material 4, and a reflow process in a nitrogen atmosphere is performed to form solder bumps 6.
【0011】 次に、あらかじめ回路パターンを設けた表装材4と内装材1を衝合し、ディス パージョンプレートを押圧7a、7bの作用する面に配して、温度230℃、押 圧5.5Kg/cm2 を加え表装材4と内装材1とを半田バンプ接合する。Next, the interior material 1 is abutted against the surface material 4 provided with a circuit pattern in advance, the dispersion plate is placed on the surface on which the pressures 7a and 7b act, and the temperature is 230 ° C. and the pressure is 5.5 Kg. / Cm @ 2 is added and the mounting material 4 and the interior material 1 are solder bump bonded.
【0012】[0012]
以上説明したように、基板の貼り合わせの面すべてにわたり歪の少ない半田バ ンプ接合体が得られ、反復する熱衝撃にも破損のない高信頼性の多層回路基板と なすことができる。 As described above, a solder bump bonded body having less distortion over the entire bonding surface of the boards can be obtained, and a highly reliable multilayer circuit board that is not damaged by repeated thermal shock can be formed.
【図1】本考案の実施例の断面説明図。FIG. 1 is an explanatory sectional view of an embodiment of the present invention.
【図2】従来例の断面説明図。FIG. 2 is a sectional explanatory view of a conventional example.
1 内装材 2、5 回路パターン 3、3´ 回路パターン 4 表装材 6 半田バンプ 8 押圧低下領域 9 歪域 10 半田バンプ衝合用均圧パッド 1 Interior Material 2, 5 Circuit Pattern 3, 3'Circuit Pattern 4 Surface Material 6 Solder Bump 8 Depressed Area 9 Strained Area 10 Solder Bump Abutting Pressure Equalizing Pad
Claims (1)
の印刷回路樹脂基板を半田バンプを介して積層して成る
多層回路基板において、 前記印刷回路樹脂基板のバンプ接合面と異なる面に、前
記半田バンプに対応させて金属箔を設け、かつ該金属箔
の厚さを同じ面上の回路パターンの厚さ以上に形成した
ことを特徴とする高密度多層回路基板。1. A multi-layer circuit board comprising a plurality of printed circuit resin boards having circuit patterns formed on both sides of the board, wherein the printed circuit resin boards are laminated via solder bumps, wherein the solder is provided on a surface different from a bump bonding surface of the printed circuit resin board. A high-density multilayer circuit board, characterized in that a metal foil is provided corresponding to the bumps, and the thickness of the metal foil is formed to be equal to or greater than the thickness of a circuit pattern on the same surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11053291U JPH0553267U (en) | 1991-12-17 | 1991-12-17 | High density multilayer circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11053291U JPH0553267U (en) | 1991-12-17 | 1991-12-17 | High density multilayer circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0553267U true JPH0553267U (en) | 1993-07-13 |
Family
ID=14538199
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11053291U Pending JPH0553267U (en) | 1991-12-17 | 1991-12-17 | High density multilayer circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0553267U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02178995A (en) * | 1988-12-29 | 1990-07-11 | Japan Radio Co Ltd | Manufacture of multilayer printed board |
JPH0360095A (en) * | 1989-07-27 | 1991-03-15 | Japan Radio Co Ltd | Manufacture of multilayer printed circuit board |
-
1991
- 1991-12-17 JP JP11053291U patent/JPH0553267U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02178995A (en) * | 1988-12-29 | 1990-07-11 | Japan Radio Co Ltd | Manufacture of multilayer printed board |
JPH0360095A (en) * | 1989-07-27 | 1991-03-15 | Japan Radio Co Ltd | Manufacture of multilayer printed circuit board |
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