JPH0553067B2 - - Google Patents

Info

Publication number
JPH0553067B2
JPH0553067B2 JP18090285A JP18090285A JPH0553067B2 JP H0553067 B2 JPH0553067 B2 JP H0553067B2 JP 18090285 A JP18090285 A JP 18090285A JP 18090285 A JP18090285 A JP 18090285A JP H0553067 B2 JPH0553067 B2 JP H0553067B2
Authority
JP
Japan
Prior art keywords
pin
wiring pattern
substrate
film substrate
grid array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18090285A
Other languages
Japanese (ja)
Other versions
JPS6240754A (en
Inventor
Akira Konishi
Teruo Wakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
I Pex Inc
Original Assignee
Dai Ichi Seiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Ichi Seiko Co Ltd filed Critical Dai Ichi Seiko Co Ltd
Priority to JP18090285A priority Critical patent/JPS6240754A/en
Priority to DE8686108770T priority patent/DE3675321D1/en
Priority to EP86108770A priority patent/EP0218796B1/en
Priority to US06/880,832 priority patent/US4823234A/en
Priority to KR1019860006161A priority patent/KR870002647A/en
Priority to CN198686105249A priority patent/CN86105249A/en
Publication of JPS6240754A publication Critical patent/JPS6240754A/en
Publication of JPH0553067B2 publication Critical patent/JPH0553067B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はピングリツドアレイ、特に、薄肉のプ
ラスチツク製フイルムを基板とするピングリツド
アレイに関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a pin grid array, and particularly to a pin grid array having a thin plastic film as a substrate.

(従来の技術) 従来、半導体装置のパツケージとしてデユアル
インラインパツケージ(以下、DIPという。)が
大部分を占めていたが、最近のLSIチツプの高集
積化や電子装置の小型化、高性能化に対する要求
の増大に伴い装置のピン数が増大し、DIPではピ
ン数の増加に限界があるため対応できないという
問題があつた。このため、最近では、セラミツク
基板にピンを複数列立設したピングリツドアレイ
が開発され、実用に供されてきている。
(Prior technology) Traditionally, dual in-line packages (hereinafter referred to as DIPs) have been the most popular package for semiconductor devices, but with the recent increase in the integration density of LSI chips and the miniaturization and high performance of electronic devices, As demand increased, the number of pins in devices increased, and DIP had the problem of not being able to handle this increase as there was a limit to the increase in the number of pins. For this reason, pin grid arrays in which multiple rows of pins are erected on a ceramic substrate have recently been developed and put into practical use.

(発明が解決しようとする問題点) しかしながら、従来のピングリツドアレイは、
セラミツク基板を採用しているため、コストが高
く、しかも基板が大きくなると共に、回路を微細
化することは困難であるという問題がある。この
ため、プリント配線基板技術を応用した比較的安
価なプラスチツク基板を用いたピングリツドアレ
イが開発されているが、製造工程での管理を厳し
くしなければ高精度のものが得られず、熱伝導を
高めるため金属製放熱板を組み込むと、接合工程
や接合部の封止工程など製造工程が増加するなど
の問題がある他、セラミツク基板を用いたものと
同様、ピングリツドアレイの薄型化が困難であつ
た。
(Problem to be solved by the invention) However, the conventional pin grid array
Since a ceramic substrate is used, there are problems in that the cost is high, the substrate becomes large, and it is difficult to miniaturize the circuit. For this reason, pingrid arrays have been developed using relatively inexpensive plastic substrates using printed wiring board technology, but high precision cannot be obtained without strict control during the manufacturing process. Incorporating a metal heat sink to increase conduction has problems such as increasing the manufacturing process such as bonding process and sealing process of the joint part, as well as making the pin grid array thinner as with ceramic substrates. was difficult.

本発明者は、前記問題を解決する手段として、
開口部を有し表面に配線パターンを形成されたプ
ラスチツクフイルム基板と、該フイルム基板に立
設され前記配線パターンに接続された複数のピン
と、前記フイルム基板の開口部を覆うようにフイ
ルム基板上に配置された金属製放熱板とからな
り、前記フイルム基板を放熱板の周縁部及びピン
と共に耐熱性樹脂で封入成形して一体化してなる
ことを特徴とするピングリツドアレイを開発し
た。
As a means to solve the above problem, the present inventor has provided the following:
a plastic film substrate having an opening and a wiring pattern formed on its surface; a plurality of pins standing upright on the film substrate and connected to the wiring pattern; We have developed a pin grid array, which consists of arranged metal heat sinks, and is made by integrally molding the film substrate together with the periphery of the heat sink and the pins using a heat-resistant resin.

しかしながら、このピングリツドアレイは、基
板が機械的強度の弱い薄肉のプラスチツクフイル
ムであるため、基板とピンと結合強度が弱く、ま
た、配線パターンとピンをハンダ付しても、基板
の配線パターンの接合強度が低いためピンと基板
との結合強度の向上に寄与せず、しかも、ハンダ
付による面接合方法を採用した場合はハンダ付加
工が繁雑になり、又、加工後、洗浄工程も必要と
なるなどの問題があることが明らかとなつた。
However, in this pin grid array, the board is made of a thin plastic film with low mechanical strength, so the bonding strength between the board and the pins is weak, and even if the wiring pattern and pins are soldered, the wiring pattern on the board Since the bonding strength is low, it does not contribute to improving the bonding strength between the pin and the board, and if surface bonding method using soldering is adopted, the soldering process becomes complicated and a cleaning process is also required after processing. It became clear that there were some problems.

従つて、本発明は、プラスチツクフイルムから
なる基板とピンとの結合強度を高め、信頼性が高
く高精度のピングリツドアレイを安価に製造でき
るようにすることを目的とするものである。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to increase the bonding strength between a plastic film substrate and pins, thereby making it possible to manufacture a highly reliable and highly accurate pin grid array at low cost.

(問題点を解決するための手段) 本発明は、前記問題を解決する手段として、表
面に配線パターンを形成されたプラスチツクフイ
ルムからなる基板と、該基板と配線パターンを貫
通する各貫通孔に挿入固定され前記配線パターン
に接続された複数のピンと、前記基板と該基板に
挿入固定されたピンの挿入側とを封入一体化する
樹脂封止部とを備えたピングリツドアレイにおい
て、前記貫通孔への挿入端側に段部を有するピン
を用い、その段部と挿入端側に形成された頭部と
で前記基板と配線パターンを挾持させるようにし
たものである。
(Means for Solving the Problems) As a means for solving the above-mentioned problems, the present invention provides a substrate made of a plastic film with a wiring pattern formed on its surface, and a plastic film inserted into each through-hole passing through the substrate and the wiring pattern. In a pin grid array comprising a plurality of pins fixed and connected to the wiring pattern, and a resin sealing part that encapsulates and integrates the board and the insertion side of the pin inserted and fixed to the board, the through hole A pin having a stepped portion on the insertion end side is used, and the substrate and wiring pattern are held between the stepped portion and a head formed on the insertion end side.

好ましい実施態様においては、フイルム基板の
配線パターンと反対側の表面上に貫通孔と同軸に
金属リングを形成し、該金属リングとフイルム基
板及び配線パターンとを前記貫通孔に嵌入された
段付きピンの段部と頭部とで挾持させることが行
なわれる。
In a preferred embodiment, a metal ring is formed coaxially with the through hole on the surface of the film substrate opposite to the wiring pattern, and the metal ring, the film substrate, and the wiring pattern are connected to each other by a stepped pin fitted into the through hole. It is held between the stepped part and the head.

(作用) 本発明は、頭部側に段部のあるピンを用い、そ
の頭部をフイルム基板及び配線パターンを貫通す
る貫通孔に嵌入し、その先端部をかしめて段部と
頭部とで基板及び配線パターンを挾持させると、
配線パターンが基板を機械的に補強する状態とな
り、ピンと基板間の結合強度の向上に寄与し、ピ
ンのフイルム基板への取り付けと配線パターンへ
の接続とが同時に行なわれる。また、フイルム基
板の片側表面に形成された配線パターンの反対側
表面に貫通孔と同軸に金属リングを形成し、ピン
の段部と頭部とでこれらを挾持すると、フイルム
基板が金属リングと配線パターンとで挾持された
状態となつて補強され、ピンを嵌入固定して立設
した際のピンと基板との結合度を向上させ、これ
によつてプラスチツク製フイルムを基板とするピ
ングリツドアレイの信頼性を一段と向上させる。
(Function) The present invention uses a pin with a step on the head side, fits the head into a through hole penetrating the film substrate and the wiring pattern, and caulks the tip to connect the step and the head. When the board and wiring pattern are held together,
The wiring pattern mechanically reinforces the board, contributing to improving the bonding strength between the pins and the board, and the pins are attached to the film board and connected to the wiring pattern at the same time. In addition, a metal ring is formed coaxially with the through hole on the opposite surface of the wiring pattern formed on one surface of the film substrate, and when these are sandwiched between the stepped part and the head of the pin, the film substrate is connected to the metal ring and the wiring. It is reinforced by being held between the pins and the pattern, and improves the degree of bonding between the pins and the substrate when the pins are inserted and fixed in an upright position. Further improve reliability.

(実施例) 以下、本発明の実施例について添付の図面を参
照して説明する。
(Example) Hereinafter, an example of the present invention will be described with reference to the accompanying drawings.

図は本発明に係るピングリツドアレイの一実施
例を示し、1はポリイミド樹脂、エポキシ樹脂な
どのプラスチツク材料からなるフイルム基板、2
は良導電性金属材料からなる段付きピン、3は銅
又はアルミニウムなど良熱伝導性金属材料からな
る放熱板、4はフイルム基板と、ピンと放熱板と
を一体に封じ込める封止部で、ポリフエニレンサ
ルフアイド、エポキシ樹脂などの耐熱性樹脂から
形成されている。
The figure shows an embodiment of a pin grid array according to the present invention, in which 1 is a film substrate made of a plastic material such as polyimide resin or epoxy resin;
3 is a stepped pin made of a metal material with good conductivity, 3 is a heat sink made of a metal material with good thermal conductivity such as copper or aluminum, and 4 is a sealing part that seals the film substrate, pin and heat sink together, and is made of polyphenylene. It is made of heat-resistant resin such as rensulfide and epoxy resin.

フイルム基板1は、その中央部に開口部5を有
し、その表面には、第3図に示すように、開口部
5の近傍から放射状に伸張した配線パターン6が
形成され、該配線パターン6及びフイルム基板1
を貫通して複数の貫通孔7が形成されている。フ
イルム基板1上の配線パターン6は、貫通孔7と
同軸にリング部6aが形成されていて、フイルム
基板1の配線パターン6と反対側の表面上には、
貫通孔7と同軸に、かつ配線パターン6のリング
部6aと同形状の金属リング8が形成されてい
る。
The film substrate 1 has an opening 5 in its center, and a wiring pattern 6 extending radially from the vicinity of the opening 5 is formed on its surface, as shown in FIG. and film substrate 1
A plurality of through holes 7 are formed through the. The wiring pattern 6 on the film substrate 1 has a ring portion 6a formed coaxially with the through hole 7, and on the surface of the film substrate 1 opposite to the wiring pattern 6,
A metal ring 8 is formed coaxially with the through hole 7 and having the same shape as the ring portion 6a of the wiring pattern 6.

段付きピン2は、一端側近傍に段部を形成する
大径部2aを有し、一端側をフイルム基板1の貫
通孔7に嵌入した後、その一端側をかしめて頭部
2bを形成させ、その頭部2bと大径部2aとの
間に金属リング8、フイルム基板1及び配線パタ
ーン6を挾持させることによりフイルム基板1に
固定されると共に、配線パターン6に電気的に接
続されている。
The stepped pin 2 has a large diameter portion 2a forming a step near one end, and after the one end is inserted into the through hole 7 of the film substrate 1, the one end is caulked to form a head 2b. , is fixed to the film substrate 1 by sandwiching the metal ring 8, the film substrate 1, and the wiring pattern 6 between the head 2b and the large diameter portion 2a, and is electrically connected to the wiring pattern 6. .

放熱板3はフイルム基板1の開口部5に面する
側に該開口部5とほぼ同面積の凹所9が形成され
る一方、周縁部3aに突起10が形成され、周縁
部3aをフイルム基板1及びピン2と耐熱性樹脂
で封入成形することによりフイルム基板1及びピ
ン2と一体化されている。なお、11はスタンド
オフで、ピングリツドアレイをピンソケツトやマ
ザー基板等に装着した際、マザー基板等との間に
一定の間隔をあけるためのもので、ピングリツド
アレイの4つの角部にそれぞれ封止部4と一体成
形されている。なお、スタンドオフ11はフイル
ム基板の角部に限らず任意の位置に形成すること
ができる。また、封止部4にはピン2の頭部2b
に達する穴12が形成されているが、この穴12
は封入成形時にピン2を押圧固定する可動ピン1
9により形成される。20は放熱板3と封止部4
との結合部から水分が侵入するのを防止するため
の防湿用保護皮膜である。
The heat dissipation plate 3 has a recess 9 having approximately the same area as the opening 5 on the side facing the opening 5 of the film substrate 1, and a protrusion 10 on the peripheral edge 3a. The film substrate 1 and the pins 2 are integrally formed by sealing and molding the film substrate 1 and the pins 2 with heat-resistant resin. In addition, 11 is a standoff, which is used to leave a certain distance between the pin grid array and the mother board when it is attached to a pin socket or mother board. Each of them is integrally molded with the sealing part 4. Note that the standoffs 11 can be formed not only at the corners of the film substrate but also at any arbitrary position. In addition, the sealing portion 4 includes the head 2b of the pin 2.
A hole 12 is formed that reaches this hole 12.
is the movable pin 1 that presses and fixes the pin 2 during encapsulation molding.
9. 20 is a heat sink 3 and a sealing part 4
This is a moisture-proof protective film that prevents moisture from entering through the joints.

前記構造のピングリツドアレイは次のようにし
て製造できる。即ち、フイルム基板1のベースフ
イルムの両面に銅箔を積層し、該銅箔の表面上に
フオトレジストを塗布して乾燥させ、一方の表面
に配線パターンを、反対側の表面に貫通孔7を形
成すべき位置に対応する金属リングをパターンを
それぞれ露光した後、公知方法によりエツチング
して配線パターン6と金属リング8とを形成す
る。次いで、フオトレジストを溶解、除去した
後、電気メツキ法により配線パターン6上にニツ
ケルメツキを下地として金メツキを積層し、さら
に貫通孔の形成及び所定寸法への穿設切断加工を
施すことにより製造できる。
The pin grid array having the above structure can be manufactured as follows. That is, copper foil is laminated on both sides of the base film of the film substrate 1, a photoresist is applied on the surface of the copper foil and dried, and a wiring pattern is formed on one surface and a through hole 7 is formed on the opposite surface. After each metal ring pattern corresponding to the position to be formed is exposed to light, it is etched by a known method to form the wiring pattern 6 and the metal ring 8. Next, after dissolving and removing the photoresist, gold plating is laminated on the wiring pattern 6 using nickel plating as a base layer by electroplating, and further, through-holes are formed and drilling and cutting to predetermined dimensions are performed. .

なお、この実施例では、銅箔をエツチングして
形成された配線パターンの上にニツケルメツキ及
び金メツキを積層しているが、必ずしもその必要
は無く、配線パターンを銀メツキその他の耐食
性、良導電性金属メツキで形成しても良い。
In this example, nickel plating and gold plating are laminated on the wiring pattern formed by etching the copper foil, but it is not necessary to do so, and the wiring pattern may be coated with silver plating or other corrosion-resistant and highly conductive materials. It may be formed by metal plating.

また、フイルム基板1の製造方法として次の方
法を採用しても良い。即ち、ベースフイルムにス
リツト加工を施し、脱脂、乾燥後、化学銅メツキ
の付着を容易にするためベースフイルムの両表面
に触媒ペーストを塗布し、乾燥させた後、スタン
ピング加工し、配線パターン6及び金属リング8
を形成すべき部位以外の部位にレジストインキを
スクリーン印刷してマスキングし、次いで化学銅
メツキ法により銅メツキを施すことにより金属リ
ング8と配線パターン6の下地を形成し、配線パ
ターン6の下地となる銅メツキ上に電気銅メツ
キ、電気銀メツキを積層して配線パターンを完成
させる方法である。この場合、配線パターン6の
表面とレジストインキ層の表面とを同一レベルに
形成できるので、表面に凹凸の無い平滑なフイル
ム基板とすることができ、封入成形時にバリが形
成されることが無い。
Furthermore, the following method may be adopted as a method for manufacturing the film substrate 1. That is, the base film is slitted, degreased, and dried. Catalyst paste is applied to both surfaces of the base film to facilitate attachment of chemical copper plating. After drying, stamping is performed to form wiring patterns 6 and metal ring 8
The base of the metal ring 8 and the wiring pattern 6 is formed by screen printing resist ink to mask the parts other than the parts where the wiring pattern 6 is to be formed, and then applying copper plating using a chemical copper plating method. In this method, the wiring pattern is completed by laminating electrolytic copper plating and electrolytic silver plating on top of the copper plating. In this case, since the surface of the wiring pattern 6 and the surface of the resist ink layer can be formed on the same level, a smooth film substrate with no unevenness on the surface can be obtained, and no burrs are formed during encapsulation molding.

前記フイルム基板1にピンを取り付けるには、
予め用意した段付きのピン2をフイルム基板1の
貫通孔7にピン2が嵌入し、ピン2の頭部2bと
なる端部を振動あるいはハンマーリングによりか
しめれば良い。これにより、ピン2の頭部2bと
大径部2aとの間に金属リング8、フイルム基板
1及び配線パターン6が挾持させ、ピン2がフイ
ルム基板1に固定されると共に、配線パターン6
に電気的に接続される。
To attach pins to the film substrate 1,
A stepped pin 2 prepared in advance may be inserted into the through hole 7 of the film substrate 1, and the end portion of the pin 2 that will become the head 2b may be caulked by vibration or hammering. As a result, the metal ring 8, the film substrate 1, and the wiring pattern 6 are sandwiched between the head 2b and the large diameter portion 2a of the pin 2, and the pin 2 is fixed to the film substrate 1, and the wiring pattern 6
electrically connected to.

その後、第4図に示すように、下型15のキヤ
ビテイ17内に配置し、フイルム基板1の開口部
を覆うように放熱板3をセツトし、上型18を降
下させて型閉めし、耐熱性樹脂をキヤビテイ17
に射出して封入成形し、次いで、放熱板3が露出
している側の表面にエポキシ系あるいはポリイミ
ド系樹脂をコーテイングすることにより、第1図
に示す構造のピングリツドアレイを製造できる。
Thereafter, as shown in FIG. 4, the lower mold 15 is placed in the cavity 17, the heat sink 3 is set so as to cover the opening of the film substrate 1, the upper mold 18 is lowered to close the mold, and the heat resistant Cavity resin 17
A pin grid array having the structure shown in FIG. 1 can be manufactured by injecting and encapsulating the resin, and then coating the exposed surface of the heat sink 3 with epoxy or polyimide resin.

なお、ピンの形状としては、必ずしも段を一重
とする必要はなく、第5図に示すように、段部を
形成する大径部2aに少なくとも一つの環状溝2
cを形成することにより二以上の段部を設け、隣
合う二つの段部間の空間、即ち、環状溝2cに樹
脂がまわり込むようにし、ピン2と樹脂封止部4
との結合強度及びピンの引抜力を向上させるよう
にしてもよい。
Note that the shape of the pin does not necessarily have to be a single step, and as shown in FIG.
c, two or more step portions are provided, and the resin wraps around the space between two adjacent step portions, that is, the annular groove 2c, and the pin 2 and the resin sealing portion 4 are
The bonding strength with the pin and the pulling force of the pin may be improved.

(発明の効果) 以上の説明から明らかなように、本発明によれ
ば、プラスチツクフイルム基板をその表面に形成
された配線パターンと共に段付きピンの段部と頭
部とで挾持するようにしたので、配線パターンが
プラスチツクフイルムを補強する役割を果たし、
プラスチツクフイルム基板に変形を生じさせるこ
となくピンを強固に固定することができ、基板と
ピンとの結合強度を向上させ、ピングリツドアレ
イの信頼性を向上させることができる。
(Effects of the Invention) As is clear from the above description, according to the present invention, the plastic film substrate is held between the stepped portion and the head of the stepped pin together with the wiring pattern formed on its surface. , the wiring pattern plays the role of reinforcing the plastic film,
The pins can be firmly fixed without deforming the plastic film substrate, improving the bonding strength between the substrate and the pins, and improving the reliability of the pin grid array.

また、基板の配線パターンと反対側に金属リン
グを形成し、金属リングと配線パターンとを介在
させて基板にピンを固定するようにすると、金属
リングと配線パターンとが基板を補強する形とな
り、ピンをかしめる際にフイルム基板の変形が防
止され、挾持不能となる事態が発生することが
く、ピンと基板との結合強度を一段と向上させる
ことができる。このため、薄肉のプラスチツクフ
イルム基板であつてもピン及び放熱板と一体に封
入成形でき、ピングリツドアレイの薄型化及び低
コスト化を図ることができ、しかも50μm程度の
高寸法精度で信頼性の高いピングリツドアレイを
製造できるという優れた効果が得られる。
Furthermore, if a metal ring is formed on the opposite side of the board from the wiring pattern, and the pin is fixed to the board with the metal ring and the wiring pattern interposed, the metal ring and the wiring pattern will reinforce the board. Deformation of the film substrate is prevented when the pins are caulked, a situation in which the film substrate cannot be held is prevented from occurring, and the bonding strength between the pins and the substrate can be further improved. Therefore, even if it is a thin plastic film substrate, it can be integrally molded with pins and a heat sink, making it possible to make the pin grid array thinner and lower in cost.Moreover, it has high dimensional accuracy of about 50 μm and is reliable. An excellent effect can be obtained in that a pin grid array with a high pin-grid array can be manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るピングリツドアレイの断
面図、第2図はその部分拡大断面図、第3図は第
1図のピングリツドアレイの製造に使用するフイ
ルム基板の平面図、第4図は第1図のピングリツ
ドアレイの製造過程における封入成形時の金型の
要部断面図、第5図は本発明の変形例を示すピン
グリツドアレイの要部断面図である。 1……フイルム基板、2……ピン、2a……大
径部、2c……環状溝、3……放熱板、3a……
放熱板の周縁部、4……樹脂封止部、5……開口
部、6……配線パターン、7……貫通孔、8……
金属リング、10……突起。
1 is a sectional view of a pin grid array according to the present invention, FIG. 2 is a partially enlarged sectional view thereof, and FIG. 3 is a plan view of a film substrate used for manufacturing the pin grid array of FIG. FIG. 4 is a sectional view of a main part of a mold during encapsulation molding in the manufacturing process of the pin grid array shown in FIG. 1, and FIG. 5 is a sectional view of a main part of a pin grid array showing a modification of the present invention. DESCRIPTION OF SYMBOLS 1... Film substrate, 2... Pin, 2a... Large diameter part, 2c... Annular groove, 3... Heat sink, 3a...
Peripheral part of heat sink, 4... Resin sealing part, 5... Opening, 6... Wiring pattern, 7... Through hole, 8...
Metal ring, 10...protrusion.

Claims (1)

【特許請求の範囲】 1 表面に配線パターンを形成されたプラスチツ
クフイルムからなる基板と、該基板の配線パター
ンを貫通する各貫通孔に挿入固定され前記配線パ
ターンに接続された複数のピンと、前記基板と該
基板に挿入固定されたピンの挿入側とを封入一体
化する樹脂封止部を備え、前記ピンが前記貫通孔
への挿入端側に段部を有し、その段部と挿入端側
に形成された頭部とで前記基板と配線パターンを
挾持してなることを特徴とするピングリツドアレ
イ。 2 前記基板がその配線パターンと反対側の表面
上に貫通孔と同軸に形成された金属リングを有
し、該金属リングと前記基板及び配線パターンと
を前記ピンの段部と頭部とで挾持させてなる特許
請求の範囲第1項記載のピングリツドアレイ。 3 前記ピンがその段部を形成する大径部に環状
溝を有し、該環状溝を含む段部が樹脂封止部に封
入されている特許請求の範囲第1項又は第2項記
載のピングリツドアレイ。
[Scope of Claims] 1. A substrate made of plastic film with a wiring pattern formed on its surface, a plurality of pins inserted and fixed into through holes penetrating the wiring pattern of the substrate and connected to the wiring pattern, and the substrate. and the insertion side of the pin inserted and fixed into the substrate, the pin has a stepped part on the insertion end side into the through hole, and the stepped part and the insertion end side are provided. 1. A pin grid array comprising: a head formed on a pin sandwiching the substrate and the wiring pattern; 2. The substrate has a metal ring formed coaxially with the through hole on the surface opposite to the wiring pattern, and the metal ring, the substrate and the wiring pattern are held between the stepped portion and the head of the pin. A pin grid array according to claim 1. 3. The pin according to claim 1 or 2, wherein the pin has an annular groove in a large diameter portion forming a stepped portion, and the stepped portion including the annular groove is sealed in a resin sealing portion. Pin grid array.
JP18090285A 1985-08-16 1985-08-16 Pin mounting structure of pin grid array Granted JPS6240754A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP18090285A JPS6240754A (en) 1985-08-16 1985-08-16 Pin mounting structure of pin grid array
DE8686108770T DE3675321D1 (en) 1985-08-16 1986-06-27 SEMICONDUCTOR ARRANGEMENT WITH PACK OF PIN PLUG TYPE.
EP86108770A EP0218796B1 (en) 1985-08-16 1986-06-27 Semiconductor device comprising a plug-in-type package
US06/880,832 US4823234A (en) 1985-08-16 1986-07-01 Semiconductor device and its manufacture
KR1019860006161A KR870002647A (en) 1985-08-16 1986-07-28 Semiconductor device and manufacturing method
CN198686105249A CN86105249A (en) 1985-08-16 1986-08-16 Semiconductor device and manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18090285A JPS6240754A (en) 1985-08-16 1985-08-16 Pin mounting structure of pin grid array

Publications (2)

Publication Number Publication Date
JPS6240754A JPS6240754A (en) 1987-02-21
JPH0553067B2 true JPH0553067B2 (en) 1993-08-09

Family

ID=16091304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18090285A Granted JPS6240754A (en) 1985-08-16 1985-08-16 Pin mounting structure of pin grid array

Country Status (1)

Country Link
JP (1) JPS6240754A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0787221B2 (en) * 1987-02-27 1995-09-20 イビデン株式会社 Semiconductor mounting board
JPH05183019A (en) * 1991-12-27 1993-07-23 Hitachi Ltd Semiconductor device and manufacture thereof
JP4860443B2 (en) * 2006-11-20 2012-01-25 パナソニック株式会社 Fluorescent lamp

Also Published As

Publication number Publication date
JPS6240754A (en) 1987-02-21

Similar Documents

Publication Publication Date Title
KR960003766B1 (en) Plastic pin grid array package
US7193329B2 (en) Semiconductor device
KR101297915B1 (en) Flexible circuit substrate for flip-chip-on-flex applications
EP1096567A2 (en) BGA package and method for fabricating the same
US8294253B2 (en) Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure
JPS6134963A (en) Integrated circuit chip carrier
JPH10261753A (en) Resin sealed type semiconductor device
JP2002026187A (en) Semiconductor package and manufacturing method therefor
EP0563264B1 (en) Leadless pad array chip carrier
KR20240017393A (en) Semiconductor device and manufacturing method thereof
US6379996B1 (en) Package for semiconductor chip having thin recess portion and thick plane portion
KR100271656B1 (en) Bga semiconductor package and fabrication method thereof
JPH09321173A (en) Semiconductor device package, semiconductor device and their manufacture
JPH09312355A (en) Semiconductor device and its manufacture
JP3656861B2 (en) Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
KR100251868B1 (en) Chip scale semiconductor package using flexible circuit board and manufacturing method thereof
JPH0553067B2 (en)
JPH0533535B2 (en)
JP3293202B2 (en) Semiconductor device and manufacturing method thereof
KR20010042682A (en) Semiconductor device and process for manufacturing the same
KR100708041B1 (en) semiconductor package and its manufacturing method
KR19980068016A (en) Ball Grid Array (BGA) Semiconductor Package Using Flexible Circuit Board and Manufacturing Method Thereof
JP2700257B2 (en) Lead frame with wiring board and method of manufacturing the same
JPH07326690A (en) Package for semiconductor device and semiconductor device
JP2002076215A (en) Semiconductor device package and its manufacturing method