JPH0552971A - Time measuring device - Google Patents

Abstract

PURPOSE:To continuously measure the pulse width and cycle of a pulse signal. CONSTITUTION:An edge generating circuit 1 outputting an edge pulse signal on the basis of the rising/falling edge of a pulse signal, a counter 3 enabled by a measurement start signal and counting the pulse signal on the basis of a clock signal and disabled by a measurement stop signal to stop counting, a latch 5 temporarily holding the count value of the counter on the basis of the edge pulse signal of the edge generating circuit 1 and the clock signal and a memory 7 storing the count value held by the latch 5 are provided. The pulse width and cycle of the pulse signal are continuously measured on the basis of the count value stored in the memory 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time measuring device for measuring the pulse width and period of a pulse signal based on a clock signal. The present invention relates to a time measuring device that holds a counted value in a latch at each rising / falling edge of a pulse signal and continuously measures the pulse width and period of the pulse signal based on the counted value.

[0002]

2. Description of the Related Art In a conventional time measuring device, a counter counts the pulse width of a pulse signal based on a reference clock, temporarily stores the result in a memory, and then a CPU calculates the count value stored in this memory. Is calculated as the pulse width of the pulse signal.

FIG. 7 is a time chart showing the operation of a conventional time measuring apparatus, in which (a) is a pulse signal to be measured S0,
(C) is the reference clock signal CLK input to the counter
0 and (f) are the Q output of the counter for counting the reference clock signal CLK0 and (j) the write signal WR. (1) The counter is enabled by the rise of the pulse signal S0 to be measured, and starts counting the reference clock signal CLK0 input to the clock terminal. (2) The counter becomes disabled when the pulse signal S0 to be measured falls, and outputs the value counted by the counter, in this case, the count "9", to the memory. (3) The counter holds the count value while the count value is written in the memory, and after the write signal is given to the memory and the count value is written, the count value is cleared by the reset signal.

[0004]

In such a conventional time measuring device, it takes time to write the data of the pulse width counted by the counter into the memory, and the period is continuously counted after counting the pulse width. Had the drawback that it could not be counted.

The present invention has been made in view of the above circumstances, and holds a count value obtained by continuously counting pulse signals by a counter based on a clock signal by a latch at each rising / falling edge of the pulse signal. The data held by the latch is stored in the memory, and an object thereof is to provide a time measuring device capable of continuously measuring the pulse width and period of the pulse signal under measurement. ..

[0006]

In order to achieve such an object, the present invention is a time measuring device for continuously measuring the rising and falling times of a pulse signal based on a clock signal, Rise of the pulse signal /
An edge generation circuit that outputs an edge pulse signal based on a falling edge, and an enable signal by a start signal for starting measurement, the pulse signal is counted by the clock signal, and a disable signal by a stop signal at the end of measurement. A counter that stops counting, a latch that temporarily holds the count value of the counter based on the edge pulse signal of the edge generation circuit and the clock signal, and a memory that stores the count value held by the latch.
An address counter for designating an address for storing the count value of the latch is provided in the memory, and the pulse width and the cycle of the pulse signal are continuously measured based on the count value stored in the memory. There is.

[0007]

Each component of the present invention operates as follows.
The edge generation circuit outputs the edge pulse signal generated based on the pulse signal under measurement to the timing generation circuit.
The counter is enabled by the enable signal from the timing generation circuit and counts the reference clock signal input from the time base. The latch uses the count value counted by the counter as the rising edge / pulse of the pulse signal under measurement.
Hold for each falling edge. The memory continuously stores the count value of the counter held by the latch. The address counter increments the address by the address clock signal output from the timing generation circuit and specifies the address in the memory.

[0008]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of the time measuring device of the present invention. In the figure, reference numeral 1 denotes an edge detection circuit, which generates an edge pulse signal S1 based on the rising / falling edge of the pulse signal S0 to be measured and outputs it to the timing generation circuit 2. Timing generation circuit 2
A start signal S2 and a stop signal S3 for instructing the start and end of the measurement are input, and a measurement enable signal S4 for instructing the start of the measurement based on the start signal S2 is activated in a synchronous counter. 3 and the buffer 6, and inactively output based on the stop signal S3.

The synchronous counter 3 receives the measurement enable signal S4 and becomes active, and the reference clock CLK0 input from the time base 4 to the clock terminal.
The counting of the reference clock CLK0 is stopped when the measurement enable signal S4 is switched to inactive and disabled. Reference numeral 5 is a latch for holding the data counted by the synchronous counter 3, which is an edge pulse signal S
Based on 1 and the reference clock CLK0, the timing generation circuit 2 holds the count value data by the latch signal S5 output to the clock terminal. That is, the count value of the synchronous counter 3 at the time of rising / falling of the pulse signal S0 is held.

The count value held in the latch 5 is input to the memory 7 via the buffer 6 and written via the buffer 8 to the address designated by the address counter 9 by the write signal S6 output from the timing generation circuit 2. .. The address designated by the address counter 9 in the memory 7 is incremented by the address clock signal S7 from the timing generator 2.

The write signal S6 and the address clock signal S7 are generated based on the clock signal CLK1 input to the timing generation circuit 2.

After the count value data for each edge of the pulse signal S0 to be measured is stored in the memory 7 in this manner, CP
U10 specifies the address of the memory 7 to read the count value data, and calculates the pulse width and the period time by calculation.

FIG. 2 is a circuit diagram showing an extracted edge detection circuit 1 of the time measuring apparatus of the present invention. In the figure, 11 is an exclusive OR circuit, and the measured pulse signal S0 is directly input to one input terminal and the measured pulse signal S0 is input to the other input terminal of the delay line 1
It is designed to be input via 2. That is, the exclusive OR circuit 11 outputs the edge pulse signal S1 having the delay time width with respect to the rising edge of the measured pulse signal S0.

FIG. 3 is a circuit diagram showing an extracted timing generation circuit 2 of the time measuring device of the present invention. 2 in the figure
Reference numeral 1 is a D-type flip-flop to which a high level signal common to the D terminal and the clock terminal is applied. When the start signal S2 is input to the preset terminal (PR), the active measurement enable signal S4 is inverted. When the stop signal S3 is input to the synchronous counter, address counter, etc. from the terminal Q (hereinafter abbreviated as Q * terminal) and the stop signal S3 is input to the clear terminal (CLR), the measurement enable signal S4 is inverted and becomes inactive Become.

Reference numeral 22 denotes a D-type flip-flop having a high-level signal applied to the D-terminal. The edge pulse signal S1 is input to the clock terminal and the Q output is connected to the D-terminal of the D-type flip-flop 23. In the D-type flip-flop 23, the reference clock signal CLK0 is input to the clock terminal from the time base through the inverter 231 and D
The Q output of the flip-flop 21 is connected to the clear terminal, and the Q output is connected to the latch 5 as the latch signal S5.

Reference numeral 232 is a negative logic OR gate, one input terminal of which is connected to the Q * output of the D-type flip-flop 23, and the other input terminal of which is connected to the Q-output of the D-type flip-flop 21. ing. The output signal of the OR gate 232 is connected to the clear terminal of the D-type flip-flop 22.

Reference numeral 24 is a D-type flip-flop having a high-level signal applied to the D-terminal, the edge pulse signal S1 is input to the clock terminal, and the Q output is connected to the D-terminal of the D-type flip-flop 25. The clock signal CLK1 is input to the clock terminal of the D-type flip-flop 25, the Q output of the D-type flip-flop 21 is connected to the clear terminal, and the Q output is connected to one input terminal of the AND gate 251. ..

Reference numeral 26 is a D-type flip-flop in which the output of the AND gate 251 is connected to the D terminal.
The clock signal CLK1 is input to the clock terminal via 1, the Q output of the D-type flip-flop 21 is input to the clear terminal, the Q output is output to the D terminal of the D-type flip-flop 27, and the Q * output is written. The signal S6 is output to the memory 7. D-type flip-flop 27
The clock signal CLK1 is input to the clock terminal,
The Q output of the D-type flip-flop 21 is connected to the clear terminal, and the Q * output is connected to the address counter 8 as the address clock signal S7.

Numeral 241 is an OR gate of negative logic. One input terminal is connected to the Q * output of the D-type flip-flop 27, and the other input terminal is connected to the Q-output of the D-type flip-flop 21. ing. The output signal of the OR gate 241 is connected to the clear terminal of the D-type flip-flop 24.

FIG. 4 is a time chart showing the operation of the time measuring device of the present invention, in which (a) is the pulse signal to be measured S0,
(B) is an edge pulse signal S output from the edge detection circuit
1, (c) is the reference clock signal CLK0 generated by the time base, (d) is the start signal S2 input to the timing generation circuit, and (e) is the measurement enable signal S4 output by the timing generation circuit. , (F) is the Q output of the synchronous counter, (g) is the latch signal S5 output from the timing generation circuit, (h) is the Q output of the latch, (i) is the clock signal CLK1 input to the timing generation circuit, (J)
Is a write signal S6 output from the timing generation circuit,
(K) is the address clock signal S7 output from the timing generation circuit, (l) is the Q output of the address counter,
(M) is a stop signal S3 input to the timing generation circuit. The clock signal CLK1 does not have to be particularly synchronized with the reference clock signal CLK0 and the like, and an extremely short measured pulse period can be measured by using a clock signal that is as fast as possible according to the access time of the memory.

(10) The timing generation circuit 2 receives the measurement enable signal S4 based on the input start signal S2.
Is output to the synchronous counter 3, the latch 5, the buffers 6 and 8, and the address counter 9. (11) After the measurement enable signal S4 is input and the state becomes measurable, the edge circuit 1 changes the measured pulse signal S4.
The edge pulse signal S1 generated based on 0 is output to the timing generation circuit 2.

(12) The timing generation circuit 2 outputs to the latch 5 the edge pulse signal S1 and the latch signal S5 generated by the trailing edge of the reference clock signal CLK0 input from the time base 4. (13) When the latch signal S5 is input, the latch 5 holds the count value of the synchronous counter 3 at that time. In this case, the value of the count value "1" is held.

(14) On the other hand, the timing generation circuit 2 outputs the write signal S6 generated by the fall of the clock signal CLK1 input after the input of the edge pulse signal S1 to the memory 7, and the latch 5 holds it. The count value “1” is written in the memory 7.

(15) Further, the timing generation circuit 2 outputs the address clock signal S7 generated by the next rising edge of the clock signal CLK1 to the address counter 9.

(16) The address counter 9 increments the address of the memory 7 by the address clock signal S7 input to the clock terminal. (17) When the measured pulse signal S0 falls, the edge detection circuit 1 outputs the edge pulse signal S1 generated based on the measured pulse signal S0 to the timing generation circuit 2.

(18) The timing generation circuit 2 outputs to the latch 5 the latch signal S5 generated by the fall of the edge pulse signal S1 and subsequently the reference clock signal CLK0 input from the time base 4. (19) When the latch signal S5 is input, the latch 5 holds the count value of the synchronous counter 2 at that time. In this case, the value of the count value "16" is held. Below, (14) ~ (1
The process of 6) is repeated.

FIG. 5 shows a state in which the data of the pulse signal to be measured described in FIG. 4 is written in the memory.
FIG. 6 shows the CPU based on the data written in the memory.
FIG. 3 is an explanatory diagram for calculating the pulse width and period of the pulse signal under measurement by calculation.

In the memory, the data DT1 is written to the address "0000 _H ", that is, the count value "1" at the first rising, and the data is written to the address "0001 _H ".
DT2, that is, the count value "1" at the time of the next fall
6 "is written, and the count value" 28 "at the second rising is written in the address" 0002 _H ". In this way, the measured pulse signal S0 alternately output.
The count value at the time of rising / falling of is written in the memory.

The data DTn (n is an integer of 1 or more) written in the memory is subjected to an operation represented by the following equation by the CPU to obtain a pulse width and a cycle at arbitrary times. Note that t is the cycle of the reference clock signal CLK0, T
wi (i is an integer of 1 or more) is the pulse width, and Tci (i is 1
The integers above are the periods. Twi = (DT _{n + 1} -DT _n ) t Tci = (DT _{2n + 1} -DT _2n-1 ) t

[0030]

As described in detail above, in the time measuring apparatus of the present invention, the counter continuously counts the pulse signals based on the clock signal and outputs the count value at each rising / falling edge of the pulse signal. Since it is held in the latch and the time is measured based on the count value of the pulse signal, the rising / falling time of the pulse signal can be continuously measured. Therefore, even when the pulse width and period of the pulse signal continuously change, accurate measurement can be performed by following the change in the pulse signal.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a time measuring device of the present invention.

FIG. 2 is a circuit diagram showing an extracted edge detection circuit of the time measuring device of the present invention.

FIG. 3 is a circuit diagram showing an extracted timing generation circuit of the time measuring device of the present invention.

FIG. 4 is a time chart showing the operation of the time measuring device of the present invention.

5 is a diagram showing a state in which the data of the pulse signal under measurement described in FIG. 4 is written in a memory.

FIG. 6 is a CPU based on the data written in the memory
FIG. 3 is an explanatory diagram for calculating a pulse width and a cycle by calculation.

FIG. 7 is a time chart showing the operation of a conventional time measuring device.
It is

[Explanation of symbols]

 1 Edge Detection Circuit 2 Timing Generation Circuit 3 Synchronous Counter 4 Time Base 5 Latch 7 Memory 10 CPU

Claims (1)

[Claims] 1. A time measuring device for continuously measuring the rising and falling times of a pulse signal based on a clock signal, which outputs an edge pulse signal based on the rising / falling edge of the pulse signal. An edge generating circuit, a counter that is enabled by a start signal for measurement and counts the pulse signal by the clock signal, and a counter that is disabled by a stop signal at the end of measurement and stops counting, and a counter of this counter. A latch for temporarily holding a numerical value based on the edge pulse signal of the edge generation circuit and the clock signal, a memory for storing the count value held by the latch, and an address for storing the count value of the latch in this memory And an address counter that specifies, and based on the count value stored in the memory, A time measuring device characterized by continuously measuring a pulse width and a cycle of the pulse signal.