JPH0551936B2 - - Google Patents

Info

Publication number
JPH0551936B2
JPH0551936B2 JP63022176A JP2217688A JPH0551936B2 JP H0551936 B2 JPH0551936 B2 JP H0551936B2 JP 63022176 A JP63022176 A JP 63022176A JP 2217688 A JP2217688 A JP 2217688A JP H0551936 B2 JPH0551936 B2 JP H0551936B2
Authority
JP
Japan
Prior art keywords
cache
address
partition
plat
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63022176A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63257853A (ja
Inventor
Jeraado Burenza Jeemuzuu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS63257853A publication Critical patent/JPS63257853A/ja
Publication of JPH0551936B2 publication Critical patent/JPH0551936B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP63022176A 1987-04-03 1988-02-03 キヤツシユ・メモリ・システム Granted JPS63257853A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3413687A 1987-04-03 1987-04-03
US34136 1987-04-03

Publications (2)

Publication Number Publication Date
JPS63257853A JPS63257853A (ja) 1988-10-25
JPH0551936B2 true JPH0551936B2 (enrdf_load_stackoverflow) 1993-08-04

Family

ID=21874539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63022176A Granted JPS63257853A (ja) 1987-04-03 1988-02-03 キヤツシユ・メモリ・システム

Country Status (3)

Country Link
EP (1) EP0284751B1 (enrdf_load_stackoverflow)
JP (1) JPS63257853A (enrdf_load_stackoverflow)
DE (1) DE3873388T2 (enrdf_load_stackoverflow)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5553262B1 (en) * 1988-01-21 1999-07-06 Mitsubishi Electric Corp Memory apparatus and method capable of setting attribute of information to be cached
JPH0727492B2 (ja) * 1988-01-21 1995-03-29 三菱電機株式会社 緩衝記憶装置
EP0340901A3 (en) * 1988-03-23 1992-12-30 Du Pont Pixel Systems Limited Access system for dual port memory
CA1301367C (en) * 1988-03-24 1992-05-19 David James Ayers Pseudo set-associative memory cacheing arrangement
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JPH01280860A (ja) * 1988-05-06 1989-11-13 Hitachi Ltd マルチポートキヤツシユメモリを有するマルチプロセツサシステム
EP0477595A3 (en) * 1990-09-26 1992-11-19 Siemens Aktiengesellschaft Cache memory device with m bus connections
US5392414A (en) * 1992-06-30 1995-02-21 Sun Microsystems, Inc. Rapid data retrieval from data storage structures using prior access predictive annotations
GB2292822A (en) * 1994-08-31 1996-03-06 Hewlett Packard Co Partitioned cache memory
US5924117A (en) * 1996-12-16 1999-07-13 International Business Machines Corporation Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto
US6138209A (en) * 1997-09-05 2000-10-24 International Business Machines Corporation Data processing system and multi-way set associative cache utilizing class predict data structure and method thereof
US6745293B2 (en) 2000-08-21 2004-06-01 Texas Instruments Incorporated Level 2 smartcache architecture supporting simultaneous multiprocessor accesses
EP1215581A1 (en) * 2000-12-15 2002-06-19 Texas Instruments Incorporated Cache memory access system and method
JP3900025B2 (ja) 2002-06-24 2007-04-04 日本電気株式会社 共有キャッシュメモリのヒット判定制御方法及び共有キャッシュメモリのヒット判定制御方式
EP3258382B1 (en) 2016-06-14 2021-08-11 Arm Ltd A storage controller
CN113114684B (zh) * 2021-04-14 2022-08-16 浙江中拓合控科技有限公司 一种用于现场设备的信息传输系统、方法和装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619575A (en) * 1979-07-25 1981-02-24 Fujitsu Ltd Data processing system having hierarchy memory
US4371929A (en) * 1980-05-05 1983-02-01 Ibm Corporation Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory
US4484267A (en) * 1981-12-30 1984-11-20 International Business Machines Corporation Cache sharing control in a multiprocessor
JPS5948879A (ja) * 1982-09-10 1984-03-21 Hitachi Ltd 記憶制御方式
JPS59213084A (ja) * 1983-05-16 1984-12-01 Fujitsu Ltd バッファ記憶装置のアクセス制御方式

Also Published As

Publication number Publication date
DE3873388T2 (de) 1993-03-18
EP0284751A3 (en) 1989-05-31
EP0284751B1 (en) 1992-08-05
DE3873388D1 (de) 1992-09-10
JPS63257853A (ja) 1988-10-25
EP0284751A2 (en) 1988-10-05

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