JPH0548571A - Synchronization discriminating circuit for spectrum dispersion demodulator - Google Patents

Abstract

PURPOSE:To enable a synchronization discriminating circuit for spectrum dispersion demodulator to precisely discriminate synchronization regardless of the level of C/N of input signal by utilizing for synchronization discrimination the matched pulse output timing of the dispersion code catching circuit. CONSTITUTION:Input signal is treated for A/D conversion, and the correlation value between the dispersion code for modulating this input signal and the dispersion code for demodulating this input signal by dispersion code generator 15 is obtained by digital filter DMF3. Further, from the output of DMF3 a timing at which the correlation value is made to be the maximum by the maximum value detector 4 is detected, this timing is compared with the dispersion code generator initializing timing for the controller of dispersion code generator initialized by the maximum value detecting timing when catching the dispersion comparator 5 to obtain synchronization discriminating 7. As a result at a low C/N ratio of input signal, synchronization discriminating can be carried out precisely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization decision circuit for a spread spectrum demodulator, and more particularly to a spread spectrum system capable of reliably performing lock-on decision even at a low signal power to noise power ratio (hereinafter referred to as C / N). The present invention relates to a synchronization determination circuit of a demodulator.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a synchronization judgment circuit of a conventional spread spectrum demodulator. In the figure, 1 is an input terminal for inputting an input baseband signal modulated by a PN code, and 10 is an input terminal. PN that outputs a demodulation PN code having the same pseudo-random code sequence as the above-mentioned modulation PN code of the input baseband signal input from 1
Code generator, 6 is a PN for initializing the PN code generator 10.
This PN code generator is controlled by a spread code acquisition circuit 14 which is a code generator controller and uses a digital matched filter circuit (hereinafter referred to as DMF) or a charge coupled device (hereinafter referred to as CCD). The vessel 6 itself has also been initialized. Reference numeral 9 denotes a mixer for multiplying an input signal by a PN code, that is, despreading, 11 a low-pass filter (hereinafter referred to as LPF) for integrating (adding) the output of the mixer 9, and 12 a correlation between the input signal and the PN code. A squarer for obtaining the power of this signal by removing the influence of data modulation by squaring the amplitude of the signal after taking Reference numeral 5 is a comparator for comparing the signal without the influence of data modulation with the threshold value of the threshold value setting device 13, and reference numeral 7 is a synchronization judgment for outputting a signal in which the input signal and the PN code are in phase. Is the output.

Next, the operation will be described. The input baseband signal shown in FIG. 4 modulated by the PN code is input from the input terminal 1. This signal is then multiplied by the mixer 9 with the output of the PN code generator 10 for despreading. By this despreading, the data before spreading the spectrum by the PN code, that is, the baseband signal is obtained.

Utilizing the property of the PN code, C / of the input signal
When N is infinite, that is, when the phase of the input signal input to the mixer 9 and the phase of the PN code for demodulation match, the amplitude A of the output data of the mixer 9 has a peak value A as shown in FIG.
_It becomes ₀ , and when they do not match, it becomes "0". With this property, it is possible to determine whether the phases match or not by determining the amplitude A of the output data of the mixer 9. In reality, since the polarity changes due to the data modulation, the LPF 11 passes the amplitude, and then the squarer 12 causes the amplitude to change. The power of the signal is obtained by squaring A, the influence of the data modulation is removed, and the comparator 5 compares the value with the value of the threshold value setter 13 to determine the synchronization.

If the C / N is infinite, the set value of the threshold value setter 13 may be any value between "0" and the peak value A ₀ ² . However, since the C / N is not normally infinite, the output of the mixer 9 outputs a noise level corresponding to the C / N even when the phases do not match. Also when the phases match, the output data amplitude A becomes smaller than the peak value A ₀ due to the noise level of the input baseband signal corresponding to C / N. Therefore, it is necessary to change the set value of the threshold value setter 13 in accordance with the C / N of the input baseband signal in order to reliably perform the synchronization determination.

Next, the despreading of the synchronization determination circuit will be described in more detail. First, the configuration and operation of the DMF of the spread code acquisition circuit 14 will be described. Figure 5 above
FIG. 3 is a block circuit diagram showing a block configuration of an MF, in which a plurality of shift registers that sequentially shift an input baseband signal, that is, a digital value of a received PN code,
The local PN code for demodulation, which is the same as the PN code for modulation, output from each stage output of the plurality of shift registers and a local PN code generator (not shown) provided separately.
It is composed of a circuit for adding the correlation with the code. FIG. 6 is a diagram showing an output waveform of the DMF having an amplitude peak every cycle of the PN code (2 ⁿ −1 chips). In the figure, one chip represents one data length of the PN code. FIG. 7 is an explanatory diagram showing the phases of the input code and the local PN code input to the DMF. See also FIG.
FIG. 4 is an explanatory diagram showing a correlation value when the phases of the input code and the PN code generator match or when they do not match.

Next, the operation of this despreading will be described.
First, the local PN code generator generates a local PN code for demodulation that is the same as the PN code for modulation,
It is stored in the DMF shift register. This local P
The N code is fixed when it is first input.

The input baseband signal, that is, the digital value of the received PN code is sequentially shifted by a plurality of shift registers to obtain a correlation value with the fixed local PN code. At this time, a waveform having a peak amplitude (correlation value) is obtained for each PN code period (2 ⁿ −1 chips) as shown in FIG.

For example, as shown in FIG. 7, in the code length (cycle) of 2 ⁿ -1, n = 3, 2 ³ -1 = 7, that is, the cycle of the input baseband signal is "7", and the local PN code generator is used. If the phase difference from the local PN code output from the device is "3", then "3" is set as an initial value in the shift register of the PN code generator controller 6 at the same timing as the input code in order to equalize this phase difference. To do.

Based on the DMF output synchronized with the input baseband signal thus obtained, a PN code composed of n stages of shift registers and a feedback logic consisting of a modulo-2 adder Generator 10
The PN code generator controller 6 initializes the pseudo random code sequence output by That is, control is performed so as to output a PN code synchronized with the PN code for modulation.

Next, as shown in FIG. 8, the despreading performed by the mixer 9, that is, the data value of the code of the PN code generator 10 and the PN code of the input baseband signal is "1".
Is set to "+1" and "0" is set to "-1", and each is multiplied by the mixer 9. If the output of the PN code generator 10 and the input baseband signal are in phase, as a result, the output values of the mixer 9 are all "1", and the LPF1
When the output value of the mixer 9 is integrated (added) by 1, the output value (correlation value) of the LPF 11 becomes "7".

When the output of the PN code generator 10 and the input baseband signal are out of phase with each other, the output value of the LPF 11 is close to "0", and in the case of FIG.
The output value (correlation value) of is "-1".

[0013]

Since the synchronization determination circuit of the conventional spread spectrum demodulator is constructed as described above, it is necessary to determine the C / N of the input baseband signal, and the low C / N is required. However, there is a problem that it is difficult to optimize the threshold value for synchronization determination.

The present invention has been made to solve the above-mentioned problems, and the C / N of the input baseband signal is obtained.
It is an object of the present invention to obtain a synchronization determination circuit that does not need to determine, and can reliably determine even with a low C / N.

[0015]

A spread spectrum demodulator synchronization determination circuit according to the present invention spreads a demodulation spread code having a pseudo random code sequence identical to a modulation spread code in a spread code acquisition circuit. The correlation value between the spreading code for modulation of the received spread spectrum communication wave and the spreading code for demodulation generated by the code generator is calculated by the DMF or CCD.
, The maximum value of the correlation value output from the DMF or CCD is detected by the maximum value detector, the spreading code generator controller is initialized at the maximum value detection timing for detecting this maximum value, and then The spread code generator controller outputs the control signal by free running at a fixed timing. An initialization control signal output timing of the spread code generator controller and a maximum value detection timing of the maximum value detector are compared by a comparator to synchronize the spreading code for modulation and the spreading code for demodulation,
Asynchronous is determined.

[0016]

According to the present invention, the matched pulse output timing of the spread code acquisition circuit using DMF or CCD for obtaining the correlation value between the spread code for modulation of the received spread spectrum communication wave and the spread code for demodulation is set. Since it is used for the synchronization judgment, it is possible to eliminate the restrictions on the C / N and level of the input baseband signal.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit configuration diagram of a synchronization determination circuit of a spread spectrum demodulator according to an embodiment of the present invention. In the figure, 1 is an input terminal for inputting an input baseband signal, and 2 is a digital value for the input baseband signal. , A / D converter (hereinafter referred to as A / D converter), 3 is a DMF that detects the correlation value between the input signal and the spread code, and 4 is a maximum that detects the maximum value of the correlation value output of DMF3. A value detection circuit, 6 is a spread code generator controller initialized by the spread code phase timing obtained by the maximum value detection circuit 4, and 5 is a maximum value detection signal output from the maximum value detection circuit 4 and spread code generation. A comparator for judging the time relationship with the spread code phase timing output outputted by the controller controller 7, 7 is a synchronization judgment output outputted by the comparator 5, and 15 is the same decoding as the PN code for modulation. A local PN code generator for outputting a PN code of use. 2 (a)-(d)
FIG. 6 is a diagram showing an output waveform of the maximum value detection circuit 4.

Next, the operation will be described. The input baseband signal is converted into a digital signal by the A / D converter 2 and input to the DMF 3. The configuration and operation of the DMF 3 have been described in the conventional example, and will not be repeated here. In the DMF3, the correlation value between the input signal and the spread code is calculated. This correlation value is compared by the maximum value detection circuit 4 over one cycle of the spread code, and the maximum value is detected. However, if the C / N of the input signal is infinite, then FIG.
Although the waveform as shown in (a) is obtained, the C / N of the input signal is usually bad, so that the waveform has noise superimposed as shown in FIGS. 2 (b) and 2 (c). Therefore, the value after adding the correlation values in synchronization with one cycle of the spreading code as shown in FIG. 2 (d) is used, that is, the waveforms as shown in FIGS. 2 (b) and 2 (c) are obtained. Noise is removed by adding and averaging, and only the signal component is extracted. In this way, the error rate of maximum value detection by the maximum value detector 4 is reduced. This maximum value detection timing and the spreading code generator initial of the spreading code generator controller 6 initialized so as to be synchronized with the phase of the spreading code of the input signal in the spreading code acquisition process by the DMF 3 and the maximum value detection circuit 4 etc. The comparison timing is compared by the comparator 5. If these timings match, it is determined to be synchronous, and if they do not match, it is determined to be asynchronous.

The spreading code acquisition process will be described in more detail. The maximum value of the correlation values output from the maximum value detection circuit 4 is the highest probability value among the values considered to be in synchronization with the input code and the PN code. As shown in (b) and FIG. 2 (c), noise is superimposed, and noise close to the peak value may be erroneously detected as the maximum value although it is asynchronous. Therefore, it is necessary to confirm the maximum value detection timing of the maximum value detection circuit 4 again in the comparator 5.
Therefore, the maximum value detection timing of the maximum value detection circuit 4 is input to the spread code generator controller 6 as the spread code phase timing, and the spread code generator controller 6 is initialized. That is, as shown in FIG. 1, the output waveform of the maximum value detection circuit 4 and P
The initial peak value is aligned with the output waveform of the N code generator controller 6. The maximum value detection circuit 4 outputs a waveform having a cycle according to the measurement result, and the PN code generator controller 6 self-runs a waveform having a fixed cycle. Therefore, the initial peak values are aligned by the above initialization, and the phases a of the second and subsequent peak values are compared by the comparator 5, and the PN code for modulation of the input signal and the PN code for demodulation are synchronized or asynchronous. Can be determined.

It is necessary to widen the range of timing judgment in order to absorb the timing jitter. If the C / N of the input baseband signal is not infinite, the error rate of maximum value detection does not become "0", so that it is necessary to protect the synchronous / asynchronous judgment.

As described above, in the present embodiment, in the spread code acquisition circuit, the local PN code generator 15 generates the demodulation spread code having the same pseudo random code sequence as the modulation spread code, and the received spectrum is obtained. The correlation value between the spread communication wave and the demodulation spreading code is obtained by using the DMF 3, the maximum value of the correlation values output from the DMF 3 is detected by the maximum value detector 4, and the maximum value is detected to detect this maximum value. The spread code generator controller 6 is initialized at a timing, and thereafter, the spread code generator controller 6 outputs the control signal by free-running at a constant timing. The initialization control signal output timing of the spread code generator controller 6 and the maximum value detection timing of the maximum value detector 4 are compared by the comparator 5 to synchronize the spreading code for modulation and the spreading code for demodulation. , Asynchronous determination is performed, so that the circuit is simplified, and highly accurate synchronization determination can be obtained even when the input baseband signal has a low C / N and level.

In the above embodiment, the DMF for outputting the correlation value is used.
Although a case has been described as an example where the synchronization determination of the spread spectrum demodulator using 3 is performed, a CCD may be used for the above correlation value output, and the same effect as that of the above embodiment can be obtained.

Hereinafter, such another embodiment will be described with reference to the drawings. FIG. 2 is a block circuit configuration diagram of a synchronization determination circuit of a spread spectrum demodulator according to another embodiment of the present invention. In the figure, 8 indicates a CCD.

Next, the operation will be described. In the above embodiment, the DMF 3 obtains the correlation value between the digital value of the input baseband code and the digital value of the local PN code, but in the case of the CCD 8, the input code and the local value are determined according to the amount of electric charge corresponding to each digital value. The correlation value with the PN code is obtained. Therefore, in this case, it is not necessary to perform A / D conversion on the input baseband signal, but it is necessary to configure the maximum value detection circuit 4 with an analog circuit. The operations after the CCD 8 are the same as those in the above-described embodiment, and the description thereof will be omitted.

[0025]

As described above, according to the synchronization determination circuit of the spread spectrum demodulator according to the present invention, the synchronization determination of the delay locked loop is performed by the output pulse of the spread code generator controller and the output pulse of the maximum value detector. Since the circuit is configured to be obtained at the timing of, the circuit is simplified, and highly accurate synchronization determination can be obtained even when the input baseband signal has a low C / N and level.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a synchronization determination circuit of a spread spectrum demodulator according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the output of the maximum value detector that constitutes the synchronization determination circuit of the spread spectrum demodulator according to the embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a synchronization determination circuit of a spread spectrum demodulator according to another embodiment of the present invention.

FIG. 4 is a block circuit diagram showing a synchronization determination circuit of a conventional spread spectrum demodulator.

FIG. 5 is a block circuit diagram showing a block configuration of a DMF.

FIG. 6 is a waveform diagram showing a waveform of a matched pulse output from the DMF.

FIG. 7 is an explanatory diagram showing a phase difference between an input code and a local PN code in the DMF.

FIG. 8 is an explanatory diagram showing a correlation value when an input code and a PN code match or do not match in a synchronization determination circuit of a conventional spread spectrum demodulator.

[Description of Codes] 1 input baseband signal 2 A / D converter 3 DMF 4 maximum value detector 5 comparator 6 PN code generator controller 7 synchronization determination output 8 CCD 14 spreading code capturing circuit 14a spreading code capturing circuit 15 Local PN code generator

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[Procedure amendment]

[Submission date] January 9, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

Next, the operation will be described. The input baseband signal shown in FIG. 4 modulated by the PN code is input from the input terminal 1. This signal is then multiplied by the mixer 9 with the output of the PN code generator 10 for despreading. This despreading, before data to spread spectrum by the PN code is obtained.

Claims (3)

[Claims] 1. A synchronization determination circuit of a spread spectrum demodulator for performing synchronization determination for demodulating a received spread spectrum communication wave modulated by a modulation spreading code, the pseudo random code being the same as the modulation spreading code. Spreading code generating means for generating a spreading code for demodulation having a sequence,
Spreading code capturing means including correlation means for obtaining a correlation value between the received spread spectrum communication wave and the spreading code for demodulation, and a maximum value detecting means for detecting a maximum value of the output of the correlation means, and the predetermined code Initialized by the detection timing of the maximum value,
After that, the control means that outputs a control signal at a constant timing is compared with the timing of the control signal output from the control means after the initialization and the timing of the maximum value detection signal output from the maximum value detection means. Synchronization determining circuit for a spread spectrum demodulator. 2. The correlation means is a digital matched
2. A filter using a filter.
A synchronization determination circuit of the spread spectrum demodulator described. 3. The correlation means is charge coupled
The device according to claim 1, wherein the device is used.
A synchronization determination circuit of the spread spectrum demodulator described.