JPH033530A - Correlation demodulator - Google Patents

Abstract

PURPOSE:To attain correlation demodulation whose communication efficiency is not lowered by providing a controller which implements search and tracking processing in correlation demodulation according to an efficient algorithm. CONSTITUTION:A controller 14 reads registers 10-12 to detect a detection level being the output of reset integration devices 7-9 sequentially, stores the content into a memory, retards the clock phase of a clock generator 13 by one tip and repeats the same operation. Then plural phases corresponding to larger reception levels having larger reception levels stored in the memory are selected to be candidates of obtained synchronization phases. Then the clock generator 13 is set to the phase of the selected candidate, and the reception level inputted and integrated is compared with a prescribed synchronization deciding level and when the reception level is smaller than the discrimination level, the similar comparison processing is repeated as to the next candidate phase and when larger, it is discriminated that the synchronization is complemented at the phase and the processing is transited to the tracking. Thus, the efficient correlation demodulation is always attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a correlation demodulation device. More specifically, the present invention relates to a novel configuration of a correlation demodulation device that performs synchronization acquisition in a communication device, particularly when receiving spread spectrum communication.

2. Description of the Related Art As spread spectrum communication, there is a direct sequence spread spectrum communication system in which the frequency spectrum of the transmission output is spread over a wide frequency range by multiplying the transmission data by a pseudo-random code sequence on the transmission side.

As a conventional technique for demodulating this direct sequence type spread spectrum signal, a correlator type correlation demodulator (for example, 5pread spectrum system) is used.
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6.30) is known.

FIG. 5 is a block diagram schematically showing the configuration of a correlation receiving device when implementing the correlator method.

One reception input receives a spread spectrum signal and is connected to one input terminal of correlation detectors 2.3 and 4, respectively. On the other hand, the pseudorandom code sequence output from the PN code generator 5 is input to the other input terminal of the correlation detector 2 in its phase. Further, the shift register 6 generates a phase-delayed signal and a phase-advanced signal of this pseudorandom code sequence, and these are input to the other input terminals of the correlation detectors 3 and 4, respectively.

The output of the correlation detector 2 is connected to a search/tracking control circuit 22 via a low-pass filter 17, and switches between search and tracking as described later. In addition, the outputs of the correlation detectors 3 and 4 are compared by a comparator 20 after passing through low-pass filters 18 and 19, and the comparison results are input to a search/tracking control circuit 22 via a loop filter 21 to perform tracking control. Let's do it.

The output of the search/tracking control circuit 22 controls the clock phase of the clock generator 13, thereby controlling the phase of the pseudorandom code sequence that is the output of the PN code generator 5 driven by this clock.

FIG. 7 is a diagram showing an example of the configuration of the PN code generator 5.

As shown in the figure, this PN code generator 5 is composed of an m-sequence (maximal 5 sequence) generation shift register 71 and an exclusive OR circuit 72, and a pseudo-random code is generated by a shift clock circuit 4. An m-sequence, which is one type of sequence, is generated.

One period of this signal is composed of 31 bit data as shown in FIG. 7, etc., and is repeatedly output.

The conventional correlator type correlation demodulation device configured as described above operates as follows.

In the spread spectrum communication system, on the transmitting side, the 8th
As shown in Figure (a), an accumulation of m-sequences and transmission data is sent out as a transmission output. On the other hand, on the receiving side, as shown in Figure 8 (
As shown in b), the m-sequence generated on the receiving side and the received input are subjected to correlation detection and then passed through a low-pass filter to perform demodulation.

FIG. 6 is a diagram showing the correlation value in demodulation with respect to the phase difference between the m-sequence on the transmitting side and the m-sequence on the receiving side.

As shown in the figure, when the phase difference is 0, the correlation value is 31, and when the phase difference is greater than ±1, the correlation value is -1. That is, in order to correctly demodulate the received signal, it is necessary to lock the phase of the m-sequence on the receiving side to the m-sequence on the transmitting side. Therefore, the operation of the search/tracking control circuit for performing phase locking will be explained below.

FIG. 2 is a flowchart illustrating the operation of the search/tracking control circuit in the circuit shown in FIG.

This circuit first performs a search process in an asynchronous state, performs correlation detection on the received input, and if the received output is equal to or higher than a certain correlation value (for example, 15), ends the search and moves on to the tracking process. On the other hand, if the received output is less than this, by controlling the clock generator 60, the phase of the m-sequence is delayed and a search is performed until synchronization is established. still,
The search always ends before the receiving m-sequence has a phase delay of one period (31 chips).

In tracking processing, signals obtained by interferometrically detecting received inputs based on m-sequences whose phase differs by [10 chips] or [-each chip] with respect to the reference m-system signal 11 are compared, and Determine whether the phase of the receiving side m-sequence is delayed or advanced.

If it is behind, the receiving m-sequence phase is advanced by controlling the clock generator, and if it is ahead, it is delayed. When there is no more reception input, the synchronization goes out, tracking ends, and the process returns to the search process.

Problems to be Solved by the Invention The conventional correlator-type correlation demodulation device described above generates a pseudo-random code sequence whose phase matches the pseudo-random code sequence of a received input signal, and performs correlation reception. That is,
A multiplier 52, a low-pass filter 57, a search/tracking control circuit 61, and a clock generator 60 perform a sequential search and capture operation in which the timing of generation by the PN code generator 5 is gradually changed to synchronize with the received input signal.
, a PN code generator 55 and a shift register 56.

However, when the S/N in the transmission path is poor, in order to avoid the influence of noise and ensure synchronization, the establishment of synchronization is determined after integrating the time correlation detection output value for a sufficiently long time for all clock phases to be searched. must be done. Particularly in packet communications and the like, the feedback of synchronization signals that are not valid as communication data becomes long. This has the disadvantage of reducing line usage efficiency and communication speed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide a new correlation demodulation device that can always perform efficient correlation demodulation regardless of the S/N ratio of the transmission path.

Means for Solving the Problems, that is, according to the present invention, a phase-variable clock generator that generates clock pulses, a pseudo-random code sequence based on the clock pulses generated by the clock generator, and a code A PN code generator that generates an interrupt request signal for each period of the sequence, and three types of pseudo-random code sequences of a reference phase, a delayed phase, and an advanced phase generated from the pseudo-random code sequences generated by the PN code generator. three detectors that each perform correlation detection on the received signal using the three detectors, and three reset integrators that integrate the outputs of the detectors over one period of the pseudorandom code sequence, respectively;
The controller includes three registers each holding an integral value output from the reset integrator, and a controller that performs search processing for synchronization acquisition in response to the interrupt request, and executes tracking processing after synchronization acquisition. is input, the clock phase of the clock generator is delayed one chip at a time until a phase delay of one cycle of the pseudo-random code series occurs, and the received level is sequentially detected by reading out the register for each phase and stored in the memory. After selecting as a candidate the reception level corresponding to the reception level with a large value among the reception levels stored in the memory, the reception level is integrated at the phase corresponding to the candidate, and this is determined as the given judgment level. There is provided a correlation demodulation device characterized in that it is configured to determine that synchronization has been captured when the time period exceeds 0, and to shift the operation to tracking processing.

Further, according to a preferred embodiment of the present invention, the synchronization acquisition search process includes a primary search performed over the phases of one period of the pseudorandom sequence, and a plurality of phases having the highest correlation as a result of the primary search. , can be advantageously performed by a secondary search performed by integrating the correlation values multiple times.

The conventional correlator type correlation demodulation device described above performs synchronization acquisition by sequential search, which slows down the processing and reduces communication efficiency, whereas the correlation demodulation device according to the present invention Since synchronization supplementation is performed by efficient search processing based on a specific algorithm, communication efficiency does not decrease due to a decrease in the speed of search processing.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but the following disclosure is only one embodiment of the present invention, and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 is a block diagram showing a configuration example of a correlation demodulation device according to the present invention.

A receiving input 1 receiving a spread spectrum signal is connected to one input terminal of correlation detectors 2.3 and 4, respectively. On the other hand, the pseudorandom code sequence output from the PN code generator 5 is input to the other input terminal of the correlation detector 2 in its phase. Further, the shift register 6 generates a phase-delayed signal and a phase-advanced signal of this pseudorandom code sequence, and these are input to the other input terminals of the correlation detectors 3 and 4, respectively.

The outputs of the correlation detectors 2.3.4 are respectively integrated by reset integrators 7.8.9 and then transferred to registers 10.11.12.
is maintained.

The pseudo-random code sequence generation timing generated by the PN code generator 5 is based on the clock pulses supplied from the clock generator 13. Further, a synchronization signal outputted from the PN code generator 5 for each period of the pseudorandom code series is sent to the register 10 and IL1 as a latch pulse.
2, and also as a reset pulse to the reset integrator 7.
8.9, furthermore, the controller 14 as an interrupt pulse.
, respectively. The controller 11 processes data in registers 10, 11, and 12 each time an interrupt occurs, as will be described later, and also controls the clock phase of the clock generator 13.

FIG. 3 is a flowchart showing the operation of the correlation demodulation circuit shown in FIG. 1, particularly the search process.

A search process is started by inputting an interrupt signal to the controller 14 based on the synchronization signal output from the PN code generator 5. The controller registers register 10.1
Reset integrator 7.8 by reading 1.12.
The detection level which is the output of 9 is sequentially detected and stored on the memory. Next, the same operation is repeated with the clock phase of the clock generator delayed by one chip. This operation is repeated until a phase delay of one cycle (here, 31 chips) of the m-series occurs. Here, from among the reception levels stored in the memory, a plurality of phases corresponding to reception levels with large values are selected and used as candidates for the synchronization phase to be sought.

Then set the clock generator to the phase of the selected candidate,
The received level is input and integrated, and the result is compared with a predetermined synchronization determination level. Such operations are performed for each candidate phase, and if the phase is smaller than a predetermined determination level, the same comparison process is repeated for the next candidate phase. If it is larger than the determination level, it is determined that synchronization has been achieved at this phase and the process is shifted to tracking.

Embodiment 2 FIG. 4 is a flowchart showing another embodiment of the correlation demodulation device according to the present invention.

In this implementation, it is assumed that test data is communicated in the initial state of data communication. In communication of this test data, a correlation value at the time of synchronization establishment is detected, and the synchronization determination level is set to, for example, 70% of this value. Communication line S
/ If the N is bad and the synchronization determination level is low, the synchronization period is lengthened and the search integration time is set to be long.

When correlation demodulation is performed using the search integration time and synchronization determination level set by the above operations, there is an advantage that good communication can be performed even in packet communication regardless of the S/N of the communication line.

As described in detail, the correlation demodulation device according to the present invention includes a controller that performs search and tracking processing in correlation demodulation according to an efficient algorithm, so that search processing in synchronization can be reliably executed in a short time. be done. Moreover, this preferable characteristic is ensured regardless of conditions such as the S/N ratio of the communication line.

Furthermore, the controller search and tracking processing can be performed periodically every cycle of the PN code generator, and can be performed by a controller for data link processing in communication, rather than a dedicated controller. Hardware can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a correlation demodulation device according to the present invention, and FIG. 2 is a flowchart explaining operations in search processing and tracking processing in a conventional correlator type correlation demodulation device. FIG. 3 is a flowchart illustrating operations in search processing and tracking processing in the correlation demodulation device shown in FIG. 1, and FIG. 4 illustrates operations in another embodiment of the correlation demodulation device according to the present invention. FIG. 5 is a block diagram showing the configuration of a conventional correlator type correlation demodulation device, and FIG. 6 is a graph showing the relationship between the phase difference of the m-sequence and the correlation value in correlation detection. , Fig. 7(a) and et al.)
8A and 8B are a block diagram showing the configuration of an m-sequence generator and a waveform diagram of an m-sequence waveform, respectively, and FIGS. FIG. 2 is a diagram showing the basic configuration of. [Main reference numbers] 1... Reception input, 2, 3. 4. Correlation detector, 5. PN code generator, 6. O shift register, ? , 8. 9...Reset integrator, 10, 11.
12...Register, 13...Clock generator, 14...Controller, 17, 18.19...Low pass filter, 20...Comparator, 21...Loop filter, 22・71・72・73・74・Search/ Tracking control circuit, m-series generation shift register, exclusive OR circuit, m-series output, shift clock input

Claims (1)

[Scope of Claims] A variable-phase clock generator that generates clock pulses; and a pseudo-random code sequence generated based on the clock pulses generated by the clock generator, and an interrupt request for each cycle of the code sequence. Correlation detection is performed on each received signal using a PN code generator that generates a signal, and three types of pseudo-random code sequences: a reference phase, a delayed phase, or an advanced phase generated from the pseudo-random code sequence generated by the PN code generator. three reset integrators that each integrate the output of the detector over one period of a pseudorandom code sequence; and three registers that each hold the integral value output from the reset integrator. , Performing a synchronization acquisition search process according to the interrupt request,
and a controller that executes tracking processing after synchronization acquisition, and when an interrupt signal is input, the controller delays the clock phase of the clock generator one chip at a time until a phase delay of one cycle of the pseudorandom code series occurs. The reception level is sequentially detected by reading out the register for each phase while storing the reception level in the memory, and among the reception levels stored in the memory, the one corresponding to the reception level having a large value is selected as a candidate. , is configured to integrate the received level at a phase corresponding to the candidate, and when this exceeds a given determination level, it is determined that synchronization has been supplemented, and the operation is shifted to tracking processing. correlation demodulator.