JPH0547934A - Manufacture of large scale integrated circuit - Google Patents
Manufacture of large scale integrated circuitInfo
- Publication number
- JPH0547934A JPH0547934A JP20510091A JP20510091A JPH0547934A JP H0547934 A JPH0547934 A JP H0547934A JP 20510091 A JP20510091 A JP 20510091A JP 20510091 A JP20510091 A JP 20510091A JP H0547934 A JPH0547934 A JP H0547934A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- connection
- wafer
- circuit block
- large scale
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、大規模集積回路(LSI)
の製造方法に関する。近年、LSIの集積度は増々大規
模になっており、動物の神経組織の動作を擬態したニュ
ーロ素子を多数集積した回路の様に、一枚のウェハ全体
を使用するものも開発されつつある。BACKGROUND OF THE INVENTION The present invention relates to a large scale integrated circuit (LSI).
Manufacturing method. In recent years, the degree of integration of LSIs has become larger and larger, and a circuit using a single wafer as a whole has been developed, such as a circuit in which a large number of neuro elements simulating the operation of animal nerve tissue are integrated.
【0002】本発明は、この様な程度までに集積度が進
んだ超大規模集積回路の製造に適した製造方法に関す
る。The present invention relates to a manufacturing method suitable for manufacturing an ultra-large scale integrated circuit whose degree of integration has advanced to such a degree.
【0003】[0003]
【従来の技術】従来では、ウェハ上に集積回路を形成し
た後に行なう機能試験において合格したもののみを使用
し、1個所でも欠陥があるために機能試験に合格しない
ものは不良品として取扱われていた。2. Description of the Related Art Conventionally, only those which have passed a functional test performed after forming an integrated circuit on a wafer are used, and those which do not pass the functional test due to a defect at one place are treated as defective products. It was
【0004】[0004]
【発明が解決しようとする課題】しかし、1枚のウェハ
全体を使用する回路の場合には、微細なごみ、キズ等に
よるウェハの部分的な欠陥であっても全体が不良品とな
るので、歩留りを一定のレベルにするためには半導体製
造プロセスに高度な信頼性を必要とし、コストアップの
要因となっていた。However, in the case of a circuit using one wafer as a whole, even a partial defect of the wafer due to fine dust, scratches, etc., will result in a defective product as a whole. In order to achieve a certain level, the semiconductor manufacturing process requires high reliability, which has been a factor of cost increase.
【0005】したがって本発明の目的は、ウェハに欠陥
があってもそれが一部に限定されていれば、使用が可能
な大規模集積回路の製造方法を提供することにある。Therefore, it is an object of the present invention to provide a method of manufacturing a large scale integrated circuit which can be used even if there are defects in the wafer and the defects are limited to a part thereof.
【0006】[0006]
【課題を解決するための手段】前述の目的を達成する本
発明の大規模集積回路の製造方法は、i)1枚の集積回
路形成用ウェハ上に、互いに同一の機能を有し同数の外
部と接続すべき接続点を具備する複数の集積回路ブロッ
クと、それぞれの回路ブロックの同一機能の接続点と共
通の外部接続端子との接続を形成し、ii)該集積回路ブ
ロックの動作の良否を判定し、iii)動作が良好と判定さ
れた1つの集積回路ブロック以外の集積回路ブロックに
ついて、前記接続点と前記外部接続端子との接続を解除
する各段階を具備することを特徴とするものである。The method of manufacturing a large scale integrated circuit according to the present invention which achieves the above-mentioned object includes: i) the same function and the same number of external devices on one integrated circuit forming wafer. And a plurality of integrated circuit blocks having connection points to be connected with each other, and a connection point of each circuit block having the same function and a common external connection terminal are formed, and ii) whether the operation of the integrated circuit block is good or bad. And iii) the integrated circuit blocks other than the one integrated circuit block determined to be good in operation, each step of releasing the connection between the connection point and the external connection terminal. is there.
【0007】[0007]
【作用】動作が良好な集積回路ブロックのみを生かし
て、他の回路ブロックの接続を切り離すことによりウェ
ハの一部に欠陥があっても使用可能となる。By using only the integrated circuit block that operates well and disconnecting the other circuit blocks, it becomes possible to use even if there is a defect in a part of the wafer.
【0008】[0008]
【実施例】図1は本発明の第1の実施例を説明するため
の図である。ウェハ10上には同一の機能を有する2つの
回路ブロック12−1,12−2が左右対称に形成されてい
る。2つの回路ブロックの中央に外部との接続のための
入出力バス14が設けられており、これにより、回路ブロ
ック12−1,12−2のそれぞれと配線用パッド16とが接
続される。1 is a diagram for explaining a first embodiment of the present invention. On the wafer 10, two circuit blocks 12-1 and 12-2 having the same function are formed symmetrically. An input / output bus 14 for connecting to the outside is provided in the center of the two circuit blocks, and thereby each of the circuit blocks 12-1 and 12-2 and the wiring pad 16 are connected.
【0009】機能試験の結果、回路ブロック12−2に×
印で示すように欠陥があり、そのために回路ブロック12
−2が動作不良と判定されたとき、回路ブロック12−2
の側の配線は×印で示すようにレーザですべてカットさ
れる。破線で表わされているものは接続用コネクタ18で
あり、それに設けられた配線用パッド20とウェハ10上の
配線用パッド16との間でワイヤボンディングが行なわれ
る。As a result of the function test, the circuit block 12-2 has an X mark.
There is a defect as indicated by the mark, which is why circuit block 12
-2 is determined to be defective, the circuit block 12-2
The wiring on the side of is cut with a laser as shown by the cross. What is represented by a broken line is a connector 18 for connection, and wire bonding is performed between the wiring pad 20 provided on the connector 18 and the wiring pad 16 on the wafer 10.
【0010】図2は図1の集積回路板に接続用コネクタ
18を取り付け、全体をモールド22,24で覆ったものを表
わしており、(a)欄は平面図、(b)欄は×−×断面
図である。図3は本発明の第2の実施例を表わす図であ
り、図4はその内部の機能を表わす概略的な回路図であ
る。図4を参照すると、回路ブロック12−1,12−2の
外部との接続線にはそれぞれ入出力ゲート30−1,30−
2が挿入されており、それぞれ共通の制御線32−1,33
−2で制御される。機能試験はいずれか1つの回路ブロ
ックについて制御線32へHレベルを与えて入出力ゲート
30を生かし、他はLレベルを与えてフローティング状態
にする。FIG. 2 shows a connector for connecting to the integrated circuit board of FIG.
18 is attached, and the whole is covered with molds 22 and 24. A column (a) is a plan view and a column (b) is a XX sectional view. FIG. 3 is a diagram showing a second embodiment of the present invention, and FIG. 4 is a schematic circuit diagram showing its internal function. Referring to FIG. 4, the input / output gates 30-1 and 30- are respectively connected to the connection lines of the circuit blocks 12-1 and 12-2 to the outside.
2 are inserted, and the common control lines 32-1 and 33 are respectively provided.
Controlled by -2. For the functional test, give H level to the control line 32 for any one circuit block and input / output gate
Make the most of 30 and give L level to others to make them floating.
【0011】試験の結果、動作が良好であった回路ブロ
ックについて、図4 に示すように制御線32に設けられた
プルアップ抵抗およびプルダウン抵抗のうちプルダウン
抵抗を切断してHレベルに保ち、他の回路ブロックにつ
いては、プルアップ抵抗を切断してLレベルに保つ。As for the circuit block which has been operated well as a result of the test, as shown in FIG. 4, the pull-down resistor of the pull-up resistor and the pull-down resistor provided on the control line 32 is cut off to keep it at the H level. For the circuit block of, the pull-up resistor is cut off and kept at the L level.
【0012】[0012]
【発明の効果】以上述べてきたように本発明によれば、
ウェハ全体を使用する形態の大規模集積回路において、
ウェハの一部に欠陥があっても使用が可能な大規模集積
回路の製造方法が提供される。As described above, according to the present invention,
In a large scale integrated circuit that uses the entire wafer,
Provided is a method for manufacturing a large scale integrated circuit which can be used even if a part of a wafer is defective.
【図1】本発明の第1の実施例を説明するための図であ
る。FIG. 1 is a diagram for explaining a first embodiment of the present invention.
【図2】接続用コネクタが取り付けられ、モールドが施
された集積回路を表わす図である。FIG. 2 is a diagram showing a molded integrated circuit to which a connector for connection is attached.
【図3】本発明の第2の実施例を説明するための図であ
る。FIG. 3 is a diagram for explaining a second embodiment of the present invention.
【図4】図3の集積回路板の内部機能を表わす概略回路
図である。4 is a schematic circuit diagram showing internal functions of the integrated circuit board of FIG.
10…ウェハ 12…回路ブロック 14…入出力バス 16,20 …配線用パッド 18…接続用コネクタ 10 ... Wafer 12 ... Circuit block 14 ... I / O bus 16, 20 ... Wiring pad 18 ... Connector for connection
Claims (3)
互いに同一の機能を有し同数の外部と接続すべき接続点
を具備する複数の集積回路ブロックと、それぞれの回路
ブロックの同一機能の接続点と共通の外部接続端子との
接続を形成し、 ii)該集積回路ブロックの動作の良否を判定し、 iii)動作が良好と判定された1つの集積回路ブロック以
外の集積回路ブロックについて、前記接続点と前記外部
接続端子との接続を切り離す各段階を具備することを特
徴とする大規模集積回路の製造方法。1. An i) one integrated circuit forming wafer,
Forming a connection between a plurality of integrated circuit blocks having the same function as each other and having the same number of connection points to be connected to the outside and a connection point having the same function of each circuit block and a common external connection terminal, ii. ) Determining whether the operation of the integrated circuit block is good or bad, and iii) performing steps for disconnecting the connection between the connection point and the external connection terminal for integrated circuit blocks other than the one integrated circuit block for which the operation is determined to be good. A method of manufacturing a large-scale integrated circuit, comprising:
記外部接続端子とを接続する配線を切断することにより
接続が切り離される請求項1記載の方法。2. The method according to claim 1, wherein in step iii), the connection is disconnected by cutting a wire connecting the connection point and the external connection terminal.
記外部接続端子との接続毎に該接続を断続する素子およ
び前記回路ブロック毎に該断続素子を同時に制御する制
御素子をさらに設け、 前記段階iii)において、該制御素子により接続を切り離
す請求項1記載の方法。3. In the step i), an element for connecting and disconnecting the connection point and the external connection terminal for each connection of the connection point and a control element for simultaneously controlling the connection and disconnection element for each of the circuit blocks are further provided. The method according to claim 1, wherein in step iii) the control element disconnects the connection.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20510091A JPH0547934A (en) | 1991-08-15 | 1991-08-15 | Manufacture of large scale integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20510091A JPH0547934A (en) | 1991-08-15 | 1991-08-15 | Manufacture of large scale integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0547934A true JPH0547934A (en) | 1993-02-26 |
Family
ID=16501421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20510091A Withdrawn JPH0547934A (en) | 1991-08-15 | 1991-08-15 | Manufacture of large scale integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0547934A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001332094A (en) * | 2000-05-22 | 2001-11-30 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit, its test method, and recording device and communication equipment having it |
US6730527B1 (en) | 2001-12-31 | 2004-05-04 | Hyperchip Inc. | Chip and defect tolerant method of mounting same to a substrate |
-
1991
- 1991-08-15 JP JP20510091A patent/JPH0547934A/en not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001332094A (en) * | 2000-05-22 | 2001-11-30 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit, its test method, and recording device and communication equipment having it |
US6730527B1 (en) | 2001-12-31 | 2004-05-04 | Hyperchip Inc. | Chip and defect tolerant method of mounting same to a substrate |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981112 |