JPH0547195A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device with small current consumption by detecting this when the potential of the word line containing a defective memory cell is raised from the grounded potential at the time of a standby and interrupting the electric connection of a word line with a word line selection driving circuit and simultaneously to provide the semiconductor storage device with a malfunction preventing function by adding the constitution restoring the potential of the word line to the grounded potential by a reset signal input. CONSTITUTION:A detecting/interrupting circuit 11 is provided so as to lie between the word line selection driving circuit 9 and the word line 5. By this detecting/interrupting circuit 11, when the word line 5 rising from the grounded voltage 0V at the time of the standby by the presence of an electric leaking route 10 generated to the memory cell 1 is detected, the connection of the word line 5 with other power source line, etc., is interrupted so that no leakage current flows and the useless increase of the current consumption is prevented. Further, to the word line 5 whose potential floats by induction, etc., from the external, the potential of the word line 5 is withdrawn to the grounded potential by inputting the reset signal to the detecting/interrupting circuit 11 and the malfunction of the constitution is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device, particularly to a dynamic MOS memory.

[0002]

2. Description of the Related Art In recent years, with the high integration of semiconductor memory devices, the structure of semiconductor memory devices has become finer and the insulating film has become thinner.

FIG. 5 is a circuit diagram of a conventional semiconductor memory device. 1 is a memory cell, 2 is a storage node, 3 is a cell plate, 4 is a capacitor, 5 is a word line,
6 is a transfer gate, 7 is a row address signal, 8 is a bit line, 9 is a word line selection drive circuit, and 10 is an electric leak path.

First, the structure and operation of this semiconductor memory device will be described with reference to FIG. A memory cell 1 which is a memory element portion of a semiconductor memory device includes a capacitor section 4 including a storage node 2 and a cell plate 3,
The word line 5 is composed of a transfer gate 6 composed of an NchMOS transistor which is its gate.

Writing / reading of data is performed by selectively driving the word line 5 by the row address signal 7, turning on the transfer gate 6 and taking charge / removal of electric charge with the bit line 8. Data storage is performed by keeping the transfer gate 6 in the OFF state and maintaining the charge in the capacitor section 4.

The potential of the word line 5 is the ground potential 0V in the standby state in which data is not written or read.
When the word line selection drive circuit 9 drives the word line 5 by the input of the row address signal 7, the potential of the word line 5 becomes the power supply potential of 5V or higher. In addition, the potential of the bit line 8 during standby is 2.5 V, which is half the power source potential.

Next, when an electric leak path 10 is generated between the word line 5 and the bit line 8 in the insulating layer between the word line 5 and the bit line 8 due to the mixture of conductive foreign matters, the word line 5 Potential rises above the ground potential, the transfer gate 6 is turned on, the charge in the capacitor 4 cannot be maintained, and data cannot be maintained. Therefore, the memory cell 1 becomes a defective memory cell. ..

This defective memory cell is replaced by a redundant memory
The semiconductor memory device can be repaired by substituting the cells. That is, by registering the address of the defective memory cell in the redundant selection circuit, the redundant memory cell is selected instead of selecting the word line including the defective memory cell.

[0009]

However, in the above configuration, the word line including the defective memory cell is
Even after the replacement with the redundant word line, the word line including the defective memory cell is connected to the word line selection drive circuit. Then, since the word line selection drive circuit operates so that the potential of this word line becomes the ground voltage, the word line is driven from the bit line having a potential half the power supply potential through the electric leakage path due to the conductive foreign substance. As described above, the current flows to the ground potential portion of the selective drive circuit, which in turn increases the standby current consumption of the semiconductor memory device.

[0010]

The present invention comprises a word line and
A circuit that includes a circuit that selectively drives the word line, a unit that detects the potential of the word line, and a unit that disconnects electrical connection between the word line and the circuit that selectively drives the word line. A characteristic semiconductor memory device.

The present invention also provides the above semiconductor memory device,
It has a circuit provided with means for periodically setting the word line to the ground potential.

[0012]

According to the present invention, when the potential of the word line including the defective memory cell rises above the ground potential during standby, the shutoff circuit detects the word line selection drive circuit and the word line. To break the electrical connection between the bit line and the electrical leakage path in the defective memory cell, and the generation of current through the word line,
It is possible to prevent an increase in standby current consumption.

Furthermore, by adding a configuration in which the potential of the word line including the defective memory cell is periodically returned to the ground potential, even though the defective memory cell is not included,
The word line potential rises above the ground potential by induction from the outside, so that it is possible to prevent an erroneous operation in which a word line that is not defective is cut off from the word line selection drive circuit.

[0014]

1 is a circuit configuration diagram of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 2 is an example of a circuit diagram of a detection cutoff circuit configured in FIG.

1 is a memory cell, 2 is a storage node, 3 is a cell plate, 4 is a capacitance, 5 is a word line,
6 is a transfer gate, 7 is a row address signal, 8 is a bit line, 9 is a word line selection drive circuit, 10 is an electric leakage path, 11 is a detection cutoff circuit, 12 is a word line potential detection section, and 13 is a cutoff section. , 14 and 22 are NchMOS transistors, 15 is a resistor, 16 is a power supply line, 17 is an output of the word line potential detecting unit 12, 18 is a ground line, 19 and 20 are inverters, and 21 is a NAND.

First, the structure and operation of the semiconductor memory device according to the first embodiment will be described with reference to FIGS.

A memory cell 1 which is a memory element portion of a semiconductor memory device includes a capacitor portion 4 composed of a storage node 2 and a cell plate 3, and an NchMOS transistor having a word line 5 as its gate electrode. And a transfer gate 6 composed of

A detection cutoff circuit 11 is formed between the word line selection drive circuit 9 and the word line 5.

As shown in FIG. 2, the detection cutoff circuit 11 is composed of a word line potential detection section 12 and a cutoff section 13.

The word line potential detecting section 12 includes an NchMOS transistor 14 having a lower threshold voltage than the transfer gate 6 in the memory cell 1 and a resistor 15 having a resistance value larger than the ON resistance of the NchMOS transistor 14. Composed. The source of the NchMOS transistor 14 is connected to the power supply line 16, the drain is connected to the ground line 18 via the resistor 15, and serves as the output 17 of the word line potential detection unit. The gate of the NchMOS transistor 14 is connected to the word line.

When the potential of the word line 5 is the ground voltage 0V, N
Since the chMOS transistor 14 is in the OFF state, the potential of the output 17 of the word line potential detector 12 is 0V. The potential of the word line 5 changes to the NchMOS transistor 14
When the threshold voltage is exceeded, NchMOS transistor 1
4 becomes the ON state, and the output 1 of the word line potential detection unit 12
The potential of 7 becomes the power source potential of 5V.

The cutoff unit 13 includes inverters 19 and 20.
, NAND21, and NchMOS transistor 22
Composed of and. The input of the inverter 19 is the output 17 of the word line potential detector, and the input of the NAND 21 is the output of this inverter 19 and the output 9a of the word line selection drive circuit 9. Then, the output of the NAND 21 is input to the gate of the NchMOS transistor 22 via the inverter 20. The source of the NchMOS transistor 22 is the output 9a of the word line selection drive circuit 9, and the drain is the word line 5.

The output 9a of the word line selection drive circuit 9 is at the ground potential 0V in the standby state in which data is not written or read. In this standby state, when the potential of the word line is higher than the ground potential 0V, that is, when the output 17 of the word line potential detector 12 is 5V, the NchMOS transistor 22 is turned off, and the word line 5 and the word line selection drive circuit. 9 is cut off. In the standby state, when the potential of the word line is the ground potential, that is, when the output 17 of the word line potential detection unit 12 is 0V, the NchMOS transistor 22 is in the ON state, and the word line 5 and the word line selection drive circuit. 9 is connected.

Next, during the data write / read operation, the output 9a of the word line selection drive circuit 9 is at the power supply potential of 5V or higher. In this operation, the output of the NAND 21 is 0V regardless of the potential of the output 17 of the word line potential detection unit 12, and NchMO
The S transistor 22 is turned on to connect the word line 5 and the word line selection drive circuit 9.

With the configuration and operation of the detection / cutoff circuit 11 described above, in a normal memory cell, the potential of the word line 5 in the standby state is 0V, so that the word line selection drive circuit 9 and the word line 5 are always connected. Is connected. Then, for writing / reading of data, the word line 5 is selectively driven by the word line selection drive circuit 9 by the row address signal 7, the transfer gate 6 is turned on, and charge is taken in and out from the bit line 8. It will be executed. Data is stored by keeping the charge in the capacitor 4 by turning off the transfer gate 6.

Next, when an electric leak path 10 is generated between the word line 5 and the bit line 8 in the insulating layer between the word line 5 and the bit line 8 due to the mixture of conductive foreign substances, the bit line 8 Since the potential of is 2.5V, which is half the power supply potential of 5V,
The potential of the word line 5 is pulled to the potential of the bit line 8 and rises above the ground potential, and in the detection cutoff circuit 11, the connection between the word line selection drive circuit 9 and the word line 5 is cut off during standby, No leak current is generated from the bit line 8 through the electric leak path 10.

As described above, according to the first embodiment, when the electric leak path is generated between the bit line and the word line, the word line potential in the standby state is pulled to the potential of the bit line. By detecting the rise and cutting off this word line from the word line drive circuit, it is possible to prevent the generation of useless current.

FIG. 3 is a circuit configuration diagram of a semiconductor memory device according to the second embodiment of the present invention, and FIG. 4 is an example of a circuit diagram of the detection cutoff circuit configured in FIG.

Reference numeral 23 is a reset unit, 24 is a periodic reset signal, and 25 is an NchMOS transistor.

First, the structure and operation of the semiconductor memory device according to the second embodiment will be described with reference to FIGS. 3 and 4.

A memory cell 1 which is a memory element portion of a semiconductor memory device includes a capacitor portion 4 composed of a storage node 2 and a cell plate 3, and an NchMOS transistor having a word line 5 as its gate electrode. And a transfer gate 6 composed of

A detection interruption circuit 11 is formed between the word line selection drive circuit 9 and the word line 5.

As shown in FIG. 4, the detection cutoff circuit 11 is composed of a word line potential detection section 12 and a cutoff section 13.

The word line potential detector 12 includes an NchMOS transistor 14 having a lower threshold voltage than the transfer gate 6 in the memory cell 1 and a resistor 1 having a resistance value larger than the ON resistance of the NchMOS transistor 14.
5 and. The source of the NchMOS transistor 14 is connected to the power supply line 16, the drain is connected to the ground line 18 via the resistor 15, and serves as the output 17 of the word line potential detection unit. The gate of the NchMOS transistor 14 is connected to the word line.

When the potential of the word line 5 is the ground voltage 0V, N
Since the chMOS transistor 14 is in the OFF state, the potential of the output 17 of the word line potential detector 12 is 0V. The potential of the word line 5 changes to the NchMOS transistor 14
When the threshold voltage is exceeded, NchMOS transistor 1
4 becomes the ON state, and the output 1 of the word line potential detection unit 12
The potential of 7 becomes the power source potential of 5V.

The cutoff unit 13 includes inverters 19 and 20.
, NAND21, and NchMOS transistor 22
Composed of and. The input of the inverter 19 is the output 17 of the word line potential detector, and the input of the NAND 21 is the output of this inverter 19 and the output 9a of the word line selection drive circuit 9. Then, the output of the NAND 21 is input to the gate of the NchMOS transistor 22 via the inverter 20. The source of the NchMOS transistor 22 is the output 9a of the word line selection drive circuit 9, and the drain is the word line 5.

The output 9a of the word line selection drive circuit 9 is at the ground potential 0V in the standby state in which data is not written or read. In this standby state, when the potential of the word line is higher than the ground potential 0, that is, the word line potential detection unit 1
When the output 17 of 2 is 5V, the NchMOS transistor 22 is turned off, and the word line 5 and the word line selection drive circuit 9 are cut off. In the standby state, when the potential of the word line is the ground potential, that is, when the output 17 of the word line potential detection unit 12 is 0V, the NchMOS transistor 22 is in the ON state, and the word line 5 and the word line selection drive circuit. 9 is connected.

Next, during the data write / read operation, the output 9a of the word line selection drive circuit 9 is at the power supply potential of 5 V or higher. In this operation, the output of the NAND 21 is 0V regardless of the potential of the output 17 of the word line potential detection unit 12, and NchMO
The S transistor 22 is turned on to connect the word line 5 and the word line selection drive circuit 9.

The reset section 23 is composed of an NchMOS transistor 25 having a source connected to the ground line 18 and a drain connected to the word line 5. By inputting the reset signal 24 to the gate of the NchMOS transistor 24, the potential of the word line 5 becomes the ground potential.

With the configuration and operation of the detection cutoff circuit 11 described above, in a normal memory cell, the potential of the word line 5 in the standby state is the ground potential 0 V, so that the word line selection drive circuit 9 and the word line are always connected. It is connected. Then, for writing / reading of data, the word line 5 is selectively driven by the word line selection drive circuit 9 by the row address signal 7, the transfer gate 6 is turned on, and charge is taken in and out from the bit line 8. It will be executed. Data is stored by keeping the charge in the capacitor 4 by turning off the transfer gate 6.

Further, although the word line 5 includes a normal memory cell, the reset signal 2 is applied to the word line 5 which is floated from the ground potential due to electric induction or the like.
By inputting 4 to the reset unit 23, the potential of the word line 5 can be pulled out to the ground potential.

Next, when an electric leakage path 10 is generated between the word line 5 and the bit line 8 in the insulating layer between the word line 5 and the bit line 8 due to the mixing of the conductive foreign substance, the bit line 8 is generated. Since the potential of is 2.5V, which is half the power supply potential of 5V,
The potential of the word line 5 is pulled to the potential of the bit line 8 and rises above the ground potential, and in the detection cutoff circuit 11, the connection between the word line selection drive circuit 9 and the word line 5 is cut off during standby, No leak current is generated from the bit line 8 through the electric leak path 10.

As described above, according to the second embodiment, when the electric leakage path is generated between the bit line and the word line, the word line potential in the standby state is pulled to the potential of the bit line. By detecting the rise and cutting off this word line from the word line drive circuit, it is possible to prevent the generation of useless current.

Further, by inputting the reset signal to set the word line to the ground potential, it is possible to prevent malfunction of the detection cutoff circuit due to floating of the word line potential due to induction or the like.

In the present embodiment, the detection cutoff circuit provided between the word line selection drive circuit and the word line is NchMO.
Although the circuit is configured by the S transistor, the NAND, the inverter, and the resistor, it may be configured by using another functional element having the same operation. Further, although the power supply potential is set to 5 V, it goes without saying that it may be another potential.

[0046]

As described above, according to the present invention, there is provided means for cutting off the word line including the defective memory cell having the electric leakage path between the word line and the bit line from the word line selection drive circuit. This can prevent an increase in current consumption during standby. Further, by inputting the reset signal to set the potential of the word line to the ground potential, it is possible to prevent the normal word line in which the potential is accidentally raised due to induction or the like from being erroneously recognized as the word line including the defective memory cell. Therefore, a stable semiconductor memory device can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the detection cutoff circuit configured in FIG.

FIG. 3 is a circuit configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a detection cutoff circuit configured in FIG.

FIG. 5 is a circuit configuration diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 1 Memory Cell 2 Storage Node 3 Cell Plate 4 Capacitance 5 Word Line 6 Transfer Gate 7 Row Address Signal 8 Bit Line 9 Word Line Selection Drive Circuit 10 Electrical Leakage Path 11 Detection and Cutoff Circuit 12 Word Line Potential Detection Section 13 Breaking unit 14, 21, 25 NchMOS transistor 15 Resistance 16 Power supply line 17 Output of word line potential detection unit 12 18 Ground line 19, 20 Inverter 22 NAND 23 Reset unit 24 Reset signal

Claims (2)

[Claims] 1. A word line, a circuit for selectively driving the word line, a means for detecting a potential of the word line, and an electrical connection between the word line and a circuit for selectively driving the word line are cut off. A semiconductor memory device having a circuit including: 2. The semiconductor memory device according to claim 1, further comprising a circuit including a unit that periodically sets the word line to a ground potential.