JPH0547193A - Logic circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction by a shift register even when a skew is generated to the clock inputs of respective D type flip-flops in the shift register of the D type flip-flop. CONSTITUTION:This logic circuit is constituted of input terminals 1, 2 and 3, a D latch circuit 4 latching a data at the rise of a clock, a selector circuit 5 and an output terminal 6. In the selector circuit, the data input D0 is outputted except when the select input A is '1' and tone select input B is '0', the data input D1 is outputted when the select input A is '1' and the select input B is '0'.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to logic circuits, and more particularly to D
The present invention relates to a clock skew absorbing circuit used between shift registers of a type flip-flop.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional D-type flip-flop shift register.

Conventionally, the shift register of the D-type flip-flop has to consider the skew that can be assumed in the clock input of each D-type flip-flop.

[0004]

The above-described conventional D-type flip-flop shift register has a drawback that the shift register malfunctions when the skew of the clock input of each D-type flip-flop cannot be defined. ..

An object of the present invention is to provide a logic circuit in a shift register of a D type flip-flop, which prevents malfunction of the shift register even if skew occurs in the clock input of each D type flip-flop.

[0006]

According to the present invention, in a selector circuit, the first data input is performed except when the first select input is a logical value "1" and the second select input is a logical value "0". Selective output is performed. When the first select input has a logical value "1" and the second select input has a logical value "0", a selector circuit that selects and outputs the second data input and D-latch circuit for latching data, consisting of 3 input terminals and 1 output terminal,
The signal of the first input terminal is used as the data input of the D latch circuit and the first data input of the selector circuit, and the signal of the second input terminal is used as the clock input of the D latch circuit and the first select input of the selector circuit. The signal of the third input terminal is connected to the second select input of the selector circuit, the output of the D latch circuit is connected to the second data input of the selector circuit, and the output of the selector circuit is connected to the output terminal. It is a logic circuit.

In the shift register of the D-type flip-flop, the data output of the D-type flip-flop of the previous stage is connected to the first input terminal of the logic circuit, and the clock input of the D-type flip-flop of the previous stage is connected to the first input terminal of the logic circuit. Two input terminals, the output of the above logic circuit is connected to the data input of the D-type flip-flop in the subsequent stage,
The clock input of the subsequent D-type flip-flop is connected to the third input terminal of the logic circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the present invention. 1, 2, 3
Is an input terminal and 6 is an output terminal. Input terminal 1 is D
The clock input of the latch circuit 4 and the data input D0 of the selector circuit 5 are connected, the input terminal 2 is connected to the clock input of the D latch circuit 4 and the select input A of the selector circuit 5, and the input terminal 3 is selected by the selector circuit 5. The input Q is connected to the input B, the output Q of the D latch circuit 4 is connected to the data input D1 of the selector circuit 5, and the output terminal 6 is connected to the output bar O of the selector circuit 5. The logical value of the data input D0 is output to the output bar O of the selector circuit 5 except when the select input A is the logical value "1" and the select input B is the logical value "0", and the select input A is the logical value "1". When the select input B is "0", the logical value of the data input D1 is output.

FIG. 2 shows an embodiment of a shift register of a D type flip-flop using the logic circuit of FIG. 1 of the present invention. Reference numeral 12 is the logic circuit of FIG. The data input terminal 7 is connected to the D input of the D type flip-flop 11, the clock input 8 is connected to the inputs of the buffers 9 and 10, and the output of the buffer 9 is the D type flip-flop 11.
Of the D type flip-flop 11 is connected to the data input D of the logic circuit 12, and the output of the buffer 10 is connected to the select signal B of the logic circuit 12 and the D type. It is connected to the clock input of the flip-flop 13, the output bar O of the logic circuit 12 is connected to the data input of the D-type flip-flop 13, and the output terminal 14 is connected to the Q output of the D-type flip-flop 13.

3 and 4 are explanatory diagrams of waveforms in the circuit of FIG.

In FIG. 3, the output propagation delay time of the buffer 9 is t1, and the output propagation delay time of the buffer 10 is t2.
Then, when t1 <t2, the output bar O of the logic circuit 12 when the output of the buffer 9 is the logical value “1” and the output of the buffer 10 is the logical value “0”, the D input of the logical circuit 12 is the logical circuit. When the latched signal is output at the rising edge of the select signal A of 12 and the output of the buffer 9 becomes the logical value "1" and the output of the buffer 10 becomes the logical value "1", the logic circuit 1
The output bar O of 2 outputs the input signal D1 of the data input terminal 7 because the D input of the logic circuit 12 is output as it is.
The data enters the D input of the D type flip-flop 13, the D type flip-flop 13 latches at the next rising edge of the buffer 10, and the data D1 is output to the output 14 to operate as a shift register. When t1 ≧ t2 in FIG. 4, the output bar O of the logic circuit 12 operates as a shift register because the D input of the logic circuit 12 is output as it is.

[0013]

As described above, by using the logic circuit of the present invention, the shift register of the D-type flip-flop can operate normally even when the skew of the clock input of each D-type flip-flop cannot be defined. Has the effect of working.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram of the present invention.

2 is an example of a shift register using the logic circuit diagram of FIG.

FIG. 3 is a signal waveform diagram of FIG.

FIG. 4 is a signal waveform diagram of FIG.

FIG. 5 is a conventional shift register circuit diagram.

6 is a signal waveform diagram of FIG.

[Explanation of symbols]

 1, 2 and 3 input terminals 4 D latch circuit 5 selector circuit 6 output terminal 7 data input terminal 8 clock input terminal 9 and 10 buffer 11 and 13 D type flip-flop 12 logic circuit 14 output terminal

Claims (1)

[Claims] 1. A selector circuit selects and outputs a first data input except when the first select input has a logical value "1" and the second select input has a logical value "0". A selector circuit that selects and outputs the second data input when one select input has a logical value "1" and a second select input has a logical value "0", and a D latch circuit that latches data at the rising edge of a clock, And a signal from the first input terminal to the data input of the D latch circuit and the first data input of the selector circuit, and a signal from the second input terminal to the D input. The clock input of the latch circuit and the first select input of the selector circuit, the signal of the third input terminal to the second select input of the selector circuit, the output of the D latch circuit to the second data input of the selector circuit, Selector circuit A logic circuit characterized in that an output is connected to each output terminal.