JPH054712B2 - - Google Patents

Info

Publication number
JPH054712B2
JPH054712B2 JP61011577A JP1157786A JPH054712B2 JP H054712 B2 JPH054712 B2 JP H054712B2 JP 61011577 A JP61011577 A JP 61011577A JP 1157786 A JP1157786 A JP 1157786A JP H054712 B2 JPH054712 B2 JP H054712B2
Authority
JP
Japan
Prior art keywords
unrolling
loop
program
operation sequence
vector operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61011577A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62169272A (ja
Inventor
Masaki Aoki
Morie Sagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61011577A priority Critical patent/JPS62169272A/ja
Publication of JPS62169272A publication Critical patent/JPS62169272A/ja
Publication of JPH054712B2 publication Critical patent/JPH054712B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Devices For Executing Special Programs (AREA)
JP61011577A 1986-01-22 1986-01-22 ベクトル演算列ル−プアンロ−リング処理方式 Granted JPS62169272A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61011577A JPS62169272A (ja) 1986-01-22 1986-01-22 ベクトル演算列ル−プアンロ−リング処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61011577A JPS62169272A (ja) 1986-01-22 1986-01-22 ベクトル演算列ル−プアンロ−リング処理方式

Publications (2)

Publication Number Publication Date
JPS62169272A JPS62169272A (ja) 1987-07-25
JPH054712B2 true JPH054712B2 (enExample) 1993-01-20

Family

ID=11781767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61011577A Granted JPS62169272A (ja) 1986-01-22 1986-01-22 ベクトル演算列ル−プアンロ−リング処理方式

Country Status (1)

Country Link
JP (1) JPS62169272A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03150636A (ja) * 1989-11-08 1991-06-27 Matsushita Electric Ind Co Ltd コンパイル方法
JP2718816B2 (ja) * 1990-10-19 1998-02-25 富士通株式会社 コンパイラ装置
JP2009070070A (ja) * 2007-09-12 2009-04-02 Nec Corp コンパイラ及びコンパイル方法

Also Published As

Publication number Publication date
JPS62169272A (ja) 1987-07-25

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees