JPH0546515A - Data transfer system - Google Patents

Abstract

PURPOSE:To equalize the burden of a microprocessor by holding the start of only a write request just for a prescribed time when the time point when a write request is produced is approximately coincident with the time point when the microprocessor receives the read request interruption of the received parallel data. CONSTITUTION:A transmission/reception adaptor 1 is provided with a data conversion pert 2 and a microprogram 3 which receives the read and write request interruptions form the part 2. When the adaptor 1 receives a read request interruption and starts the read of the pert 2, a read mode flag 4 is set up and at the same time a clock counter 5 starts to count the received clocks. When a write request is received, the state of the flag 4 and the output of the counter 5 are detected. When the former is kept in a read mode and the latter is a specific value respectively, the start of the write request interruption is held by a clock timer 6 only for a prescribed time so as to evade the coincidence of timing between the read and write request interruptions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system, and more particularly to serial-to-parallel conversion of received data of the same number of bits transmitted serially via a transmission line, and transmission parallel data. A data conversion unit having a function of performing parallel-serial conversion and then sending to a transmission line, and a parallel data read request interrupt and a transmission parallel data write request interrupt from the data conversion unit, respectively. The present invention relates to a data transfer system using a transmission / reception adapter provided with a microprogram for executing processing according to the above.

[0002]

2. Description of the Related Art Generally, as one of the data transfer methods for connecting data between a host computer and a terminal device, or connecting terminal devices with a communication line and performing data communication between them, there is a Duplex communication, that is, the data that the host computer or terminal device can simultaneously perform transmission and reception
Data transfer method is used.

The full-duplex communication is an efficient transfer system capable of sending data in both directions at all times. A 4-wire system is required as a transmission line, but a 2-wire system is required. Even in a line, it becomes possible by frequency-dividing the transmission band, and a transmission / reception adapter is used as an interface with the transmission line.

As shown in FIG. 5, this transmission / reception adapter comprises a communication LSI (data conversion section) 52, a microprogram 53, etc. The communication LSI 52 is sent via a transmission line. For example, a shift register 54 for converting 8-bit serial format character data (serial data) into parallel data, a shift register for converting parallel transmission data from the CPU 56 into serial data. 55 and an error correction unit (not shown).

Here, the serial data sent to the transmission / reception adapter 51 is converted into parallel data by the shift register 54 for each data (one character), but this conversion is completed. For each time, the communication LSI 52 issues a read request interrupt of the parallel data to the microprogram 53, and the shift register 55 causes the parallel parallel data for transmission of 8 bits, for example.
Each time the processing of converting the data into serial data and sending it out to the transmission line is completed, the communication LSI 52 causes the microprogram 53
In response to this, a write request interrupt to the shift register 55 of the next parallel data for transmission is generated, and the microprogram 53 receiving these interrupts starts respective interrupt processing.

[0006]

As described above, the microprogram issues a read request interrupt and a write request interrupt.
Although it is accepted from time to time, if the timings of both sides overlap (because it is not possible to execute both interrupts at the same time), either one of the interrupts will have to wait. If t ₁ is to be waited before the start of the writing process, the time (t ₁ + t ₂ ) is originally reserved for the writing process, and the actual processing time is t ₂ and the There was a problem that the load of the program became large.

Therefore, in the present invention, a communication LSI (data
The timing of the write request generation for the read request interrupt, which is exclusively in a passive position for the data conversion unit), is checked, and when the two are almost coincident, the activation of the write request interrupt for the microprogram is delayed by a predetermined time. Thus, it is an object of the present invention to make the timings of receiving a read request interrupt and a write request interrupt in the microprograms non-coincident so that the loads on the microprograms are equalized.

[0008]

The present invention is different from the case of a read request interrupt of parallel data after serial-parallel conversion, in which a communication LSI of the parallel data for transmission (data conversion unit) is provided. The timing of the write request interrupt to the transmission / reception adapter focuses on the point that the transmission / reception adapter can adjust it by itself. When the write request is generated, the microprogram issues a read request interrupt of the parallel data after reception. When the received time substantially coincides with the received time, the activation of the write request interrupt is suspended for a predetermined time.

FIG. 1 illustrates the principle of the present invention. In the figure, reference numeral 1 denotes a transmission / reception adapter, which comprises a microprogram, a data conversion unit, a clock counter, a clock timer and the like. Reference numeral 2 is a data conversion unit that converts, for example, 8-bit serial format character data (serial data) sent via a transmission line into parallel data,
A read request interrupt of the parallel data is generated in the microprogram, and transmission parallel data sent from the CPU is sent.
After converting the data into serial data and sending it to the transmission line, a write request for the next parallel data for transmission is issued. Reference numeral 3 denotes a microprogram, which processes the read request interrupt and the write request interrupt from the data conversion unit, and notifies the data conversion unit that parallel data for transmission is sent from the CPU. The process to do is done. Reference numeral 4 is a reading flag, which is set to, for example, "1" by the microprogram which has received the read request interrupt. Reference numeral 5 denotes a clock counter, which starts counting operation of the reception clock by a start signal issued by the microprogram which has received the read request interrupt. Reference numeral 6 denotes a clock timer, which determines the timing of generation of a write request in the data conversion unit and reception of a read request interrupt in the microprogram according to the hardware signals regarding the state of the reading flag and the output of the clock counter. It is set when it is detected that they are almost the same, and after that, the count operation is executed every time the received clock is received, and only the operation time of this timer is
The activation of the write request interrupt for the microprogram from the data conversion unit is suspended. It should be noted that instead of the clock timer, a timer having a normal time counting operation may be used. 7 is a transmission line, and generally,
8-bit serial format character data (serial data) is transmitted. Reference numeral 8 denotes a CPU, which performs data communication with other computers and terminal devices via a transmission / reception adapter and a transmission line.

The processing procedure for the generation of a write request is as shown in FIG. That is, it is determined whether or not a write request is generated. If "YES", the process proceeds to the next step, and if "NO", this determination is repeated. Detects whether the reading flag is on and displays "YES
If “NO”, proceed to the next step. If “NO”, proceed to step. Whether the output value of the clock counter is a specific value,
That is, it is detected whether or not the value corresponds to the time when the read request interrupt is received by the microprogram or a time close thereto, and in the case of "YES", proceed to the next step and
If “O”, proceed to step. The clock timer 6 is set to a value (number of clocks) suitable for the communication speed and the performance of the microprogram, and the process proceeds to the next step. The clock timer 6 performs a counting operation each time it receives a reception clock, and proceeds to the next step. Whether or not the clock timer 6 has timed out is detected. If "YES", the process proceeds to the next step, and if "NO", this determination is repeated. A write request interrupt is issued to the microprogram 3. .. By such a procedure, the write request generated in the data conversion unit 2 is sent to the microprogram 3.

[0011]

In this way, the data conversion unit 2 for writing the parallel data for transmission sent from the CPU 8 and converting the parallel data into parallel-serial data.
When a write request for the next transmission parallel data is generated, the state of the reading flag 4 and the count value of the clock counter 5 are detected as a hardware signal, and the detected output is converted into data. When the microprogram 3 indicates a time point when the microprogram 3 receives a read request interrupt from the unit 2 or a time point near the time point, the microprogram 3
By delaying the activation of the write request interrupt with respect to the operation time of the clock timer 6, it is possible to prevent the microprogram 3 from receiving the read request interrupt and the write request interrupt at substantially the same time, and the processing load on the microprogram 3 is temporarily reduced. I try not to increase it.

[0012]

Embodiments of the present invention will be described with reference to FIGS. 3 shows a transmission / reception adapter of the present invention, and FIG. 4 shows a timing chart in the case of delaying the activation of a write request interrupt.

In FIG. 3, 11 is a transmission / reception adapter, 12 is an MPU, 13 is a bus LSI, 14 is a RAM for storing transmission / reception data, 15 is a ROM for storing microprograms and the like, and 16 is data serial-parallel. Communication LSI (data conversion unit) that performs conversion, parallel-serial conversion, error correction, etc., 17 is a reading flag, 18 is a 3-bit clock counter, 19 is a clock timer, 20 is a CPU, and 21 is a transmission line. ing.

Here, when the operation of the transmission / reception adapter 11 is started, the microprogram stored in the ROM 15 is M
The parallel data for transmission which is read by the PU 12 and is sent from the CPU 20 and the parallel data after reception which is read from the communication LSI 16 are once stored in the RAM 14 and are then instructed by the microprogram (transmission parallel). In the case of data, the former is written in the communication LSI 16 and the latter is transmitted to the CPU 20 in response to a write request for a write request.

As shown in FIG. 4, the transmitting / receiving adapter 11 is
When 8-bit serial format character data is received, first the serial data of the first character is converted into 8-bit parallel data by the communication LSI 16, and when the conversion is completed, a read request interrupt is sent to the micro controller. Waking up in the program. In addition,
The reception clock is created in the communication LSI 16 as a pulse signal having a constant cycle based on the bit signal received first.

Next, the microprogram which has received the read request interrupt sets the reading flag 17 to "1" and starts the operation of the clock counter 18 which counts up with the received clock. The above operation is repeated each time subsequent character data is received, and the clock counter 18 counts up eight times, that is, the serial-parallel conversion of the next character data (8 bits) is completed. At that time, the count value of "0" is indicated.

Therefore, the reading flag 17 is "1",
Further, when the clock counter 18 indicates a specific value such as "0" or "7", it is the time when the microprogram in the MPU 12 receives the read request interrupt from the communication LSI 16 or near the time, and LSI
It is not desirable as the timing for causing the write request interrupt from 16 to the MPU 12.

Therefore, when a write request is generated in the communication LSI 16, a reading flag 17 is output as a hardware signal.
And the output of the clock counter 18 are detected and the reading flag
When the output of 17 is "1" and the output of the clock counter 18 is "0" or "7", a value commensurate with the communication speed and the performance of the microprogram, for example, the processing of one character
At 200 microseconds, 4 at communication speed 9600bps
(Clock), or 2 (clock) at a communication speed of 4800bps
Is set in the clock timer 19, and thereafter, when the clock timer 19 counts up with the received clock and times out, a write request interrupt is generated to the MPU 12.

When the output of the reading flag 17 and the clock counter 18 is detected as a hardware signal and the output of the reading flag 17 is "0", or the output of the reading flag 17 is "0". If the output of the clock counter 18 is "1" to "6", the write request interrupt microprogram is immediately generated without setting the clock timer 19.

As described above, the timing at which the write request is generated in the communication LSI 16 is determined by the microprogram being the communication LS.
If the timing is substantially the same as the timing at which the read request interrupt from I16 is received, the clock timer 19 determines the timing at which the write request interrupt is issued to the microprogram.
It is delayed by the set time of.

[0021]

According to the present invention, in a transmission / reception adapter equipped with a communication LSI (data conversion section), a write request for fetching, for example, 8-bit parallel transmission data into the communication LSI and performing parallel-serial conversion. When the generation timing is substantially coincident with the timing of the read request interrupt for fetching the parallel data obtained by serial-parallel conversion of the received data in the microprogram from the communication LSI, a write request interrupt to the microprogram is generated. Since the time is delayed by a predetermined time from the time of occurrence so that the microprogram does not receive the read request interrupt and the write request interrupt at the same time, the processing time of the microprogram is equalized, and the microprogram is equalized. It is possible to prevent an overrun from occurring due to a temporary increase in load on the.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention (No. 1).

FIG. 2 is a diagram for explaining the principle of the present invention (No. 2).

FIG. 3 is an explanatory diagram showing a transmission / reception adapter of the present invention.

FIG. 4 is an explanatory diagram showing a timing chart in the case of delaying activation of a write request interrupt according to the present invention.

FIG. 5 is an explanatory diagram showing an outline of a conventional transmission / reception adapter.

[Explanation of symbols]

 In FIG. 1, 1 ... Transmission / reception adapter 2 ... Data conversion unit 3 ... Micro program 4 ... Reading flag 5 ... Clock counter 6 ... Clock timer 7 ... Transmission line 8 ... CPU

Claims (2)

[Claims] 1. Data having a function of serial-parallel converting each received data having the same number of bits transmitted serially via a transmission line, and converting parallel data for transmission into parallel-serial before sending to the transmission line. Transmission / reception provided with a conversion unit and a microprogram for executing processing according to each of the parallel data read request interrupt and the transmission parallel data write request interrupt from the data conversion unit In the data transfer method using the adapter, when the microprogram receives the read request interrupt and starts the read processing, the microprogram sets a reading flag and causes the clock counter to start the reception clock counting processing. When the write request is generated, the status of the reading flag and the output of the clock counter are respectively set in the hardware. The signal is detected as a signal, the state of the reading flag is “reading”, and the value of the clock counter is a specific value corresponding to a time point at which the microprogram receives the read request interrupt or a time point near the time point. In this case, the activation of the write request interrupt for the microprogram may be suspended for a predetermined time so that the timings of receiving the read request interrupt and the write request interrupt in the microprogram do not match. Characteristic data transfer method. 2. The clock timer according to claim 1, further comprising: a clock timer which is set to a predetermined state by detecting the specific value and performs a counting process based on a received clock for the holding. Data transfer method.