JP3496501B2 - Serial data transmission system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transmission system for transmitting serial data between data transmission devices connected via signal lines.

[0002]

2. Description of the Related Art Generally, in an inexpensive data transmission device, a one-chip microcomputer (for example, a 4-bit microcomputer or 8-bit microcomputer) having a small number of processing bits (low capacity, low speed) is often used as a CPU. The program for controlling the device operation and the program for controlling the communication are executed in the same one-chip microcomputer (hereinafter, abbreviated as microcomputer). By the way, in this type of data transmission system,
As a method of receiving serial data in a data transmission device on the receiving side, there is often adopted a method of sampling a data input port (reception port) by performing a timer interrupt at regular intervals.

As a data transmission system of this type, FIG.
As shown in FIG. 2, there is a data transmission device 10 'and a data transmission device 20' which are connected via a signal line 30 formed of a two-wire balanced cable. In the configuration shown in FIG. 7, the data transmission devices 10 ′ and 20 ′ have CPUs 11 ′ and 21 ′ (signal processing units) each composed of a one-chip microcomputer, and a CPU 1
The transmission amplifiers 12 and 22 each including a buffer amplifier for outputting the serial data output from the data output ports 111 and 211 of 1 ′ and 21 ′ to the signal line 30, and the signal line 30.
The serial data input from the CPU 11 ', 21'
The receiving amplifiers 13 and 23, which are buffer amplifiers for outputting to the data input ports 112 and 212 of FIG.
The CPUs 11 ′ and 21 ′ are the data transmission devices 1
The data output ports 111 and 211 are general-purpose output ports for transmitting serial data, and the data input ports 112 and 212 are for receiving serial data. It is a general-purpose input port of.

Next, the operation of the data transmission device 20 'when transmitting serial data from the data transmission device 10' to the data transmission device 20 'will be described with reference to FIG. FIG. 8A shows data input to the data input port 212, and D1, D2, D3, ... Each have 1 bit and are serially input. The CPU 21 'of the data transmission device 20' samples the data input port 212 at a predetermined timing in the timer interrupt process, but performs multi-level sampling in which one bit of data is sampled multiple times to reduce the bit error rate. There is. When performing such multi-valued sampling, a first timer having the same first period T ₁ as the data rate (see FIG. 8B) and a second period T ₂ faster than the data rate are used.
The second timer of FIG.
As shown in (b), during the main processing of the program, the data 1 bit is sampled an odd number of times (3 times) by performing the timer interrupt processing for the data 1 bit an odd number of times (3 times). Arrows indicate sampling timings), and many adopt a method of extracting bits by making a majority decision on an odd number of sampling values.

By the way, the CPU of the data transmission device 20 '
In the program 21 ', if there is no timer interrupt process described above, a main process loop (main routine) that goes around once every fixed time period is executed as shown in FIG. S42), main processing 3
(S43), ..., Main processing N (S46), transmission processing (S47), and reception processing (S48) are executed. In addition,
For example, in the case of configuring a doorphone system as a data transmission system, in which a house person can confirm the visitor indoors and a call can be made between the house person and the visitor, the main processing 1,
The main processing 2, the main processing 3, ..., The main processing N include a switch input capturing processing, transmission / reception data data processing, LED display output processing, melody sound output processing, and the like.

On the other hand, if there is the above-mentioned timer interrupt process, as shown in FIG. 10, the timer interrupt process (S49) for sampling is executed. In addition,
The case of transmitting serial data from the data transmission device 10 ′ to the data transmission device 20 ′ has been described, but the same applies to the case of transmitting serial data from the data transmission device 20 ′ to the data transmission device 10 ′.

[0007]

However, in the above-mentioned conventional configuration, when the timer interrupt processing is executed, the time for executing the main processing is reduced, and the amount of main processing that can be executed within one cycle of the main processing loop is reduced. There was a problem that it would decrease. Therefore, when the data speed is set high and 1-bit multi-level sampling is performed, almost only the timer interrupt processing is executed during the reception of the data, and there is a problem that the execution efficiency of the main processing is lowered. .

The present invention has been made in view of the above circumstances, and an object thereof is to make a microcomputer having a small number of processing bits coexist with a program for controlling device operation and a program for controlling communication. Therefore, it is an object of the present invention to provide a serial data transmission system capable of performing high-speed data transmission and having a low bit error rate with less reduction in execution efficiency of main processing due to interrupt processing.

[0009]

In order to achieve the above object, the invention of claim 1 is a serial transmission system for transmitting serial data between data transmission devices connected via a signal line. The data transmission device has at least a signal processing unit including a microcomputer that controls data communication, and the signal processing unit of the data transmission device on the receiving side is added to the head of the serial data sent via the signal line. An external interrupt port for detecting the generated start bit, an external interrupt means that detects the start bit input to the external interrupt port and activates the reception serial clock, and multiple times the data rate activated by the external interrupt processing. Reception serial clock generating means for generating a reception serial clock having a clock rate of A serial input port for receiving serial data and sampling serial data in synchronization with the reception serial clock, a majority decision means for making a majority decision on a plurality of sampling values obtained for each bit of the serial data, and a serial input A serial register having a plurality of bits for sequentially storing the data input to the port, and a serial register for collectively passing the data of the serial register to the majority decision means by interrupting when the data of the bit number of the serial register enters the serial register. An interrupt means is provided, and the serial interrupt means interrupts only when the data of the number of bits of the serial register is input to the serial register, and the data of the serial register is collectively judged by the majority decision means. Since it is handed over to In comparison with the case where data sampled by the timer interrupt processing as,
The number of interrupt processes that occur during data reception is reduced, and even if a program that controls device operation and a program that controls communication coexist in a small 1-chip microcomputer with a small number of processing bits, main processing by interrupt processing Execution efficiency can be reduced, and high-speed data transmission can be performed while maintaining a low bit error rate.

According to a second aspect of the invention, in the first aspect of the invention, the sampling value obtained for each bit of the serial data is an even number, and the majority decision means is one of an even number of sampling values for each bit. , Since the majority decision is performed using an odd number of sampling values excluding at least the last sampling value and including sampling values from the first sampling value to at least the order of the number obtained by adding 1 to at least one of the plurality of half Even if there is a sampling start delay due to the startup delay of the side serial clock,
Since the majority decision is made excluding the sampling values having a high possibility of sampling error, it is possible to reduce the probability of a data decision error and prevent the majority decision from becoming 50 minutes.

The invention of claim 3 is the invention of claim 1 or claim 2.
In the invention, the signal processing unit of the data transmission device on the transmission side includes a transmission side serial clock generating means for generating a transmission side serial clock having the same speed as the data rate, and a serial for outputting data in synchronization with the transmission side serial clock. Since it has an output port, it is possible to reduce the load of the communication process of the data transmission device on the transmission side as compared with the data transmission device on the reception side.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 shows a schematic configuration diagram of a serial data transmission system of the present embodiment. As shown in FIG. 1, the two data transmission devices 10 and 20 are connected via a signal line 30 composed of a two-line balanced cable.

The data transmission devices 10 and 20 include CPUs 11 and 21 (signal processing units) each including a one-chip microcomputer, and a C
Transmitting serial data output from the serial output ports SO and SO of the PUs 11 and 21 to transmission amplifiers 12 and 22 including buffer amplifiers that output serial data to the signal line 30 including a two-line balanced cable, and serial data input from the signal line 30. The serial input ports SI of the CPUs 11 and 21,
Reception amplifier 1 consisting of a buffer amplifier that outputs to SI
3 and 23 are provided.

Further, CPUs 11 and 21 of the data transmission device
Is a start bit ST added to the beginning of the serial data sent through the signal line 30 (see FIG. 2).
An external interrupt port INT for detecting a start bit ST, an external interrupt means for detecting a start bit ST input to the external interrupt port INT and activating a reception serial clock, and an external interrupt means activated by an external interrupt process and having a multiple of the data rate. Receiving serial clock generating means for generating a receiving serial clock having a clock rate, serial input ports SI, SI for receiving the serial data and sampling the serial data in synchronization with the receiving serial clock, and bits of the serial data A majority decision means for making a majority decision of a plurality of sampling values obtained for each and reproducing the larger sampling value as the data of that bit, and an 8-bit serial register for sequentially storing the data inputted to the serial input port. 11
9 and 219 and the serial registers 119 and 219 are interrupted when 8-bit data is input, and the data of the serial registers 119 and 219 are collectively transferred to the majority decision means (the data is transferred to the internal buses of the CPUs 11 and 21). ) Serial interrupt means, and serial output ports SO, SO for transmitting data in synchronization with the transmission serial clock. The external interrupt ports INT, INT are serial input ports S
It is connected in parallel with I and SI, and is for detecting the rising (or falling) edge of the start bit ST of the received signal and activating an external interrupt for starting data reception.

Here, the CPUs 11 and 21 are composed of a one-chip microcomputer, and are provided with a program for controlling device operation and a program for controlling data communication. The serial input port S of the CPUs 11 and 21
I, SI, serial output ports SO, SO are, for example, a master CPU and a slave C of a multiprocessor in the same device.
Used for data transfer with PU . In addition, the CPU 11,
The 21 serial clock ports SCK and SCK are open. The serial clock ports SCK and SCK of the CPUs 11 and 21 may be used as an input / output port of a synchronous clock for data transfer between a master CPU and a slave CPU of a multiprocessor in the same device, for example, but used in start / stop synchronization. When it is done, it is often opened.

The receiving operation of the data transmission device 20 on the receiving side when the serial data is transferred from the data transmission device 10 to the data transmission device 20 will be described below with reference to FIG. As described above, since the serial input port SI of the CPU 21 and the external interrupt port INT are connected in parallel, both ports SI and IN are received during data reception.
The same serial data is input to T. FIG. 2A shows serial data input to both ports SI and INT of the CPU 21, which includes a start bit ST and data D1.
D2, D3, ...

The CPU 21 detects the rising edge of the start bit ST added to the head of the data input to its own external interrupt port INT, performs external interrupt processing, and activates the reception serial clock. FIG. 2B shows the reception serial clock. Then C
The PU 21 samples the data input to the serial input port SI in synchronization with the rising edge of the reception serial clock shown in FIG. The upward arrow in FIG. 2 indicates the timing of sampling.

Here, in the present embodiment, FIG.
The serial clock rate of the receiving serial clock shown in (b) is set to four times the data rate of the serial data shown in FIG. 2 (a), and one bit of the serial data is sampled four times (four-value sampling is performed. Exist).
Next, the program processing of the CPU 21 will be described with reference to FIG. 3A shows serial data input to the serial input port SI, and FIG.
(B) shows the relationship between the main process and the serial interrupt process, and the upward arrow in FIG. 3 shows the sampling timing.

Since the CPU 21 fetches the data by serial interrupt processing at the time when 8 bits of data are stored in the serial register 219, the serial clock rate is set to 4 times the data rate as described above, and 1 bit is set to 4 bits.
In the case of sampling twice, when two bits of the received data are sampled, the data is taken in by the serial interrupt processing and the majority decision is made by the majority decision means.

However, in this embodiment, the serial interrupt means interrupts only when 8-bit data is input to the serial register 219, and the data in the serial register 219 is collectively passed to the majority decision means. Compared with the conventional case where data is sampled by the timer interrupt process, the number of interrupt processes entering during data reception is reduced, and the device operation is controlled by a small 1-chip microcomputer with a small number of processing bits. Even when a program and a program for controlling communication coexist, it is possible to reduce a decrease in execution efficiency of main processing due to interrupt processing, and it becomes possible to perform high-speed data transmission while maintaining a low bit error rate.

In the present embodiment, four-value sampling in which one bit is sampled four times is performed with the serial clock rate being four times the data rate. For example, the serial clock rate is eight times the data rate (a multiple of 4). 8 bits sampling may be performed in which 1 bit of the received data is sampled 8 times. Further, in the present embodiment, the case where the baseband transmission (the transmission in which the NZR code is sent to the signal line as it is) between the data transmission devices 10 and 20 is described, but the carrier transmission may be performed via the modem. .

(Embodiment 2) By the way, in Embodiment 1, since there is an even number of sampling data for 1 bit of the received data, there may be a case where the majority judgment is made into five minutes. Further, since the reception serial clock is activated by an external interrupt due to the detection of the rising (or falling) edge of the start bit ST input to the external interrupt port INT, the start bit ST indicated by the solid line in FIG. There is a clock start time T ₃ until the start of the serial clock indicated by the one-dot chain line with respect to the rising. That is, the start time of the serial clock is delayed with respect to the rising time of the start bit ST. This startup time T ₃ is caused by the software processing time. Therefore, in the configuration of the first embodiment,
The higher the sampling data, the higher the probability of error.

In order to solve this kind of problem, in the present embodiment, in the same configuration as that of the first embodiment shown in FIG. 1, when the receiving CPU 21 samples one bit of data four times, As shown in (b), the majority decision of the data is made by three sampling values excluding the last one sampling value for the bit. Further, when the number of times of sampling 1 bit of data is 8 times, the majority decision is made by using the first to fifth sampling values as shown in FIG. I am supposed to do it. In addition,
When the number of sampling times for 1 bit of data is 8 times, it is 1 time in the latter half (that is, the end for that bit).
The majority decision may be performed by using the sampling values of the first to seventh times excluding the sampling values of.

In the present embodiment, however, the CPU 21
Is an odd number of sampling values excluding at least the last sampling value among the even number of sampling values for each bit and including sampling values from the first sampling value to at least the order of the number obtained by adding 1 to the plurality of half numbers. Since the majority decision is made using the sampling value of, even if there is a sampling start delay due to the delay in the startup of the reception serial clock, the majority decision is made except for the sampling value with a high possibility of sampling error. It is possible to reduce the probability of data judgment error and prevent the majority judgment from becoming 50 minutes. Therefore, the error rate of the data reproduced by the majority decision means can be reduced.

(Third Embodiment) The basic configuration of this embodiment is the same as that of the first embodiment, and the data transmission device 10 on the transmission side is
6A, the data rate of the transmission data output from the serial output port SO of the CPU 11 and the transmission serial clock of the CPU 11 shown in FIG. The feature is that the data is transmitted in synchronization with the falling edge of.

The CP of the data transmission device 20 on the receiving side
As described in the first embodiment, U21 detects the rising edge of the start bit ST added to the head of the serial data input to the external interrupt port INT, and performs the external interrupt process in FIG. 6) is activated, and data of the serial input port SI shown in FIG. 6C is sampled in synchronization with the rising edge of the reception serial clock.

Therefore, in this embodiment, the load of the communication process of the data transmission device 10 on the transmission side can be reduced as compared with the data transmission device 20 on the reception side.

[0028]

According to a first aspect of the present invention, there is provided a serial transmission system for transmitting serial data between data transmission devices connected via a signal line, both data transmission devices being at least a micro controller for controlling data communication. An external interrupt port for detecting a start bit added to the head of the serial data sent through the signal line is provided, which has a signal processing unit including a computer. And an external interrupt means that detects the start bit input to the external interrupt port and activates the receiving serial clock, and a receiving interrupt that is activated by the external interrupt processing and that generates the receiving serial clock with a clock rate that is a multiple of the data rate. The serial clock generating means and the serial clock for receiving the serial data are input. A serial input port for sampling serial data in synchronism with the data, a majority decision means for making a majority decision of a plurality of sampling values obtained for each bit of the serial data, and a data input to the serial input port are sequentially stored. Since a serial register having a plurality of bits and serial interrupt means for interrupting when the data of the number of bits of the serial register is input to the serial register and collectively delivering the data of the serial register to the majority decision means, Only when the data of the number of bits of the serial register is stored in the register, the interrupt is issued by the serial interrupt means and the data of the serial register is collectively delivered to the majority decision means. When sampling data Compared with the above, the number of interrupt processes entering during data reception is reduced, and even when a program for controlling device operation and a program for controlling communication coexist in a small 1-chip microcomputer with a small number of processing bits, There is an effect that a decrease in the execution efficiency of the main process due to the interrupt process can be reduced and high-speed data transmission becomes possible as compared with the conventional method while keeping the bit error rate low.

According to a second aspect of the present invention, in the first aspect of the invention, the sampling value obtained for each bit of the serial data is an even number, and the majority decision means is an even number of sampling values for each bit. , Since the majority decision is performed using an odd number of sampling values excluding at least the last sampling value and including sampling values from the first sampling value to at least the order of the number obtained by adding 1 to at least one of the plurality of half Even if there is a sampling start delay due to the startup delay of the side serial clock,
Since a majority decision is made excluding a sampling value that is highly likely to have a sampling error, it is possible to reduce the probability of a data decision error and to prevent the majority decision from becoming 50 minutes.

The invention of claim 3 is the same as claim 1 or claim 2.
In the invention, the signal processing unit of the data transmission device on the transmission side includes a transmission side serial clock generating means for generating a transmission side serial clock having the same speed as the data rate, and a serial for outputting data in synchronization with the transmission side serial clock. Since the output port is provided, there is an effect that the load of the communication process of the data transmission device on the transmission side can be reduced as compared with the data transmission device on the reception side.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment.

FIG. 2 is an operation explanatory diagram of the above.

FIG. 3 is an operation explanatory diagram of the above.

FIG. 4 is an explanatory diagram of an operation example of the second embodiment.

FIG. 5 is an explanatory diagram of another operation example of the above.

FIG. 6 is an operation explanatory diagram of the third embodiment.

FIG. 7 is a schematic configuration diagram showing a conventional example.

FIG. 8 is an operation explanatory diagram of the above.

FIG. 9 is an explanatory diagram of an operation of the above.

FIG. 10 is an operation explanatory diagram of the above.

[Explanation of symbols]

10 Data transmission device 20 Data transmission equipment 11 CPU 21 CPU 30 signal lines 119 Serial register 219 serial register SO serial output port SI serial input port SCK serial clock port INT External interrupt port

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-4-329721 (JP, A) JP-A-6-37745 (JP, A) JP-A-1-276945 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 13/38 350 H04L 7/00 H04L 25/08 H04L 25/40 WPI (DIALOG)

Claims (3)

(57) [Claims] 1. A serial transmission system for transmitting serial data between data transmission devices connected via a signal line, wherein both data transmission devices include a signal processing unit including at least a microcomputer for controlling data communication. The signal processing unit of the data transmission device on the receiving side has an external interrupt port for detecting a start bit added to the beginning of the serial data sent via the signal line, and an input to the external interrupt port. An external interrupting means for detecting a start bit to activate a receiving serial clock, and a receiving serial clock generating means activated by an external interrupt processing for generating a receiving serial clock having a clock rate of a multiple of the data rate, Serial data is input and serialized in synchronization with the above reception serial clock. A serial input port for sampling data, a majority decision means for making a majority decision on a plurality of sampling values obtained for each bit of serial data, and a multi-bit serial register for sequentially storing data input to the serial input port. A serial data transmission system comprising: a serial register; and a serial interrupt means for interrupting when the data of the number of bits of the serial register has entered the serial register and collectively delivering the data of the serial register to the majority decision means. 2. The number of sampling values obtained for each bit of serial data is an even number, and the majority decision means is 1
Of the even number of sampling values for each bit, an odd number of sampling values excluding at least the last sampling value and including sampling values from the first sampling value to at least the order of the number obtained by adding 1 to the above half The majority decision is made by using.
The described serial data transmission system. 3. The signal processing unit of the data transmission device on the transmission side outputs data in synchronization with the transmission side serial clock generating means for generating a transmission side serial clock having the same speed as the data rate. The serial data transmission system according to claim 1 or 2, further comprising a serial output port.