JPH0545394A - Testing device of hysteresis comparator - Google Patents

Abstract

PURPOSE:To conduct a test of a hysteresis comparator automatically, easily and asynchronously with an input sine wave. CONSTITUTION:The device is constructed of a peak detecting means 17 which detects the peak of an output waveform of a sine wave generating means 12, an H output detecting means 18 which detects an H output of a hysteresis comparator 11 at its peak, an L output detecting means 19 which detects an L output of the hysteresis comparator 11 at its peak, and latch means 20 and 21 which latch an output of the H output detecting means 18 and an output of the L output detecting means 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hysteresis comparator test device used in a data reproducing mechanism of a magnetic disk device. The threshold measurement principle, which is related to the frequency characteristics of the hysteresis comparator (variable threshold comparator), is that the limit of the normal output when the sine wave is input to the hysteresis comparator and its amplitude is lowered. Measuring the input amplitude.

Therefore, it is necessary to develop a test device which can automatically and easily measure whether or not the output of the hysteresis comparator is normal.

[0003]

2. Description of the Related Art As a conventional method for testing a hysteresis comparator, for example, when the input amplitude of a sine wave input to the hysteresis comparator is reduced, a limit of normal output waveform is monitored with an oscilloscope or the like. was there. Further, a test device as shown in FIG. 6 is also known.

In FIG. 6, 1 is a hysteresis comparator, and 2 is a hysteresis level setting device for setting a hysteresis level. When a sine wave is generated by the sine wave generator 3 and the generated sine wave is input to the hysteresis comparator 1, the logic pattern that should be normally output from the hysteresis comparator 1 is converted into an analog input-
The logic pattern synchronization circuit 4 synchronizes with each other, and the pattern comparison circuit 5 performs pattern comparison to determine whether the output is the expected pattern.

FIG. 7 shows input, output and synchronization patterns in this conventional test apparatus.

[0006]

However, in the test method of checking with an oscilloscope or the like in order to judge whether the output of the hysteresis comparator is normal, the judgment standard for judging whether it is normal or not is clearly determined. However, there is a problem that the measurement cannot be automated.

Also, in the case of a test apparatus using an analog input-logic pattern synchronization circuit and a pattern comparison circuit, it is suitable for automation of measurement, but it is necessary to accurately synchronize the analog input and the expected value pattern of the logic. ..
However, there is a problem that accurate pattern synchronization between the analog input and the logic is difficult because of the configuration, and the measurement cannot be easily performed.

The present invention has been made in view of such conventional problems, and a hysteresis comparator capable of automatically and easily testing a hysteresis comparator asynchronously with an input sine wave. The purpose of the present invention is to provide a testing device for data.

[0009]

FIG. 1 illustrates the principle of the present invention. In FIG. 1, 17 is a peak detecting means for generating a sine wave input to the hysteresis comparator 11 and detecting the peak of the output waveform of the sine wave generating means 12 for varying its amplitude, and 18 is the hysteresis comparator 1
H output detecting means for detecting H output of 1 at the peak, 1
Reference numeral 9 is an L output detecting means for detecting the L output of the hysteresis comparator 11 at the peak, and 20 and 21 are latching means for latching the output of the H output detecting means 18 and the output of the L output detecting means 19.

[0010]

In the present invention, the H output detecting means detects the H output of the hysteresis comparator at the peak detected by the peak detecting means, and the L output detecting means detects the L output of the hysteresis comparator at the peak. The changes in the outputs of the H output detecting means and the L output detecting means are latched by the latch means.

As a result, it is possible to detect whether the output of the hysteresis comparator is normal or not as a direct current asynchronously with the sine wave which is input. As a result, the hysteresis comparator can be tested automatically and easily.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 4 are views showing an embodiment of the present invention.
In FIG. 2, reference numeral 11 denotes a hysteresis comparator which is a threshold variable comparator, and the characteristic of this hysteresis comparator 11 is tested here. Reference numeral 12 is a sine wave generator as a sine wave generating means. The sine wave generator 12 generates a sine wave to be input to the hysteresis comparator 11, and also makes its amplitude variable. The amplitude and the oscillation frequency of the sine wave generator 12 are controlled by the control device 14 which is a control means.

The controller 14 sends a reset signal to the H output detector 18, the L output detector 19, and the latches 20 and 21, and a hysteresis voltage control signal to the hysteresis voltage setting DC voltage generator 23 for the hysteresis comparator 11. Control signals for setting the amplitude and frequency are applied to the sine wave generator 12, respectively. In addition, the control device 14
Detects the error detection signal from the AND gate 13,
When the error detection signal becomes L level, the set value of the amplitude of the sine wave generator 12 is read and the read value is displayed on the measurement value display device 22.

Reference numeral 15 is a differentiating circuit, which differentiates the input sine wave. 16 is a zero-cross comparator, and the zero-cross comparator 16 is a differentiating circuit 1
The pulse that rises or falls at the zero crossing of the sine wave output from 5 is output. The differentiating circuit 15 and the zero-cross comparator 16 constitute a peak detecting means 17 for detecting the peak of the input waveform.

Reference numeral 18 is an H output detector as an H output detecting means. The H output detector 18 is composed of a D flip-flop with preset and reset. The H output detector 18 outputs an H level at the time of reset input, determines whether the output of the hysteresis comparator 11 is normal at the rising edge of the output of the zero-cross comparator 16,
If it is normal, the H output remains as it is, and if it is abnormal, the output is changed to the L level.

Reference numeral 19 is an L output detector as an L output detecting means. The L output detector 19 comprises a D flip-flop with preset and reset. The L output detector 19 outputs an H level at the time of reset input, determines whether the output of the hysteresis comparator 11 is normal at the falling edge of the zero-cross comparator 16, and if it is normal, the L output remains unchanged. If it is abnormal, the output is changed to H level.

Reference numeral 20 is a latch as a latch means,
The latch 20 comprises a D flip-flop with preset and reset. The latch 20 outputs H level when reset is input, and the output of the H output detector 18 changes from H level to L level.
When the level changes, the output becomes L level and the state is maintained. 21 is a latch as a latch means,
The latch 21 is a D flip-flop with preset and reset. The latch 21 outputs H level at the time of reset input, and the output of the L output detector 19 changes from L level to H level.
When the level changes, the output becomes L level and the state is maintained.

Reference numeral 13 is the AND gate to which the outputs of the latches 20 and 21 are input. The AND gate 23 outputs the H level when the hysteresis comparator 11 is operating normally, and the hysteresis comparator 11 outputs the H level side and the L level. On the other hand, if there is an abnormality at least once on the level side, the L level is output. Next, the operation will be described.

First, the controller 14 causes the DC voltage generator 23 to generate a hysteresis voltage to be measured, and the hysteresis voltage of the hysteresis comparator 11 to be measured is set. A control signal is applied from the control device 14 to the sine wave generator 12 so as to generate a sine wave having a certain amplitude V1 at the frequency to be measured.

Next, from the control device 14 to the H output detector 1
8. A reset signal is generated in the L output detector 19 and the latches 20 and 21 to reset the output of the AND gate 13 (set to H level). If the output of the AND gate 13 does not become H level despite the input of the reset signal, the control signal is given again to increase the amplitude of V1.

Next, the control device 14 causes the sine wave generator 12 to
A control signal is applied so as to reduce the amplitude by ΔVA from the amplitude currently generated. At this time, when the output of the AND gate 13 changes from H level to L level, the setting value of the sine wave generator 12 is read out to the control device 14 and displayed on the measurement value display device 22.

If the output of the AND gate 13 remains H level, the above is repeated until the output of the AND gate 13 becomes L level. Next, FIG. 3 shows a timing chart at the normal time. In FIG. 3, A is the waveform input to the hysteresis comparator 11, B is the output of the hysteresis comparator 11, and C is the output of the differentiator 15.
D is the output of the zero cross comparator 16, E is the reset input, F is the output of the H output detector 18, G is the output of the L output detector 19, H is the output of the latch 20, and I is the output of the latch 21. Outputs, and J indicates the output of the AND gate 13, respectively.

At the rising edge of the zero-cross comparator 16, the H output detector 18 receives the hysteresis comparator 1
The H output of 1 is determined and remains the H output. The L output detector 19 determines the L output of the hysteresis comparator 11 at the falling edge of the zero cross comparator 16,
L output remains. Therefore, the latches 20, 21
Both output H level, and the output of the AND gate 13 is H level.

Next, FIG. 4 shows a timing chart at the time of abnormality. In FIG. 5, when the input is lowered, when the input waveform does not reach the hysteresis level (see A), the output of the hysteresis comparator 11 becomes as shown by B, and the L output detector 19 causes the zero cross comparator 16 to rise. At the falling edge, it is determined that the output of the hysteresis comparator 11 is at the H level, and the output is inverted from the L level to the H level (see G).

Therefore, the output of the latch 21 also changes from H level to L level, and the output of the AND gate 13 becomes L level. Thus, the hysteresis comparator 11
It is possible to detect whether or not the output of is normal in terms of direct current asynchronous with the input sine wave. As a result, the hysteresis comparator 11 can be tested automatically and easily. Further, the input amplitude when the output is inverted can be automatically measured.

Next, FIG. 5 is a diagram showing another embodiment of the present invention. In FIG. 5, reference numeral 24 is a DC voltage generator as an initial state setting means, and the DC voltage generator 24 is
It is controlled by a DC voltage control signal from a control device 14A as a control means, and generates a DC voltage for setting the initial value (H level and L level) state of the hysteresis comparator 11 to be measured.

Reference numeral 25 is a relay controlled by a DC application signal from the controller 14A. The relay 25 is connected only when the initial state is given to the hysteresis comparator 11, and is disconnected at the time of measurement. Reference numeral 26 is a memory and an arithmetic unit, and the memory and arithmetic unit 26 is the controller 14
The measured value read by A is stored and calculated.

First, the controller 14A causes the DC voltage generator 23 to generate a hysteresis voltage to be measured, and the hysteresis voltage of the hysteresis comparator 11 to be measured is set. A relay 25 is connected to determine the initial value of the hysteresis comparator 11 to be measured, and the control device 14A controls the DC voltage generator 24 so that the output of the hysteresis comparator 11 to be measured becomes H level.

After disconnecting the relay 25, the controller 1
4A generates a reset signal from the H output detector 18, the L output detector 19, and the latches 20 and 21, and the AND gate 1
The output of 3 is reset (set to H level). A control signal is applied from the control device 14A to the sine wave generator 12 so as to increase the amplitude by 0 to ΔVA at the frequency to be measured.

At this time, when the output of the AND gate 13 changes from the H level to the L level, the set value of the sine wave generator 12 is read out to the control device 14A and stored in the memory and the arithmetic unit 26 as OFFSET1. If the output of the AND gate 13 remains H level, the above is repeated until the output of the AND gate 13 becomes L level.

Next, the relay 25 is connected, and the DC voltage generator 24 is controlled by the controller 14A so that the output of the hysteresis comparator 11 to be measured becomes L level. After disconnecting the relay 25, the H output detector 18, the L output detector 19, the latches 20 and 2 are connected from the control device 14A.
A reset signal is generated at 1 to reset the output of the AND gate 13 (set to H level).

The control device 14A gives a control signal to the sine wave generator 12 so as to increase the amplitude by 0 to ΔVA at the frequency to be measured. At this time, if the output of the AND gate 13 changes from H level to L level,
The set value of the sine wave generator 11 is read out to the control device 14A and stored in the memory and the calculation unit 26 as OFFSET2.

If the output of the AND gate 13 remains H level, the above is repeated until the output of the AND gate 13 becomes L level. O in memory and operation unit 26
The difference between FFSET1 and OFFSET2 is calculated, and the measured value table device 22 displays the voltage difference between OFFSET1 and OFFSET2. In this way, the offset voltage can be automatically measured.

[0034]

As described above, according to the present invention, whether or not the output of the hysteresis comparator is normal can be detected in direct current asynchronously with the sine wave that is input. Test automatically,
And it can be performed easily.

Further, the amplitude of the input wave when inverted can be automatically obtained, and further, the input offset voltage can be automatically obtained.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

[Fig. 3] Timing chart for normal operation

FIG. 4 is a timing chart when an abnormality occurs

FIG. 5 is a diagram showing another embodiment of the present invention.

FIG. 6 is a diagram showing a conventional example.

FIG. 7 is a conventional timing chart.

[Explanation of symbols]

 11: Hysteresis Comparator 12: Sine Wave Generator (Sine Wave Generator) 13: AND Gate 14, 14A: Control Device (Control Means) 15: Differentiation Circuit 16: Zero Cross Comparator 17: Peak Detection Means 18: H Output Detector ( H output detecting means) 19: L output detector (L output detecting means) 20, 21: Latch (latch means) 22: Measured value display device 23: DC voltage generator for hysteresis setting 24: DC voltage generator (initial) State setting means) 25: Relay 26: Memory and arithmetic unit

Claims (3)

[Claims] 1. A peak detecting means (17) for detecting a peak of an output waveform of a sine wave generating means (12) for generating a sine wave input to a hysteresis comparator (11) and varying its amplitude, and the hysteresis comparator. (11)
H output detecting means for detecting the H output of
8) and L output detection means (19) for detecting the L output of the hysteresis comparator (11) at the peak,
Latch means (20), (2) for latching the output of the H output detection means (18) and the output of the L output detection means (19)
1) A device for testing a hysteresis comparator, which is provided. 2. The hysteresis comparator test apparatus according to claim 1, further comprising control means (14) for determining the amplitude of the input sine wave when the output of the hysteresis comparator (11) is inverted. 3. An initial state setting means (24) for giving an initial state to the hysteresis comparator (11) is provided, and an input amplitude at which the input amplitude is gradually increased and the output is inverted is separately obtained for the H output and the L output. 3. The hysteresis comparator test apparatus according to claim 2, further comprising control means (14A) for obtaining an input offset voltage of the hysteresis comparator (11) from the leverage.