JPH0544827B2 - - Google Patents
Info
- Publication number
- JPH0544827B2 JPH0544827B2 JP14891884A JP14891884A JPH0544827B2 JP H0544827 B2 JPH0544827 B2 JP H0544827B2 JP 14891884 A JP14891884 A JP 14891884A JP 14891884 A JP14891884 A JP 14891884A JP H0544827 B2 JPH0544827 B2 JP H0544827B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- substrate
- forming
- pattern
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 claims description 71
- 239000000758 substrate Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 6
- 238000003672 processing method Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 17
- 239000010408 film Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体、金属、誘電体等で構成される
基板上に薄膜パターンを形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a thin film pattern on a substrate made of a semiconductor, metal, dielectric, or the like.
基板上に薄膜パターンを形成する１方法に、リ
フトオフ法が知られている。本方法は、写真喰刻
法を用いてパターン化されたフオトレジスト等の
マスク材料が形成された基板上に薄膜を形成し、
しかる後、マスク材料を除去することにより、マ
スク材料上に形成された薄膜をも除去し、薄膜パ
ターンを形成する方法である。本方法の特徴は薄
膜パターンの寸法がフオトレジスト等のマスク材
料の寸法にのみ依存するため、フオトレジストマ
スクを用いて全面的に形成された薄膜をエツチン
グし、薄膜パターンを形成する通常のパターン形
成方法に比べて寸法精度が高いことである。
A lift-off method is known as one method for forming a thin film pattern on a substrate. In this method, a thin film is formed on a substrate on which a mask material such as a photoresist is patterned using a photolithography method.
Thereafter, by removing the mask material, the thin film formed on the mask material is also removed to form a thin film pattern. The feature of this method is that the dimensions of the thin film pattern depend only on the dimensions of the mask material such as photoresist. This method has higher dimensional accuracy than other methods.
第２図に、従来のリフトオフ法の工程を示す。
第２図ａに写真喰刻法を用いてパターニングした
フオトレジスト等のマスク用第１の薄膜２０２が
形成されたシリコン、金属、セラミツクス等の基
板２０１を示す。 FIG. 2 shows the steps of the conventional lift-off method.
FIG. 2a shows a substrate 201 made of silicon, metal, ceramics, etc., on which a first thin film 202 for a mask, such as a photoresist, is patterned using a photolithography method.
第２図ｂに、第２図ａの表面に真空蒸着法等を
用いて第２の薄膜２０４，２０４′，２０５およ
び２０５′を形成した構造を示す。 FIG. 2b shows a structure in which second thin films 204, 204', 205 and 205' are formed on the surface of FIG. 2a using a vacuum evaporation method or the like.
次に、第１の薄膜がエツチングでき、しかも第
２の薄膜がエツチングできないエツチング液を用
いて２０４直下の第１の薄膜を除去し、２０４を
剥離する。この結果、先に開口部２０３，２０
３′が設けられていた部分に第２の薄膜２０５，
２０５′が残り、第２図ｃのように、基板２０１
上に第２の薄膜パターンが形成される。 Next, the first thin film immediately below 204 is removed using an etching solution that can etch the first thin film but not the second thin film, and 204 is peeled off. As a result, the openings 203 and 20
A second thin film 205,
205' remains, and as shown in FIG. 2c, the substrate 201
A second thin film pattern is formed thereon.
一例としてセラミツク基板を２０１に、シツプ
レー社のAZ−1450Jフオトレジストを第１の薄膜
に、金膜を第２の薄膜に使用し、エツチング液に
アセトンやシツプレー社の1112A剥離液を使用す
れば、セラミツク基板に金パターンを形成でき
る。この方法では、第１の薄膜２０２を除去する
時、エツチング液が２０４と２０５の境界からの
み浸透する。従つて、基板上に形成される薄膜パ
ターンの面積に比べて十分に小さい場合、２０２
をエツチングするのに長時間要する欠点がある。
このエツチング時間を短縮する目的で超音波をか
けながらエツチングする方法もよく用いられる
が、この場合、第２の薄膜と基板の接着力が弱い
と、２０５も剥離してしまうことがある。 For example, if a ceramic substrate is used as 201, Shipley's AZ-1450J photoresist is used as the first thin film, a gold film is used as the second thin film, and acetone or Shipley's 1112A stripper is used as the etching solution. Gold patterns can be formed on ceramic substrates. In this method, when removing the first thin film 202, the etching solution penetrates only from the boundary between 204 and 205. Therefore, if the area is sufficiently small compared to the area of the thin film pattern formed on the substrate, 202
It has the disadvantage that it takes a long time to etch.
In order to shorten this etching time, a method of etching while applying ultrasonic waves is often used, but in this case, if the adhesive strength between the second thin film and the substrate is weak, 205 may also peel off.
本発明の目的は上に述べた従来のリフトオフ法
の欠点を除去することである。
The purpose of the present invention is to eliminate the drawbacks of conventional lift-off methods mentioned above.
本発明は基板表面上に第１の薄膜を形成し、該
第１の薄膜に写真喰刻法を用いて第１の薄膜を貫
通する少なくとも１つの開口部を設け、次に開口
部をもつ第１の薄膜が形成されている基板上に第
２の薄膜を形成した後、第２の薄膜のエツチング
に耐える
材料を用いて、少なくとも前記第１の薄膜の開
口部に形成されている第２の薄膜を保護するマス
クパターンを形成し、しかる後、該マスクパター
ンを用いて第２の薄膜をエツチングし、最後に、
第１の薄膜およびマスクパターンを除去すること
により、基板上にパターン化された第２の薄膜を
形成することを特徴とする薄膜加工方法。であ
る。
The present invention involves forming a first thin film on a substrate surface, providing the first thin film with at least one opening passing through the first thin film using photolithography, and then forming a first thin film with the opening. After forming a second thin film on the substrate on which the first thin film is formed, a second thin film formed at least in the opening of the first thin film is etched using a material that can withstand etching of the second thin film. Forming a mask pattern to protect the thin film, then etching a second thin film using the mask pattern, and finally,
A thin film processing method comprising forming a patterned second thin film on a substrate by removing a first thin film and a mask pattern. It is.
以下、図面を用いながら本発明の実施例を詳細
に説明する。第１図は、本発明による製造工程の
流れを示したものである。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the flow of the manufacturing process according to the present invention.
第１図ａは、半導体、金属、絶縁物等の基板１
０１の表面に一様に形成されたフオトレジスト等
の第１の薄膜１０２に写真喰刻法を用いて開口部
１０３，１０３′を設けた断面図である。 Figure 1a shows a substrate 1 of semiconductor, metal, insulator, etc.
01 is a cross-sectional view in which openings 103 and 103' are provided in a first thin film 102 made of photoresist or the like uniformly formed on the surface of 01 using photolithography.
次に第１図ｂに示すように表面に、金等の第２
の薄膜を真空蒸着法等を用いて形成する。ここ
で、１０２上に形成される第２の薄膜を１０４、
開口部１０３，１０３′に形成される第２の薄膜
をそれぞれ１０５，１０５′とする。 Next, as shown in Figure 1b, a second layer of gold or the like is applied to the surface.
A thin film is formed using a vacuum evaporation method or the like. Here, the second thin film formed on 102 is 104,
The second thin films formed in the openings 103 and 103' are referred to as 105 and 105', respectively.
次に、フオトレジスト等の第３の薄膜を全面に
形成し、この後該第３の薄膜を写真喰刻法により
パターニングし第１図ｃに示されているような１
０５，１０５′を完全に覆うマスクパターン１０
６，１０６′を形成する。 Next, a third thin film such as photoresist is formed on the entire surface, and then the third thin film is patterned by photolithography to form a pattern as shown in FIG. 1c.
Mask pattern 10 that completely covers 05, 105'
6,106' is formed.
次に、１０６，１０６′をマスクとして第２の
薄膜１０４をエツチングすることにより第１図ｄ
を得る。１０４が金膜の場合のエツチング液とし
ては王水やヨウ素系エツチヤントがある。 Next, by etching the second thin film 104 using 106 and 106' as a mask, the second thin film 104 is etched as shown in FIG.
get. When 104 is a gold film, examples of the etching solution include aqua regia and iodine-based etchant.
最後に１０６，１０６′および１０２をフオト
レジスト剥離液を用いて除去することにより、１
０７も剥離され、第１図ｅに示されているよう
に、第２の薄膜パターン１０５，１０５′が基板
１０１上に形成される。 Finally, 106, 106' and 102 are removed using a photoresist stripping solution.
07 is also peeled off, and a second thin film pattern 105, 105' is formed on the substrate 101, as shown in FIG. 1e.
以上示した実施例では、第１の薄膜および第３
の薄膜としてフオトレジストを一例として示した
が、第２の薄膜のエツチング液に耐える材料であ
ればこれに限らない。例えば、第２の薄膜が金膜
の場合二酸化シリコン膜を第１および第３の薄膜
にフツ酸を第１および第３の薄膜に使用すること
もできる。 In the embodiments shown above, the first thin film and the third
Although photoresist is shown as an example of the thin film, the material is not limited to this as long as it can withstand the etching solution for the second thin film. For example, when the second thin film is a gold film, a silicon dioxide film may be used as the first and third thin films, and hydrofluoric acid may be used as the first and third thin films.
最後に第２の薄膜として金膜を一例としたが、
他の金属膜、半導体膜あるいは絶縁膜でもかまわ
ない。 Finally, we took a gold film as an example as the second thin film, but
Other metal films, semiconductor films, or insulating films may be used.
以上述べたように、本発明を用いればエツチン
グ時間が長くなる、あるいは、第２の薄膜パター
ンの剥離が発生する可能性がある、等の従来のリ
フトオフ法の欠点が解消でき、リフトオフ法の最
大のメリツトである高精度のパターン形成が容易
になる。
As described above, by using the present invention, the drawbacks of the conventional lift-off method, such as the long etching time and the possibility of peeling of the second thin film pattern, can be overcome, and the maximum High-precision pattern formation, which is an advantage of this method, becomes easier.
第１図ａ〜ｅは本発明による製造工程の流れを
示した断面図である。１０１は、基板、１０２は
第１の薄膜、１０３，１０３′は第１の薄膜に形
成された開口部である。１０４は第１の薄膜上に
形成された第２の薄膜、１０５，１０５′は開口
部１０３，１０３′に１０４と同時に形成された
第２の薄膜である。また、１０６，１０６′はパ
ターン化された第３の薄膜である。
第２図はａ〜ｃ、従来まで用いられているリフ
トオフ法を用いたパターン形成工程の流れを示す
断面図である。２０１は基板、２０２は第１の薄
膜、２０３，２０３′は第１の薄膜に形成された
開口部である。また２０４，２０５，２０５′は
第２の薄膜である。
1A to 1E are cross-sectional views showing the flow of the manufacturing process according to the present invention. 101 is a substrate, 102 is a first thin film, and 103 and 103' are openings formed in the first thin film. 104 is a second thin film formed on the first thin film, and 105 and 105' are second thin films formed at the same time as 104 in the openings 103 and 103'. Further, 106 and 106' are patterned third thin films. FIGS. 2A to 2C are cross-sectional views showing the flow of a pattern forming process using a conventional lift-off method. 201 is a substrate, 202 is a first thin film, and 203 and 203' are openings formed in the first thin film. Further, 204, 205, 205' are second thin films.
Claims (1)
薄膜に写真喰刻法を用いて第１の薄膜を貫通する
少なくとも１つの開口部を設け、次に開口部をも
つ第１の薄膜が形成されている基板上に第２の薄
膜を形成した後、第２の薄膜のエツチングに耐え
る材料を用いて、少なくとも前記第１の薄膜の開
口部に形成されている第２の薄膜を保護するマス
クパターンを形成し、しかる後、該マスクパター
ンを用いて第２の薄膜をエツチングし、最後に、
第１の薄膜およびマスクパターンを除去すること
により、基板上にパターン化された第２の薄膜を
形成することを特徴とする薄膜加工方法。1. Forming a first thin film on a surface of a substrate, providing the first thin film with at least one opening penetrating the first thin film using photolithography, and then forming a first thin film with the opening. After forming a second thin film on the substrate on which the thin film is formed, at least the second thin film formed in the opening of the first thin film is etched using a material that is resistant to etching of the second thin film. forming a protective mask pattern, then etching the second thin film using the mask pattern; and finally,
A thin film processing method comprising forming a patterned second thin film on a substrate by removing a first thin film and a mask pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14891884A JPS6127638A (en) | 1984-07-18 | 1984-07-18 | Thin film processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14891884A JPS6127638A (en) | 1984-07-18 | 1984-07-18 | Thin film processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6127638A JPS6127638A (en) | 1986-02-07 |
| JPH0544827B2 true JPH0544827B2 (en) | 1993-07-07 |
Family
ID=15463568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14891884A Granted JPS6127638A (en) | 1984-07-18 | 1984-07-18 | Thin film processing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6127638A (en) |
-
1984
- 1984-07-18 JP JP14891884A patent/JPS6127638A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6127638A (en) | 1986-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4440804A (en) | Lift-off process for fabricating self-aligned contacts | |
| JPH0544827B2 (en) | ||
| US3953266A (en) | Process for fabricating a semiconductor device | |
| JPS6251228A (en) | Manufacture of gallium-arsenide monolithic microwave integrated circuit | |
| JPS59141222A (en) | Manufacture of semiconductor device | |
| JP3349001B2 (en) | Metal film forming method | |
| US5352331A (en) | Cermet etch technique for integrated circuits | |
| US3551176A (en) | Method for providing holes in glass | |
| JPS59104523A (en) | Production of infrared-ray detector | |
| JPH0230748A (en) | Formation of fine pattern | |
| JPS62149138A (en) | Manufacture of semiconductor device | |
| JPH01119042A (en) | Manufacture of semiconductor device | |
| JPH07273280A (en) | Formation method of thin-film pattern | |
| JPS5984550A (en) | Manufacture of semiconductor device | |
| JP2912002B2 (en) | Method for manufacturing semiconductor device | |
| JPH01298740A (en) | Semiconductor device | |
| JPH03239331A (en) | Manufacture of semiconductor device | |
| JPS59211232A (en) | Fabrication of metal layer pattern in semiconductor device | |
| JPH05832A (en) | Method for etching vitreous material | |
| JPS63312645A (en) | Manufacture of semiconductor device | |
| JPH03268325A (en) | Semiconductor device | |
| JPS6193629A (en) | Manufacture of semiconductor device | |
| JPS63314852A (en) | Manufacture of semiconductor device | |
| JPS61256729A (en) | Formation of conductor pattern | |
| JPS6032203A (en) | Method of patterning transparent thin film |