JPH054374A - Printing head - Google Patents
Printing headInfo
- Publication number
- JPH054374A JPH054374A JP14844591A JP14844591A JPH054374A JP H054374 A JPH054374 A JP H054374A JP 14844591 A JP14844591 A JP 14844591A JP 14844591 A JP14844591 A JP 14844591A JP H054374 A JPH054374 A JP H054374A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting diode
- back surface
- emitting element
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Dot-Matrix Printers And Others (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Facsimile Heads (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、フアクシミリやプリン
タ等の記録装置の光源として使用されるＬＥＤプリント
ヘツドの構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an LED print head used as a light source for recording devices such as facsimiles and printers.
【０００２】[0002]
【従来の技術】図４〜７は、例えばＡ４サイズ３００ｄ
ｐｉの場合のプリントヘツドの従来例を示したものであ
る。4 to 7 show, for example, an A4 size 300d.
9 shows a conventional example of a print head in the case of pi.
【０００３】図４は電気回路図であり、処理回路１は導
体パターン２を介して駆動用ＩＣ３に印字データ信号を
導出し、駆動用ＩＣ３から個別信号ラインＣ１〜Ｃ６４
を介して各発光素子アレイＬＡ１〜ＬＡ４０の各発光ダ
イオード素子ＬＥＤ１〜ＬＥＤ６４に印字データが送ら
れる。FIG. 4 is an electric circuit diagram, in which the processing circuit 1 derives a print data signal to the driving IC 3 via the conductor pattern 2 and the individual signal lines C1 to C64 from the driving IC 3 are outputted.
The print data is sent to the respective light emitting diode elements LED1 to LED64 of the respective light emitting element arrays LA1 to LA40 via.
【０００４】また、処理回路１は導体パターン４を介し
て共通信号電極Ｖｃ１〜Ｖｃ４０にストローブ信号を導
出し、各発光ダイオードアレイＬＡ１〜ＬＡ４０の裏面
の共通信号電極Ｖａ１〜Ｖａ４０にストローブ信号が送
られる。このように処理回路１により、各発光ダイオー
ドアレイＬＡ１〜ＬＡ４０を発光させている。The processing circuit 1 also derives a strobe signal to the common signal electrodes Vc1 to Vc40 via the conductor pattern 4, and sends the strobe signal to the common signal electrodes Va1 to Va40 on the back surface of each of the light emitting diode arrays LA1 to LA40. .. In this way, the processing circuit 1 causes each of the light emitting diode arrays LA1 to LA40 to emit light.
【０００５】次に、プリントヘツドの構造について図５
〜図７により説明する。Next, the structure of the print head is shown in FIG.
~ It demonstrates by FIG.
【０００６】図５は従来のＬＥＤプリントヘツドの斜視
図、図６は同じくその個別信号ラインＣ１〜Ｃ６４を中
心に示す平面図、図７は同じく一部破断正面図である。FIG. 5 is a perspective view of a conventional LED printhead, FIG. 6 is a plan view mainly showing the individual signal lines C1 to C64 thereof, and FIG. 7 is a partially cutaway front view thereof.
【０００７】実装基板Ａ１は、図５〜７の如く、セラミ
ツクおよびガラス等の電気絶縁材料から成り、その表面
に個別信号ラインＣ１〜Ｃ６４がクランク状に被膜形成
されている。該実装基板Ａ１の個別信号ラインＣ１〜Ｃ
６４を含む奥側半分の上面には電気絶縁層５が積層さ
れ、さらに電気絶縁層５の上面にはアレイ搭載用の共通
信号電極Ｖｃ１〜Ｖｃ４０が一列に順次形成されてい
る。As shown in FIGS. 5 to 7, the mounting board A1 is made of an electrically insulating material such as ceramics and glass, and individual signal lines C1 to C64 are formed on the surface thereof in a crank shape. Individual signal lines C1 to C of the mounting board A1
The electric insulating layer 5 is stacked on the upper surface of the back half including 64, and the common signal electrodes Vc1 to Vc40 for mounting the array are sequentially formed in a line on the upper surface of the electric insulating layer 5.
【０００８】共通信号電極Ｖｃ１〜Ｖｃ４０上には、図
５，７の如く、個別的に発光ダイオードアレイＬＡ１〜
ＬＡ４０が導電性接着剤６により接続され、この発光ダ
イオードアレイ裏面の共通裏面電極Ｖａ１〜Ｖａ４０
は、各発光ダイオードアレイＬＡ１〜ＬＡ４０の各発光
ダイオード素子ＬＥＤ１〜ＬＥＤ６４に電流を流して発
光させるための一方の端子として働く。On the common signal electrodes Vc1 to Vc40, the light emitting diode arrays LA1 to LA1 are individually provided as shown in FIGS.
The LA 40 is connected by the conductive adhesive 6, and the common back surface electrodes Va1 to Va40 on the back surface of the light emitting diode array.
Serves as one terminal for causing a current to flow through each of the light emitting diode elements LED1 to LED64 of each of the light emitting diode arrays LA1 to LA40 to emit light.
【０００９】発光ダイオード素子ＬＥＤ１〜ＬＥＤ６４
は各発光ダイオードアレイＬＡ１〜ＬＡ４０上に直線上
に配列されており、合計２５６０個の発光ダイオード素
子が使用される。Light emitting diode elements LED1 to LED64
Are arranged in a straight line on each of the light emitting diode arrays LA1 to LA40, and a total of 2560 light emitting diode elements are used.
【００１０】個別信号ラインＣ１〜Ｃ６４および共通信
号電極Ｖｃ１〜Ｖｃ４０は、アルミニウムおよび銅等の
材料からなり、蒸着またはスパツタリング等の薄膜手法
あるいはスクリーン印刷等の厚膜手法によつて形成され
ている。The individual signal lines C1 to C64 and the common signal electrodes Vc1 to Vc40 are made of a material such as aluminum and copper, and are formed by a thin film method such as vapor deposition or sputtering or a thick film method such as screen printing.
【００１１】個別信号ラインＣ１〜Ｃ６４は駆動用ＩＣ
３の出力端子Ｂ１〜Ｂ６４に個別的にアルミニウムおよ
び金等から成るボンデイングワイヤ７によつて接続され
る。発光ダイオード素子ＬＥＤ１〜ＬＥＤ６４には、図
５，６の如く、個別端子８が設けられ、個別信号ライン
Ｃ１〜Ｃ６４にアルミニウム、金等から成るボンデイン
グワイヤ９により個別的に接続される。The individual signal lines C1 to C64 are driving ICs.
The three output terminals B1 to B64 are individually connected by bonding wires 7 made of aluminum and gold. The light emitting diode elements LED1 to LED64 are provided with individual terminals 8 as shown in FIGS. 5 and 6, and are individually connected to the individual signal lines C1 to C64 by bonding wires 9 made of aluminum, gold or the like.
【００１２】これによつて、図５，６の如く、例えば発
光ダイオードアレイＬＡ１，ＬＡ２における発光ダイオ
ード素子ＬＥＤ１とＬＥＤ６４とがラインＣ１を介して
接続され、発光ダイオード素子ＬＥＤ２とＬＥＤ６３と
がラインＣ２を介して接続され、同様にして発光ダイオ
ード素子ＬＥＤ６４とＬＥＤ１とがラインＣ６４を介し
て接続される。Accordingly, as shown in FIGS. 5 and 6, for example, the light emitting diode elements LED1 and LED64 in the light emitting diode arrays LA1 and LA2 are connected via the line C1, and the light emitting diode elements LED2 and LED63 are connected to the line C2. Similarly, the light emitting diode elements LED64 and LED1 are connected via the line C64.
【００１３】以上のような構成で使用するダイナミツク
駆動方式のＬＥＤプリントヘツドにおいて、図５，７の
如く、従来では先に述べたように発光ダイオードアレイ
裏面の共通信号電極Ｖａ１〜Ｖａ４０と共通信号電極Ｖ
ｃ１〜Ｖｃ４０の接続を導電性接着剤６を用いて行つて
いた。As shown in FIGS. 5 and 7, in the LED drive head of the dynamic drive type used in the above-mentioned structure, the common signal electrodes Va1 to Va40 and the common signal electrodes on the rear surface of the light emitting diode array are conventionally used as described above. V
The conductive adhesive 6 was used to connect c1 to Vc40.
【００１４】なお、図５中、８ａは各発光ダイオード素
子ＬＥＤ１〜ＬＥＤ６４と個別電極８とを結線する導
体、図７中、３ａは駆動用ＩＣ３を実装基板Ａ１に接着
する非導電性接着剤である。In FIG. 5, 8a is a conductor for connecting the light emitting diode elements LED1 to LED64 and the individual electrode 8, and 3a in FIG. 7 is a non-conductive adhesive for bonding the driving IC 3 to the mounting substrate A1. is there.
【００１５】[0015]
【発明が解決しようとする課題】しかしながら、一般に
各発光ダイオードアレイＬＡ１〜ＬＡ４０を接近して配
置する必要があるため、従来の方法では、導電性接着剤
６がはみ出して隣の導電性接着剤６と接触し、隣合う共
通信号電極同士が接続されてしまう。そうすると、本
来、処理回路１の選択にて発光ダイオードアレイＬＡ１
の裏面の共通裏面電力Ｖａ１のみにストローブ信号が導
出されるはずが、隣の発光ダイオードアレイＬＡ２の共
通裏面電極Ｖａ２にも導出され、誤動作する問題があつ
た。However, since it is generally necessary to arrange the light emitting diode arrays LA1 to LA40 close to each other, in the conventional method, the conductive adhesive 6 protrudes and the adjacent conductive adhesive 6 is formed. And the adjacent common signal electrodes are connected to each other. Then, the light emitting diode array LA1 is originally selected by the processing circuit 1.
Although the strobe signal should be derived only to the common back surface power Va1 on the back surface of the above, there is a problem that it is also derived to the common back surface electrode Va2 of the adjacent light emitting diode array LA2.
【００１６】また、導電性接着剤６のはみ出しを防止す
るために発光ダイオードアレイＬＡ１〜ＬＡ４０の裏面
のＶａ１〜Ｖａ４０の中央部のみ導電性接着剤６を付け
る方法も考えられるが、アレイＬＡ１〜ＬＡ４０の接着
面積が少なくなり、超音波ボンデイングを行う際に基板
Ａ１との間で超音波伝導が悪くなる。また、アレイＬＡ
１〜ＬＡ４０が基板Ａ１に対して不安定となる。これら
のことから、ボンデイングワイヤ９のボンデイング性が
劣化する問題があつた。In order to prevent the conductive adhesive 6 from squeezing out, a method may be considered in which the conductive adhesive 6 is attached only to the central portions of the back surfaces Va1 to Va40 of the light emitting diode arrays LA1 to LA40, but the arrays LA1 to LA40 are also included. The area of adhesion is reduced, and the ultrasonic conduction between the substrate A1 and the substrate A1 deteriorates during ultrasonic bonding. In addition, the array LA
1 to LA 40 are unstable with respect to the substrate A 1. For these reasons, there is a problem that the bondability of the bonding wire 9 deteriorates.
【００１７】本発明は、上記に鑑み、発光ダイオードア
レイの接着面積を減らさずに各アレイ間の誤動作を防止
し得るプリントヘツドの提供を目的とする。In view of the above, it is an object of the present invention to provide a print head capable of preventing malfunction between the arrays without reducing the bonding area of the light emitting diode array.
【００１８】[0018]
【課題を解決するための手段】本発明による課題解決手
段は、図１〜３の如く、実装基板Ａ１上に、複数個の発
光素子アレイＬＡ１〜ＬＡ４０と、導体パターン２とを
有し、各発光素子アレイＬＡ１〜ＬＡ４０の表面に、複
数個の発光素子ＬＥＤ１〜ＬＥＤ６４と、該発光素子Ｌ
ＥＤ１〜ＬＥＤ６４に対応する個別端子８とが形成さ
れ、前記発光素子アレイＬＡ１〜ＬＡ４０の裏面に、共
通裏面端子Ｖａ１〜Ｖａ４０が形成され、前記導体パタ
ーン２は、各発光素子アレイＬＡ１〜ＬＡ４０をその共
通裏面端子Ｖａ１〜Ｖａ４０に接続して搭載する搭載用
配線４と、各発光素子アレイＬＡ１〜ＬＡ４０の各個別
端子８にボンデイングワイヤ９を介して結線される結線
用配線Ｃ１〜Ｃ６４とからなるプリントヘツドにおい
て、各発光素子アレイＬＡ１〜ＬＡ４０の共通裏面端子
Ｖａ１〜Ｖａ４０の中央部に導電性接着剤６が塗布さ
れ、共通裏面端子Ｖａ１〜Ｖａ４０の両端部に非導電性
接着剤１１が塗布され、これらが搭載用配線４に接着さ
れたものである。As shown in FIGS. 1 to 3, a problem solving means according to the present invention has a plurality of light emitting element arrays LA1 to LA40 and a conductor pattern 2 on a mounting substrate A1. A plurality of light emitting elements LED1 to LED64 and the light emitting element L are provided on the surface of the light emitting element arrays LA1 to LA40.
Individual terminals 8 corresponding to ED1 to LED64 are formed, common back surface terminals Va1 to Va40 are formed on the back surface of the light emitting element arrays LA1 to LA40, and the conductor pattern 2 includes the light emitting element arrays LA1 to LA40. A print consisting of mounting wirings 4 connected to the common back surface terminals Va1 to Va40 and mounted, and wirings C1 to C64 connected to the individual terminals 8 of the respective light emitting element arrays LA1 to LA40 via bonding wires 9. In the head, the conductive adhesive 6 is applied to the central portions of the common back surface terminals Va1 to Va40 of the respective light emitting element arrays LA1 to LA40, and the non-conductive adhesive 11 is applied to both ends of the common back surface terminals Va1 to Va40. These are adhered to the mounting wiring 4.
【００１９】[0019]
【作用】上記課題解決手段において、使用時に、発光ダ
イオードアレイＬＡ１〜ＬＡ４０内の発光ダイオードＬ
ＥＤ１〜ＬＥＤ６４に電源を供給して駆動する際、発光
ダイオードアレイＬＡ１〜ＬＡ４０の裏面の接着剤がは
み出して隣の発光ダイオードアレイＬＡ１〜ＬＡ４０の
接着剤に接触することがあるが、接着剤の両端部に非導
電性接着剤１１を使用しているので、これらの間が電気
的に絶縁され、隣接する搭載用配線４がシヨートして誤
動作するのを防止できる。In the above means for solving the problems, the light emitting diodes L in the light emitting diode arrays LA1 to LA40 are used at the time of use.
When power is supplied to the ED1 to LED64 to drive it, the adhesive on the back surface of the light emitting diode arrays LA1 to LA40 may squeeze out and come into contact with the adhesive on the adjacent light emitting diode arrays LA1 to LA40. Since the non-conductive adhesive 11 is used for the parts, it is possible to electrically insulate the non-conductive adhesive 11 from each other and prevent adjacent mounting wirings 4 from being shorted and malfunctioning.
【００２０】[0020]
【実施例】以下、本発明の一実施例を図面に基づいて説
明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【００２１】図１は本発明の一実施例を示すプリントヘ
ツドの斜視図、図２は同じくその個別信号ラインを中心
に示す平面図、図３は同じく一部破断正面図である。FIG. 1 is a perspective view of a print head showing an embodiment of the present invention, FIG. 2 is a plan view showing the individual signal lines thereof as a center, and FIG. 3 is a partially cutaway front view.
【００２２】なお、図４〜図７に示した従来技術と同一
機能部品については同一符号を付している。The same functional parts as those in the prior art shown in FIGS. 4 to 7 are designated by the same reference numerals.
【００２３】図示の如く、本実施例のプリントヘツド
は、例えばＡ４サイズ、３００ｄｐｉのもので、その実
装基板Ａ１はセラミツクおよびガラス等の電気絶縁材料
から成り、その表面には導体パターン２としての結線用
配線（個別信号ライン）Ｃ１〜Ｃ６４が図２の如く、ク
ランク状に被膜形成されている。As shown in the figure, the print head of this embodiment is, for example, of A4 size, 300 dpi, and its mounting substrate A1 is made of an electrically insulating material such as ceramics and glass, and its surface is connected with a conductor pattern 2 Wirings (individual signal lines) C1 to C64 are formed in a crank-like film as shown in FIG.
【００２４】該個別信号ラインＣ１〜Ｃ６４は、ボンデ
イングワイヤ７にて駆動用ＩＣ３の出力端子Ｂ１〜Ｂ６
４に個別的に接続される。The individual signal lines C1 to C64 are connected to the output terminals B1 to B6 of the driving IC 3 by the bonding wire 7.
4 individually connected.
【００２５】実装基板Ａ１の個別信号ラインＣ１〜Ｃ６
４を含む奥側半分上面には、図１，３の如く、従来と同
様、電気絶縁層５と、搭載ヘツド（共通信号電極）Ｖｃ
１〜Ｖｃ４０を有する導体パターン２としての搭載用配
線４が順次形成されている。Individual signal lines C1 to C6 of the mounting board A1
As shown in FIGS. 1 and 3, the upper surface of the back half including the electrical insulating layer 5 and the mounting head (common signal electrode) Vc
The mounting wiring 4 as the conductor pattern 2 having 1 to Vc40 is sequentially formed.
【００２６】ここで、個別信号ラインＣ１〜Ｃ６４と、
前記共通信号電極Ｖｃ１〜Ｖｃ４０を含む搭載用配線４
とは、アルミニウムおよび銅等の材料からなり、蒸着ま
たはスパツタリング等の薄膜手法あるいはスクリーン印
刷等の厚膜手法によつて夫々形成されている。Here, the individual signal lines C1 to C64,
Mounting wiring 4 including the common signal electrodes Vc1 to Vc40
Is made of a material such as aluminum and copper, and is formed by a thin film method such as vapor deposition or sputtering or a thick film method such as screen printing.
【００２７】前記共通信号電極Ｖｃ１〜Ｖｃ４０上に
は、個別的に発光素子アレイ（発光ダイオードアレイ）
ＬＡ１〜ＬＡ４０が搭載されている。Light emitting element arrays (light emitting diode arrays) are individually provided on the common signal electrodes Vc1 to Vc40.
LA1 to LA40 are mounted.
【００２８】該発光ダイオードアレイＬＡ１〜ＬＡ４０
の表面には、６４個の発光素子（発光ダイオード）ＬＥ
Ｄ１〜ＬＥＤ６４が直線上に配列され、４０個の発光ダ
イオードアレイＬＡ１〜ＬＡ４０を配置することにより
合計２５６０個の点光源が直線配置される。該各発光ダ
イオードＬＥＤ１〜ＬＥＤ６４には、図１の如く、これ
に対応する個別端子８が形成されている。該個別端子８
は、個別信号ラインＣ１〜Ｃ６４にアルミニウム、金等
から成るボンデイングワイヤ９により個別的に接続され
る。The light emitting diode arrays LA1 to LA40
There are 64 light emitting elements (light emitting diodes) LE on the surface of the
The D1 to LED 64 are arranged in a straight line, and by disposing 40 light emitting diode arrays LA1 to LA40, a total of 2560 point light sources are arranged in a straight line. As shown in FIG. 1, individual terminals 8 corresponding to the respective light emitting diodes LED1 to LED64 are formed. The individual terminal 8
Are individually connected to the individual signal lines C1 to C64 by a bonding wire 9 made of aluminum, gold or the like.
【００２９】これによつて、例えば発光ダイオードアレ
イＬＡ１，ＬＡ２における発光ダイオード素子ＬＥＤ１
とＬＥＤ６４とがラインＣ１を介して接続され、発光ダ
イオード素子ＬＥＤ２とＬＥＤ６３とがラインＣ２を介
して接続され、同様にして発光ダイオード素子ＬＥＤ６
４とＬＥＤ１とがラインＣ６４を介して接続される。Accordingly, for example, the light emitting diode element LED1 in the light emitting diode arrays LA1 and LA2.
And the LED 64 are connected via the line C1, the light emitting diode element LED2 and the LED 63 are connected via the line C2, and similarly, the light emitting diode element LED6
4 and LED1 are connected via line C64.
【００３０】一方、発光ダイオードアレイＬＡ１〜ＬＡ
４０の裏面には、単一の共通裏面端子Ｖａ１〜Ｖａ４０
が形成されている。該共通裏面端子Ｖａ１〜Ｖａ４０は
各発光ダイオード素子ＬＥＤ１〜ＬＥＤ６４に電流を流
して発光させるための一方の端子として働く。On the other hand, the light emitting diode arrays LA1 to LA
40 has a single common back surface terminal Va1 to Va40 on its back surface.
Are formed. The common back surface terminals Va1 to Va40 serve as one terminal for passing a current through each of the light emitting diode elements LED1 to LED64 to emit light.
【００３１】そして、該共通裏面端子Ｖａ１〜Ｖａ４０
の中央部には銀の粉末を混入したエポキシ系樹脂（銀ペ
ースト）等の導電性接着剤６が塗布され、共通裏面端子
Ｖａ１〜Ｖａ４０の両端部にはエポキシ系樹脂等の非導
電性接着剤１１が塗布されており、これらが前記搭載用
配線４の共通信号電極Ｖｃ１〜Ｖｃ４０に接着されてい
る。Then, the common back surface terminals Va1 to Va40
A conductive adhesive 6 such as an epoxy resin (silver paste) mixed with silver powder is applied to the central portion of the common back surface terminals Va1 to Va40, and a non-conductive adhesive such as an epoxy resin is applied to both ends of the common back surface terminals Va1 to Va40. 11 is applied and these are adhered to the common signal electrodes Vc1 to Vc40 of the mounting wiring 4.
【００３２】上記構成のプリントヘツドにおいて、使用
時には、処理回路（図４参照）にて搭載用配線４を介し
て発光ダイオードアレイＬＡ１〜ＬＡ４０を選択すると
共に、駆動用ＩＣ３にて発光ダイオードアレイＬＡ１〜
ＬＡ４０内の発光ダイオードＬＥＤ１〜ＬＥＤ６４を時
分割駆動する。When the printed head having the above-mentioned structure is used, the processing circuit (see FIG. 4) selects the light emitting diode arrays LA1 to LA40 via the mounting wiring 4 and the driving IC 3 selects the light emitting diode arrays LA1 to LA1.
The light emitting diodes LED1 to LED64 in the LA 40 are time-division driven.
【００３３】この際、接着剤の両端部に非導電性接着剤
１１を使用しているので、これらの間に電気的絶縁性を
保ち得、隣接する共通信号電極Ｖｃ１〜Ｖｃ４０がシヨ
ートして誤動作するのを防止できる。At this time, since the non-conductive adhesive 11 is used at both ends of the adhesive, electrical insulation can be maintained between them, and the adjacent common signal electrodes Vc1 to Vc40 are shorted and malfunction. Can be prevented.
【００３４】また、発光ダイオードアレイＬＡ１〜ＬＡ
４０の裏面の中央部のみ接着剤を設けるのに比べて、発
光ダイオードアレイＬＡ１〜ＬＡ４０の搭載ヘツドＶｃ
１〜Ｖｃ４０への接着面積を大きく確保でき、超音波ボ
ンデイングの際の超音波伝導を良好に維持できると共に
発光ダイオードアレイＬＡ１〜ＬＡ４０を安定化させて
ボンデイングワイヤ９のボンデイング性を確保できる。Further, the light emitting diode arrays LA1 to LA
As compared with the case where an adhesive is provided only on the central portion of the back surface of 40, the mounting head Vc of the light emitting diode arrays LA1 to LA40 is mounted.
It is possible to secure a large bonding area to 1 to Vc40, to maintain good ultrasonic conduction during ultrasonic bonding, and to stabilize the light emitting diode arrays LA1 to LA40 to ensure the bondability of the bonding wire 9.
【００３５】なお、本発明は、上記実施例に限定される
ものではなく、本発明の範囲内で上記実施例に多くの修
正および変更を加え得ることは勿論である。The present invention is not limited to the above embodiment, and it goes without saying that many modifications and changes can be made to the above embodiment within the scope of the present invention.
【００３６】例えば、上記実施例においては、Ａ４サイ
ズ３００ｄｐｉのＬＥＤプリントヘツドについて説明し
たが、本発明は、Ａ４幅以外のプリントヘツドにも、３
００ｄｐｉ以外の解像度のプリントヘツドにも、またア
ノードコモンタイプのＬＥＤアレイチツプを使用したプ
リントヘツドにも適用できる。For example, in the above embodiment, the LED print head of A4 size 300 dpi has been described, but the present invention is applicable to print heads other than A4 width.
The present invention can be applied to a printhead having a resolution other than 00 dpi and also to a printhead using a common anode type LED array chip.
【００３７】[0037]
【発明の効果】以上の説明から明らかな通り、本発明に
よると、搭載用配線に接続する共通裏面端子の中央部に
導電性接着剤を塗布し、かつ共通裏面端子の両端部に非
導電性接着剤を塗布し、これらにより共通裏面端子を搭
載用配線に接着しているので、接着剤がはみ出して隣の
接着剤に接触しても電気的絶縁性を保ち得、隣接する搭
載用配線がシヨートして誤動作するのを防止できるとい
つた優れた効果がある。As is apparent from the above description, according to the present invention, a conductive adhesive is applied to the central portion of the common back surface terminal connected to the mounting wiring, and both ends of the common back surface terminal are non-conductive. Since an adhesive is applied and the common back surface terminal is adhered to the mounting wiring by these, the electrical insulation can be maintained even if the adhesive squeezes out and comes into contact with the adjacent adhesive. It has an excellent effect when it is possible to prevent malfunction due to short shot.
【図１】図１は本発明の一実施例を示すプリントヘツド
の斜視図である。FIG. 1 is a perspective view of a print head showing an embodiment of the present invention.
【図２】図２は同じくその個別信号ラインを中心に示す
平面図である。FIG. 2 is a plan view showing the individual signal line as a center.
【図３】図３は同じく一部破断正面図である。FIG. 3 is a partially cutaway front view of the same.
【図４】図４は一般的なプリントヘツドの電気回路図で
ある。FIG. 4 is an electric circuit diagram of a general printhead.
【図５】図５は従来のＬＥＤプリントヘツドの斜視図で
ある。FIG. 5 is a perspective view of a conventional LED printhead.
【図６】図６は同じくその個別信号ラインを中心に示す
平面図である。FIG. 6 is a plan view showing the individual signal line as a center.
【図７】図７は同じく一部破断正面図である。FIG. 7 is a partially cutaway front view of the same.
２ 導体パターン ４ 搭載用配線 ６ 導電性接着剤 ８ 個別端子 Ａ１ 実装基板 ＬＡ１〜ＬＡ４０ 発光素子アレイ ＬＥＤ１〜ＬＥＤ６４ 発光素子 Ｖａ１〜Ｖａ４０ 共通裏面端子 Ｖｃ１〜Ｖｃ４０ 共通信号電極 Ｃ１〜Ｃ６４ 結線用配線 2 conductor pattern 4 wiring for mounting 6 conductive adhesive 8 individual terminal A1 mounting board LA1 to LA40 light emitting element array LED1 to LED64 light emitting element Va1 to Va40 common back surface terminal Vc1 to Vc40 common signal electrode C1 to C64 wiring for wiring
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０４Ｎ 1/036 Ａ 9070−5Ｃ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display area H04N 1/036 A 9070-5C
Claims (1)
と、導体パターンとを有し、各発光素子アレイの表面
に、複数個の発光素子と、該発光素子に対応する個別端
子とが形成され、前記発光素子アレイの裏面に、共通裏
面端子が形成され、前記導体パターンは、各発光素子ア
レイをその共通裏面端子に接続して搭載する搭載用配線
と、各発光素子アレイの各個別端子にボンデイングワイ
ヤを介して結線される結線用配線とからなるプリントヘ
ツドにおいて、各発光素子アレイの共通裏面端子の中央
部に導電性接着剤が塗布され、共通裏面端子の両端部に
非導電性接着剤が塗布され、これらが搭載用配線に接着
されたことを特徴とするプリントヘツド。Claim: What is claimed is: 1. A mounting substrate having a plurality of light emitting element arrays and a conductor pattern, wherein each light emitting element array has a plurality of light emitting elements on the surface thereof. Corresponding individual terminals are formed, a common back surface terminal is formed on the back surface of the light emitting element array, and the conductor pattern includes mounting wiring for mounting each light emitting element array by connecting it to the common back surface terminal, In a printhead consisting of wiring for wiring that is connected to each individual terminal of the light emitting element array via a bonding wire, a conductive adhesive is applied to the central portion of the common back surface terminal of each light emitting element array, A printed head, characterized in that both ends are coated with a non-conductive adhesive and these are adhered to the mounting wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14844591A JPH054374A (en) | 1991-06-20 | 1991-06-20 | Printing head |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14844591A JPH054374A (en) | 1991-06-20 | 1991-06-20 | Printing head |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH054374A true JPH054374A (en) | 1993-01-14 |
Family
ID=15452958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14844591A Pending JPH054374A (en) | 1991-06-20 | 1991-06-20 | Printing head |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH054374A (en) |
-
1991
- 1991-06-20 JP JP14844591A patent/JPH054374A/en active Pending
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