JPH0543626U - Digital / analog converter - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a digital / analog converter of a PWM conversion system, in which a frequency of a reference clock necessary for forming a pulse width signal is generated without causing second harmonic distortion in an analog signal. The purpose is to reduce it to 1/2 of the conventional one. A pulse width signal forming circuit having a pulse width responsive to a value of input digital data based on a reference clock, and outputting a pulse width signal PWM1 whose pulse width end always matches the end of one conversion cycle. 1 and a pulse width signal that has a pulse width that responds to the complement value of the input digital data based on the reference clock and that outputs a pulse width signal PWM2 whose pulse width end always matches the end of the pulse width signal PWM1. Forming circuit 3, pulse width signals PWM1 and PWM2
And a LPF that removes high frequency components included in the output signal PWM3 of the subtraction circuit 4 that performs subtraction of
It is composed of 5.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a so-called PWM conversion type digital / analog converter which converts input digital data into a pulse width signal and removes high frequency components contained in the pulse width signal to obtain an analog signal.

[0002]

[Prior Art]

 Conventionally, the present applicant has proposed a digital / analog conversion method capable of canceling the second harmonic distortion contained in a pulse width signal by Japanese Patent Application No. 56-124586 (Japanese Patent Publication No. 62-53088).

A digital / analog conversion device to which this digital / analog conversion method is applied will be described with reference to FIG. This device is configured to convert 7-valued input digital data consisting of 001 (-3) to 111 (+3) represented by a 3-bit binary offset code into an analog signal ( The numbers in parentheses are decimal values of input digital data).

As shown in FIG. 23, the pulse width signal forming circuit 1 has a cycle of T / 16 when the input digital data is taken in in synchronization with the rising edge of the timing clock CK1 having a cycle T as shown in FIG. Based on the reference clock CK2, it has a pulse width corresponding to the value of the input digital data, and the center C1 of the pulse width outputs a pulse width signal PWM1 having a constant phase relationship from the beginning of one conversion cycle T. To do.

On the other hand, the complementation circuit 2 inverts each bit of the input digital data and outputs complement data obtained by adding 001. The input digital data is, for example, 111 (+3). 001 (-3) is output at the time of, and 101 (+1) is output at the time of 011 (-1). The pulse width signal forming circuit 2 has the same circuit configuration as the pulse width signal forming circuit 1, and when the complement data is taken in in synchronization with the rising edge of the timing clock CK1 as shown in FIG. , A pulse width signal PWM2 having a pulse width responsive to the complement value of the input digital data, and the center C2 of the pulse width thereof is always coincident with the center C1 of the pulse width signal PWM1. The figure shows the pulse width signal PWM2 output in response to the input digital data.

The subtracting circuit 4 performs the subtraction of the output pulse width signal PWM1 and the output pulse width signal PWM2, and the width center C3 thereof always has a constant phase relationship from the start end of one conversion cycle T as shown in FIG. Also, the waveform output in response to the plus and minus input digital data is centered around the waveform (zero level) output in response to the input digital data being 100 (0). It outputs a pulse width signal PWM 3 which has a symmetrical relationship with each other. Then, the low-pass filter (LPF) 5 removes the high frequency component contained in the pulse width signal PWM 3 to produce an analog signal and outputs it to the analog output terminal 6.

According to the above-mentioned digital / analog conversion circuit, the pulse width signal PWM3 output from the subtraction circuit 4 has a zero-level waveform output in response to the plus-side and minus-side input digital data. Since they have a symmetrical relationship with respect to each other, it is possible to obtain an analog signal without distortion from the analog output terminal 6 without including the second harmonic distortion component.

On the other hand, in recent years, in digital audio equipment such as a compact disc (CD) player and a digital audio tape (DAT) recorder, a 1-bit system has been adopted. Many digital / analog converters have been adopted. This device uses a sampling frequency (fs) of 44.1 kHz and a quantization of 16 bits of digital data obtained from a CD, for example, at 64 fs and 3 bits by an oversampling circuit and a noise shaping circuit. The data is converted into data, and the data is D / A converted by the above-mentioned PWM conversion type digital / analog conversion device.

[0009]

[Problems to be solved by the device]

 However, when trying to D / A convert 64 fs, 3 bit data by the above digital / analog converter, the reference clock necessary for forming the pulse width signal becomes a very high frequency of 1024 fs, and the reference clock becomes There was a problem that radiation of the clock into the device and its jitter component could not be ignored, and had a great impact on the sound quality of the analog signal.

[0010]

[Means for Solving the Problems]

 The present invention is a digital / analog converter intended to reduce the frequency of a reference clock to 1/2 of that of a conventional one, and has a pulse width corresponding to the value of input digital data based on the reference clock. , The first pulse width signal forming circuit that outputs the first pulse width signal whose pulse width end always matches the end of one conversion cycle, and responds to the complement value of the input digital data based on the reference clock. A second pulse width signal forming circuit that outputs a second pulse width signal having a pulse width that matches the end of the pulse width signal and the end of the pulse width that always matches the end of the first pulse width signal; And a second pulse width signal, and a subtraction circuit for subtracting the signal, and a filter circuit for removing the high frequency component contained in the output signal of the subtraction circuit and converting it into an analog signal.

[0011]

[Action]

 According to the present invention, the first pulse width signal forming circuit has a pulse width corresponding to the value of the input digital data based on the reference clock, and the end of the pulse width always coincides with the end of one conversion cycle. And outputs a first pulse width signal that On the other hand, the second pulse width signal forming circuit has a pulse width responsive to the complement value of the input digital data, and the second pulse whose pulse width end always coincides with the end of the first pulse width signal. Output the width signal. The subtraction circuit subtracts the first pulse width signal and the second pulse width signal, the width center of which has a constant phase relationship from the beginning of one conversion cycle T, and the plus side and the minus side. Waveforms output in response to the input digital data output third pulse width signals which are symmetrical with respect to the zero level. Then, the filter circuit removes the high frequency component contained in the third pulse width signal to obtain an analog signal.

[0012]

【Example】

 An embodiment of the device of the present invention will be described in detail below with reference to the drawings. The block diagram of the apparatus of this embodiment is the same as that of the conventional apparatus shown in FIG. 1, but the circuit configurations of the pulse signal forming circuits 1 and 3 shown in FIG. 1 are different. Hereinafter, one circuit example will be described with reference to FIG.

Input terminals 10 to 12 for inputting 3-bit digital data are respectively connected to preset terminals A to C of a counter 13 having a preset function. The output terminals QA to QC of the counter 13 are connected to the input of the NAND 14, and the output thereof is connected to the data terminal D of the D-FF 15.

On the other hand, the input terminal 16 for inputting the reference clock CK2 having a frequency of 1/2 of the conventional one is connected to the clock terminal CK of the D-FF 15 and also connected to the clock terminal CK of the counter 13 via the INV 17. ing. The input terminal 18 for inputting the timing clock CK 1 is connected to the load terminal LO of the counter 13 and the preset terminal PR of the D-FF 15 via the INV 19. The output terminal Q of the D-FF 15 is connected to its clear terminal CL, and its output terminal Q is connected to the output terminal 20. The counter 13 is set so that its operation counts up.

The operation of the pulse signal forming circuit having the above configuration will be described with reference to FIGS. 3 to 5 show timing charts when the digital data is 111 (+3), 100 (0) and 001 (-3), respectively. Further, in FIG. 3, only the timing clock CK1 and the reference clock CK2 are shown in FIG. 3, and the count value of the counter 13 is its decimal value.

The counter 13 presets the count value of the digital data input to the input terminals 10 to 12 in synchronization with the rising edge of the timing clock CK1, and synchronizes with the rising edge of the reference clock CK2 after presetting. Start counting up. On the other hand, the D-FF 15 takes in the "H" output of the NAND 14 in synchronism with the rising edge of the timing clock CK1, and sets its output terminals Q and Q to "H" and "L", respectively.

After that, when the count value of the counter 13 reaches the full count state of 111 (+3), the NAND 14 changes its output to “L”, and the D-FF 15 synchronizes with the next rising edge of the reference clock CK2. Then, the output terminal Q and the bar Q are changed to "L" and "H", respectively. Then, since the output terminal Q and the clear terminal CL are connected to each other, the D-FF 15 holds the state until the next timing clock CK1 rises.

Next, the operation of the entire digital / analog converter obtained by applying this pulse width signal forming circuit to the pulse width signal forming circuits 1 and 3 shown in FIG. 1 will be described.

When the pulse width signal forming circuit 1 takes in the input digital data in synchronization with the timing clock CK1 as shown in FIG. 6, the pulse width signal forming circuit 1 is based on the reference clock CK2 having a half the frequency of the conventional one. It outputs a pulse width signal PWM 1 having a pulse width corresponding to the value of the input digital data, and the end E1 of the pulse width always coincides with the end of one conversion cycle T.

On the other hand, when the pulse width signal forming circuit 2 takes in the complement data of the input digital data in synchronization with the timing clock CK1 as shown in FIG. 7, the input digital data is obtained based on the reference clock CK2. The pulse width signal PWM2 has a pulse width responsive to the complement value of the pulse width, and the end E2 of the pulse width always matches the end E1 of the pulse width signal PWM1.

The subtraction circuit 4 performs the subtraction between the pulse width signal PWM1 and the pulse width signal PWM2, and as shown in FIG. 8, the width center C4 thereof has a constant phase relationship from the beginning of one conversion cycle T. Further, the pulse width signal PW M3 in which the waveforms output in response to the plus side and minus side input digital data are symmetrical with respect to the zero level, respectively. Then, the LPF 5 removes the high frequency component contained in the pulse width signal PWM 3 to produce an analog signal and outputs it to the analog output terminal 6.

In the above embodiment, the same pulse width signal forming circuits 1 and 3 are used, and the complement data output from the complementing circuit 2 is input to the pulse width signal forming circuit 3. If the pulse width signal forming circuit 3 is, for example, the circuit shown in FIG. 9, the complementing circuit 2 can be omitted.

The pulse width signal forming circuit shown in FIG. 9 is obtained by modifying a part of the circuit shown in FIG. 2. In comparison with the circuit shown in FIG. 2, the output terminals QB and QC of the counter 13 are INV21, The difference is that it is connected to the NAND 14 via 22 and the operation of the counter 13 is set to count down. Since the other connections are the same as those of the circuit shown in FIG. 2, the same reference numerals are given and the description thereof will be omitted.

The operation will be described below with reference to FIGS. 10 to 12 show timing charts when the digital data is 111 (+3), 100 (0) and 001 (-3), respectively.

The counter 13 presets the count value of the digital data input to the input terminals 10 to 12 in synchronization with the rising edge of the timing clock CK1, and synchronizes with the rising edge of the reference clock CK2 after presetting. To start down counting. On the other hand, the D-FF 15 takes in the "H" output of the NAND 14 in synchronism with the rising edge of the timing clock CK1, and sets its output terminals Q and Q to "H" and "L", respectively.

After that, when the count value of the counter 13 becomes 001 (−3), the NAND 14 changes its output to “L”, and the D-FF 15 synchronizes with the next rising edge of the reference clock CK2. The output terminal Q and the bar Q are changed to "L" and "H", respectively. Then, since the output terminal Q and the clear terminal CL are connected to each other, the D-FF 15 holds the state until the next timing clock CK1 rises.

Further, in the pulse width signal forming circuits shown in FIGS. 2 and 9, the counter 13 inputs digital data to the input terminals 10 to 12 in synchronization with the rising edge of the timing clock CK1. Is preset to the count value, but the present invention is not limited to such a pulse width signal forming circuit.

Another example of such a circuit is shown in FIG. 13. Input terminals 10 to 12 for inputting 3-bit digital data are connected to one input of E-ORs 31 to 33, respectively. On the other hand, the preset terminals A to C of the counter 34 having the preset function are always set to "H", and the output terminals QA to QC are connected to the other inputs of the E-ORs 31 to 33, respectively. The counter 34 is set so that its operation counts down. The outputs of the E-ORs 31 to 33 are input to the OR 35, and the outputs are connected to the data terminal D of the D-FF 36.

On the other hand, the input terminal 16 for inputting the reference clock CK2 is connected to the clock terminal CK of the D-FF 36 and also to the clock terminal CK of the counter 34 via the INV 37. The input terminal 18 for inputting the timing clock CK1 is connected to the load LO of the counter 34 and the preset terminal P R of the D-FF 36 via the INV 38. The output terminal Q of the D-FF 36 is connected to its clear terminal CL, and its output terminal bar Q is connected to the output terminal 20.

The operation will be described below with reference to FIGS. 14 to 16 show timing charts when the digital data is 111 (+3), 100 (0) and 001 (-3), respectively.

The counter 34 presets its count value to 111 (+3) in synchronization with the rising edge of the timing clock CK1, and starts counting down in synchronization with the rising edge of the preset reference clock CK2. On the other hand, the D-FF 36 takes in the "H" output of the OR 35 in synchronization with the rising of the timing clock CK1 and sets its output terminals Q and Q to "H" and "L", respectively.

After that, when the count value of the counter 34 matches the digital data, the OR 35 changes its output to "L", and the D-FF 36 synchronizes with the next rising edge of the reference clock CK2. The output terminal Q and the bar Q are changed to "L" and "H", respectively. Then, since the output terminal Q and the clear terminal CL of the D-FF 36 are connected, the D-FF 36 holds the state until the next timing clock CK1 rises.

Further, also in the pulse width signal forming circuit described above, the complementing circuit 2 can be omitted by modifying a part of the circuit and using it for the pulse width signal forming circuit 3.

The pulse width signal forming circuit shown in FIG. 17 is different from the circuit shown in FIG. 13 in that although the preset terminal A of the counter 34 is set to “H”, the terminals B and C are always set to “L”. In addition, the operation is set to count up. Since the other connections are the same as those of the circuit shown in FIG. 13, the same reference numerals are given and the description thereof will be omitted.

The operation will be described below with reference to FIGS. 18 to 20 show timing charts when the digital data is 111 (+3), 100 (0) and 001 (-3), respectively.

The counter 34 presets its count value to 001 (-3) in synchronization with the rising edge of the timing clock CK1, and starts counting up in synchronization with the rising edge of the preset reference clock CK2. On the other hand, the D-FF 36 takes in the "H" output of the OR 35 in synchronization with the rising of the timing clock CK1 and sets its output terminals Q and Q to "H" and "L", respectively.

After that, when the count value of the counter 34 coincides with the digital data, the OR 35 changes its output to “L”, and the D-FF 36 synchronizes with the next rising edge of the reference clock CK 2. The output terminal Q and the bar Q are changed to "L" and "H", respectively. Then, since the output terminal Q and the clear terminal CL of the D-FF 36 are connected, the D-FF 36 holds the state until the next timing clock CK1 rises.

Further, although not shown, the pulse width signal forming circuit may be configured by using a ROM and a parallel / serial conversion circuit. In this case, the logic state of the pulse width signal output in response to digital data is stored in the ROM as data, and the data read from the ROM based on the timing clock CK1 is stored in the parallel / serial conversion circuit. A pulse width signal is formed by taking in and sequentially outputting based on the reference clock CK2.

Further, in the above-described device of the present invention, only the pulse width signals PWM1 and PWM2 output from the pulse width signal forming circuits 1 and 3 are used, but the Q outputs of the D-FFs 15 and 36, and the inversion thereof. External noise can be canceled and S / N can be further improved by using a signal.

An example of such a circuit is shown in FIG. 21, in which the pulse width signal PWM 1 output from the pulse width signal forming circuit 1 and the inverted signal buffer of the pulse width signal PWM 2 output from the pulse width signal forming circuit 2 are output. -PWM2 is added by the adder circuit 40, while the inverted signal bar PWM1 of the pulse width signal PWM1 output from the pulse width signal forming circuit 1 and the pulse width signal PWM2 output from the pulse width signal forming circuit 2 are added. It is added by the circuit 41. Then, the outputs of the adding circuits 40 and 41 are subtracted by the subtracting circuit 4, and the obtained pulse width signal PWM3 is output from the analog output terminal 6 via the LPF 5.

On the other hand, the configuration shown in FIG. 22 can also be adopted. The pulse width signal PWM1 output from the pulse width signal forming circuit 1 and its inverted signal bar PWM1 are subtracted by the subtracting circuit 42, while the pulse width signal PWM2 output from the pulse width signal forming circuit 3 and its inversion. The subtraction circuit 43 subtracts the signal bar PWM2. Then, the outputs of the subtraction circuits 42 and 43 are subtracted by the subtraction circuit 4, and the obtained pulse width signal P WM3 is output from the analog output terminal 6 via the LPF 5.

[0042]

[Effect of the device]

 As described above, according to the device of the present invention, the frequency of the reference clock can be halved as compared with the conventional one, so that the radiation of the reference clock into the device is reduced, and the analog signal due to the jitter included in the reference clock is reduced. The influence is reduced and the sound quality of the analog signal can be improved. On the other hand, when the frequency of the reference clock is the same as the conventional one, the sampling period T becomes half that of the conventional one, so that the sampling frequency of the input digital data can be doubled and a high S / N ratio can be obtained. Can be secured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a conventional device and a device of the present invention.

FIG. 2 is a circuit diagram of an embodiment of a pulse width signal forming circuit used in the device of the present invention.

FIG. 3 is a circuit diagram of a pulse width signal forming circuit shown in FIG.
It is a timing chart when digital data of (+3) is input.

4 is a circuit diagram of the pulse width signal forming circuit shown in FIG.
This is a timing chart when digital data (0) is input.

5 is a circuit diagram of the pulse width signal forming circuit shown in FIG.
It is a timing chart when the digital data of (-3) is input.

FIG. 6 shows that the device of the present invention has 001 (−3) to 111 (+3).
3 is a timing chart showing a waveform change of the pulse width signal PWM1 obtained from the pulse width signal forming circuit 1 when the digital data of FIG.

FIG. 7: 001 (-3) to 111 (+3) in the device of the present invention
2 is a timing chart showing a waveform change of the pulse width signal PWM2 obtained from the pulse width signal forming circuit 3 when the digital data of FIG.

FIG. 8 shows the device of the present invention with 001 (−3) to 111 (+3).
2 is a timing chart showing a waveform change of the pulse width signal PWM3 obtained from the subtraction circuit 4 when the digital data of FIG.

FIG. 9 is a circuit diagram of another embodiment of the pulse width signal forming circuit used in the device of the present invention.

FIG. 10 is a circuit diagram of the pulse width signal forming circuit shown in FIG.
This is a timing chart when 1 (+3) digital data is input.

FIG. 11 is a circuit diagram of a pulse width signal forming circuit shown in FIG.
This is a timing chart when 0 (0) digital data is input.

12 is a circuit diagram of the pulse width signal forming circuit shown in FIG.
This is a timing chart when 1 (-3) digital data is input.

FIG. 13 is a circuit diagram of another embodiment of the pulse width signal forming circuit used in the device of the present invention.

FIG. 14 is a circuit diagram of the pulse width signal forming circuit shown in FIG.
It is a timing chart when 11 (+3) digital data is input.

FIG. 15 is a circuit diagram showing the pulse width signal forming circuit shown in FIG.
This is a timing chart when digital data of 00 (0) is input.

FIG. 16 is a circuit diagram showing that the pulse width signal forming circuit shown in FIG.
This is a timing chart when the digital data of 01 (-3) is input.

FIG. 17 is a circuit diagram of another embodiment of the pulse width signal forming circuit used in the device of the present invention.

FIG. 18 is a circuit diagram showing the pulse width signal forming circuit shown in FIG.
It is a timing chart when 11 (+3) digital data is input.

FIG. 19 is a circuit diagram of the pulse width signal forming circuit shown in FIG.
This is a timing chart when digital data of 00 (0) is input.

20 is a circuit diagram showing a pulse width signal forming circuit shown in FIG.
This is a timing chart when the digital data of 01 (-3) is input.

FIG. 21 is a block diagram showing another embodiment of the device of the present invention.

FIG. 22 is a block diagram showing another embodiment of the device of the present invention.

FIG. 23 shows the conventional device with 001 (−3) to 111 (+3).
3 is a timing chart showing a waveform change of the pulse width signal PWM1 obtained from the pulse width signal forming circuit 1 when the digital data of FIG.

FIG. 24 shows 001 (−3) to 111 (+3) in the conventional device.
2 is a timing chart showing a waveform change of the pulse width signal PWM2 obtained from the pulse width signal forming circuit 3 when the digital data of FIG.

FIG. 25 shows the conventional device with 001 (−3) to 111 (+3).
2 is a timing chart showing a waveform change of the pulse width signal PWM3 obtained from the subtraction circuit 4 when the digital data of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 pulse width signal formation circuit 2 complementation circuit 3 pulse width signal formation circuit 4 subtraction circuit 5 low-pass filter 40 addition circuit 41 addition circuit 42 subtraction circuit 43 subtraction circuit

Claims (6)

[Scope of utility model registration request] 1. A first pulse width signal having a pulse width responsive to a value of input digital data, the end of the pulse width always matching the end of one conversion cycle, is output based on a reference clock. A first pulse width signal forming circuit having a pulse width responsive to the complement value of the input digital data based on the reference clock, and the end of the pulse width is the end of the first pulse width signal. A second pulse width signal forming circuit that outputs a second pulse width signal that always matches, a subtraction circuit that subtracts the first pulse width signal and the second pulse width signal, and an output of the subtraction circuit A digital / analog conversion device comprising a filter circuit that removes high-frequency components contained in a signal and converts it into an analog signal. 2. A first pulse width signal having a pulse width responsive to the value of input digital data, the end of the pulse width always matching the end of one conversion cycle, is output based on a reference clock. A first pulse width signal forming circuit having a pulse width responsive to the complement value of the input digital data based on the reference clock, and the end of the pulse width is the end of the first pulse width signal. A second pulse width signal forming circuit that outputs a second pulse width signal that is an inversion of the pulse width signal that always matches; and a subtraction circuit that subtracts the first pulse width signal and the second pulse width signal. A digital / analog converter comprising a filter circuit which removes a high frequency component contained in the output signal of the subtraction circuit and converts it into an analog signal. 3. A first pulse width signal having a pulse width responsive to the value of the input digital data based on the reference clock, and the end of the pulse width always coincides with the end of one conversion period is output. A first pulse width signal forming circuit having a pulse width responsive to the complement value of the input digital data based on the reference clock, and the end of the pulse width is the end of the first pulse width signal. A second pulse width signal forming circuit that outputs a second pulse width signal that is an inversion of the pulse width signal that always matches; and an adder circuit that adds the first pulse width signal and the second pulse width signal. A digital / analog conversion device comprising a filter circuit that removes high-frequency components included in the output signal of the adder circuit to generate an analog signal. 4. A first pulse width signal which has a pulse width responsive to a value of input digital data and whose pulse width end always coincides with the end of one conversion period based on a reference clock. A first pulse width signal forming circuit which outputs a pulse width signal; and a pulse width which responds to a complement value of the input digital data based on the reference clock, and the end of the pulse width is the first pulse width signal. A second pulse width signal forming circuit for outputting a second pulse width signal which is an inversion of the pulse width signal which always coincides with the end of the pulse width signal, and the first pulse width signal and the second pulse width signal. A digital / analog converter comprising an adder circuit that performs addition and a filter circuit that removes a high-frequency component included in an output signal of the adder circuit and converts it into an analog signal. 5. A first pulse width signal having a pulse width responsive to a value of input digital data based on a reference clock, and an end of the pulse width always coincides with an end of one conversion period and its inversion. A first pulse width signal forming circuit for outputting a signal, and a pulse width responsive to the complement value of the input digital data based on the reference clock, the end of the pulse width having the first pulse width. A second pulse width signal forming circuit that outputs a second pulse width signal that always coincides with the end of the signal and its inverted signal, and addition of the first pulse width signal and the inverted signal of the second pulse width signal. A second adder circuit for adding the inversion signal of the first pulse width signal and the second pulse width signal, an output signal of the first adder circuit and the first adder circuit Subtract the output signal of the adder circuit of 2 A digital / analog converter comprising a subtraction circuit and a filter circuit which removes a high frequency component contained in the output signal of the subtraction circuit and converts it into an analog signal. 6. A first pulse width signal having a pulse width responsive to the value of input digital data based on a reference clock, and the end of the pulse width always coincides with the end of one conversion period and its inversion. A first pulse width signal forming circuit for outputting a signal, and a pulse width responsive to the complement value of the input digital data based on the reference clock, the end of the pulse width having the first pulse width. A second pulse width signal forming circuit that outputs a second pulse width signal that always matches the end of the signal and its inversion signal, and a first subtraction circuit that subtracts the first pulse width signal and its inversion signal. A second subtraction circuit for subtracting the second pulse width signal and its inverted signal, and a third subtraction circuit for subtracting the output signal of the first subtraction circuit from the output signal of the second subtraction circuit. Of the subtraction circuit and the third subtraction circuit A digital / analog conversion device comprising a filter circuit that removes high-frequency components contained in an output signal and converts it into an analog signal.