JPH0542856B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to an FM stereo demodulation method in an FM stereo receiver, in particular to an FM stereo demodulation method using sample and hold.
This article relates to an FM stereo demodulation method that performs stereo demodulation.

Conventional configuration and its problems In an FM stereo receiver, the frequency discriminator output, ie, the stereo composite signal S(t), when receiving stereo broadcasting, is as shown in equation (1).

S(t)=(L+R)+ _Psinωs /2t+(L-R) _sinωst ...(1) However, (L+R): Red signal (L-R) _sinωst : Sub signal _Psinωs /2t: Pilot Signal L: Left channel audio signal R: Right channel audio signal P: Pilot signal amplitude ω _s : Subcarrier angular frequency (=2π×38kHz) Separate left and right channel audio signals from the above stereo composite signal (stereo Currently, the switching method is the mainstream demodulation method.

This switching method extracts the pilot signal from the signal shown in equation (1), inputs it to a phase comparator that forms part of a PLL (phase locked loop), and generates a switching signal synchronized with the pilot signal in the PLL. The pilot signal component is removed from the signal shown in equation (1) using a trap circuit, etc., and the remaining signal is converted into the above switching signal (rectangular wave).
By switching, the audio signals are separated into left and right channels.

However, the above-mentioned conventional FM stereo demodulation method requires a trap circuit to remove the pilot signal from the stereo composite signal, and also has the disadvantage that it requires separation adjustment in principle and is difficult to integrate into an IC. Ta.

Purpose of the Invention The present invention eliminates the above-mentioned conventional drawbacks, and provides an FM stereo demodulation method that does not require a trap circuit, does not require separation adjustment in principle, and is easy to integrate into an IC. It is.

Structure of the Invention In order to achieve the above object, the present invention converts the stereo composite signal shown in equation (1) to t ₁ =2π/ω _s (2n+1/4) t ₂ =2π/ω _s (2n+5/4) t ₃ = 2π/ω _s (2n+3/4) t ₄ = 2π/ω _s (2n+7/4) Sample and hold the signal
S ₁ , S ₂ , S ₃ , S ₄ are obtained, a pilot signal component Pc is obtained from these signals S ₁ to _{S 4} , and from the signals S ₁ to S ₄ and the pilot signal component Pc, S ₁ ′=S ₁ − Pc S ₂ ′=S ₂ +Pc S ₃ ′=S ₃ −Pc S ₄ ′=S ₄ +Pc is obtained, and the above signal S ₁ ′ is converted to t=t ₂ (or t=t ₃ or t=
t ₄ ), and the above signal S ₂ ' is sampled and held alternately at t = t ₁ (or t ₌ t ₄ or t = t ₃ ) to obtain a left channel audio signal, and the above signal S ₃ ' is obtained. t
= t ₄ (or t = t ₂ or t = t ₁ ), and the above signal
The patent is for obtaining a right channel audio signal by sequentially and alternately sampling and holding S ₄ ' at t=t ₃ (or t=t ₁ or t=t ₂ ).

DESCRIPTION OF EMBODIMENTS First, the principle of the present invention will be explained. Said (1)
The stereo composite signal S(t) of the formula is expressed as: t ₁ =2π/ω _s (2n+1/4) ...(2) t ₂ =2π/ω _s (2n+5/4) ...(3) t ₃ =2π /ω _s (2n+3/4) ...(4) t ₄ =2π/ω _s (2n+7/4) ...(5) If you sample and hold each at the timing,
The outputs S ₁ , S ₂ , S ₃ , and S ₄ are as shown in equations (6), (7), (8), and (9), respectively. (However, the signal component with an angular frequency of ω _s /2 and its harmonic components are ignored.) S ₁ = 2L + P / √2 ... (6) S ₂ = 2L - P / √2 ... (7) S ₃ =2R+P/√2 ...(8) S ₄ =2R-P/√2 ...(9) Pilot signal component in the signal shown in equations (6) to (9)
Perform the following calculation to find Pc.

Pc = (S ₁ - _{S 2} + S ₃ - S ₄ )/4 = P/√2 ... (10) Pilot signal component Pc from the signals S ₁ to _{S 4}
In order to remove , perform the following calculation.

S ₁ ′=S ₁ −Pc=(2L+P/√2)−P/√2=2L……
(11) S ₂ ′=S ₂ +Pc=(2L−P/√2)+P/√2=2L……
(12) S ₃ ′=S ₃ −Pc=(2R+P/√2)−P/√2=2R……
(13) S ₄ ′=S ₄ +Pc=(2R−P/√2)+P/√2=2R……
(14) When the signals S ₁ ′ and S ₂ ′ shown in equations (11) and (12) above are sampled and held alternately at a 1/ _s period ( _s is the subcarrier frequency), the left channel audio signal is obtained, Furthermore, if the signals S ₃ ′ and S ₄ ′ shown in equations (13) and (14) are sampled and held alternately at a period of 1 _s , the audio signal of the right channel is obtained.

The generation of sample pulses for carrying out the various sample holds described above can be achieved by a method invented using a PLL when performing stereo demodulation using the conventional switching method, or by the method shown in Japanese Patent Publication No. 58-23983. It can be done by

Sip is calculated from equations (11) to (14) above.

Sip=S ₁ ′−S ₂ ′−S ₃ ′ ₊ S ₄ ′ =2L−2L−2R+2R =0 ……(15) From the above equation (15), if stereo separation is perfect, Sip
=0.

On the other hand, the sample hold timing is (2) to (5)
When the timing is advanced by △t from the timing shown in the formula, that is, t ₁ ′=2π/ω _s (2n+1/4)−△t ……(2)′ t ₂ ′=2π/ω _s (2n+5/4)− △t ……(3)′ t ₃ ′=2π/ω _s (2n+3/4)−△t ……(4)′ t ₄ ′=2π/ω _s (2n+7/4)−△t ……(5 )′, the sample and hold outputs are as follows.

S ₁ ′=(1+a ₁ )L+(1-a ₁ )R+P/√
2(a ₂ − a ₃ )……(6)′ S ₂ ′=(1+a ₁ )L+(1−a ₁ )R−P/√
2(a ₂ −a ₃ )……(7)′ S ₃ ′=(1−a ₁ )L+(1+a ₁ )R+P/√
2(a ₂ + a ₃ )……(8)′ S ₄ ′=(1−a ₁ )L+(1+a ₁ )R−P/√
2 (a ₂ + a ₃ )……(9)′ However, a ₁ = cos (ω _s・△t) a ₂ = cos (ω _s・△t/2) a ₃ = sin (ω _s・△t/ 2) As is clear from equations (6)' to (9)', if the sample and hold timing advances by △t, the signals S ₁ ', S which should be only the left channel audio signal except the pilot signal component ₂ ' contains the right channel audio signal, and signals _S3 ' and _S4 ', which should be only the right channel audio signal other than the pilot signal component, contain the left channel audio signal, so stereo separation is not complete. It disappears. In this case, Sip is Sip′=S ₁ ′−S ₂ ′−S ₃ ′+S ₄ ′=−2√2Pa ₃ <0
...(15)′ becomes.

Conversely, when the sample-hold timing is delayed by Δt from the timing shown in equations (2) to (5), the sample-and-hold outputs are as follows.

S ₁ ″=(1+a ₁ )L+(1-a ₁ )R+P/√
2(a ₂ + a ₃ )……(6)″S ₂ ″=(1+a ₁ )L+(1−a ₁ )R−P/√
2 (a ₂ + a ₃ )……(7)″S ₃ ″=(1−a ₁ )L+(1+a ₁ )R+P/√
2(a ₂ −a ₃ )……(8)″S ₄ ″=(1−a ₁ )L+(1+a ₁ )R−P/√
2(a ₂ − _{a 3} )...(9)″ As is clear from equations (6)″ and (9)″, if the sample and hold timing is delayed by △t, the left channel audio except the pilot signal component The right channel audio signal is included in the signals S ₁ ″ and S ₂ ″, which should be only signals, and the left channel audio signal is included in the signals S ₃ ″ and S ₄ ″, which should be only the right channel audio signal except for the pilot signal component. In this case, Sip″ is: Sip″=S ₁ ″−S ₂ ″−S ₃ ″+S ₄ ″=2√2Pa ₃ > 0
...(15)''.

From equations (15), (15)′, and (15)″ above, the Sip value is monitored and S
ip
If Sip is greater than 0, the sample hold timing is advanced, and if Sip is less than 0, it is delayed, and if control is performed so that Sip=0 at all times, complete stereo separation can be achieved.

An embodiment of the present invention will be described below with reference to the drawings.

In Fig. 1, 1 is a low-pass filter (LPF) for extracting only the stereo composite signal shown in equation (1) above from the frequency discriminator output, and 2 to 5 are sample and hold circuits. The hold circuits 2 to 5 receive a stereo composite signal (see Fig. 2a) which is the output of the low-pass filter 1.
(Refer to Figure 2a, however, the stereo composite signal is shown divided into a pilot signal and a main signal + sub signal.)
Sample hold (sampling complete, hold start) at the timing shown in equations (2) to (5) respectively.
Then, the signals S ₁ to S ₄ shown in equations (6) to (9) above (Fig. 2 f to
(see i) is output. 6 is a cancel signal generation circuit which inputs the outputs of the sample and hold circuits 2 to 5, performs the calculation (including integration operation) shown in equation (10) above, and outputs the pilot signal level Pc to be canceled; 7 is the cancel signal generator circuit described above; Sample hold circuit 2~
Input the output of 5 and sample hold pulse SP
1, SP2, SP3, SP4 and gate pulse GPL,
This is a PLL circuit that outputs GPR, and details of an example of this PLL circuit 7 are described in Japanese Patent Publication No. 58-23983. Note that the gate pulse GPL is outputted from a monostable multi-valve generator which is "H" for a certain period of time from the rising edge of the sample and hold pulses SP3 and SP4, and is "L" during the rest of the time.
It becomes “H” for a certain period of time from the rising edge of SP2, and
During other times, it is output from a monostable multivibrator which is "L".

8 is a difference circuit that subtracts the output Pc of the cancel signal generation circuit 6 from the output S ₁ of the sample hold circuit 2 and outputs the signal S ₁ ' shown in equation (11) above;
9 is a summation circuit that takes the sum of the output S ₂ of the sample and hold circuit 3 and the output Pc of the cancel signal generation circuit 6 and outputs the signal S ₂ ' shown in equation (12); 10 is the output S ₃ of the sample and hold circuit 4; 11 is a difference circuit which subtracts the output Pc of the cancel signal generation circuit 6 from and outputs the signal _{S3 '} shown in (13). , is a sum circuit that outputs the signal S ₄ ' shown in equation (14).

12 is a sample and hold circuit that alternately samples and holds the output S ₁ ' of the difference circuit 8 with a sample and hold pulse SP2, and the output S ₂ ' of the summation circuit 9 with a sample and hold pulse SP1 (see Fig. 2j);
Reference numeral 13 denotes a sample-hold circuit (see Fig. 2 k) that alternately samples and holds the output S ₃ ' of the difference circuit 10 with the sample-hold pulse SP4 and the output S ₄ ' of the summation circuit 11 with the sample-hold pulse SP3; is the output S _L of the sample hold circuit 12
is switched by the gate pulse GPL (see Figure 2 e) (GPL "H" and signal S _L are passed through, and the signal S L is "L").
1) Switching circuit that outputs the PAM signal of the left channel audio signal.
5 switches the output S _R of the sample and hold circuit 13 with the gate pulse GPR (see Figure 2 m) (when GPR is "H", the signal S _R is passed; when it is "L", the output is set to "0"). ) A switching circuit that outputs the P _AM signal of the right channel audio signal, 1
6 and 17 are switching circuits 14 and 15, respectively.
The low-pass filters 14 and 15 output a left channel audio signal and a right channel audio signal, respectively.

In the above embodiment, if some deterioration in the frequency characteristics of the left and right channel audio signal outputs is to be tolerated, the switching circuit 1 in FIG.
4 and 15, and the sample and hold circuit 12,
13 outputs are directly connected to low-pass filters 16 and 1, respectively.
7 may be entered.

In addition, in the above embodiment, the signal is expressed as shown in equation (10).
Although the pilot signal component Pc is obtained from S ₁ , S ₂ , S ₃ , and S ₄ , the pilot signal component Pc may be obtained from the signals S ₁ and _{S 2} or the signals S ₃ and S ₄ .

Further, in the above embodiment, the signal S ₁ ' is converted into a sample pulse in the sample hold circuit (SH5) 12.
SP2 alternately samples and holds the signal S ₂ ' with sample pulse SP1, and the sample hold circuit (SH6) 13 alternately samples and holds the signal S ₃ ' with sample pulse SP4 and the signal S ₄ ' with sample pulse SP3. However, the signal S ₁ ′ is the sample pulse SP
3 or SP4, the signal S ₂ ' is sampled pulse SP4 or
SP3, sample pulse SP2 or SP1, signal S ₃ '
The signal S ₄ ' may be sampled and held alternately with the sample pulse SP1 or SP2.

In addition, in the above embodiment, the sample hold circuit processes an analog signal, but it is converted into a digital signal and processed (A/D converted after sampling, then processed digitally, and returned to analog after stereo separation). It's also good.

FIG. 3 shows details of the PLL circuit 7 in the above embodiment. In FIG. 3, 18 is a difference circuit for obtaining the difference (S ₁ - _{S 2} ) between the output S ₁ of the sample and hold circuit ₂ and the output S 2 of the sample and hold circuit 3, and 19 is the output S ₃ of the sample and hold circuit 4. 20 is a difference circuit for obtaining the difference (S ₃ - _{S 4} ) between the output S ₄ of the sample and hold circuit 5, and 20 is the output of the difference circuit 18 (S ₁
−S ₂ ) difference between the outputs (S ₃ −S ₄ ) of the circuit 19 (S ₁ −
S ₂ −S ₃ +S ₄ ), and the output of this difference circuit 20 corresponds to the above-mentioned Sip.

21 is a loop filter that converts the output of the difference circuit 20 into a signal that controls the frequency and phase of a voltage-controlled oscillator (VCO) output signal, which will be described later; controlled voltage controlled oscillator (VCO),
23 is a monostable multivibrator (MM) whose output is "1" for a certain period of time from the rise of the output signal of VCO 22 and output is "0" during the rest of the time, and 24 is the input of the output of monostable multivibrator 23. A 2-bit counter 25 is a multiplexer whose output is controlled by the output condition of the counter 24, and when the two outputs of the counter 24 are "0" and "0", the multiplexer 25 is a monostable multivibrator. The output of 23 appears at terminal 0 and becomes the sample hold pulse SP1, and if the output of the counter 24 is "1" or "0", it appears at the output of terminal 1 and becomes the sample hold pulse SP3, and the output of the counter 24 becomes "0". ”, “1”, the output appears at terminal 2 and becomes the sample hold pulse SP2, and the output of the counter 24 becomes “1”,
In the case of "1", an output appears at terminal 3 and becomes a sample hold pulse SP4.

It is a monostable multivibrator that is "H" for a certain period of time from the rising edge of sample and hold pulses SP3 and SP4, and "L" during the rest of the time.
This monostable multivibrator 26 outputs a gate pulse GPL. Reference numeral 27 denotes a monostable multivibrator which becomes "H" for a certain period of time from the rising edges of the sample and hold pulses SP1 and SP2, and remains "L" during the rest of the time, and this monostable multivibrator 27 outputs a gate pulse GPR.

In the embodiment shown in FIGS. 1 and 3, sample and hold circuits 2 to 5, difference circuits 18, 19, 2
0, a loop filter 21, a VCO 22, a monostable multivibrator 23, a counter 24, and a multiplexer 25 constitute a PLL, and the sample and hold circuits 2 to 5 and difference circuits 18, 19, and 20 have the function of a phase comparator. .

Effects of the Invention According to the present invention, there is no need for a trap circuit for removing a pilot signal from a stereo composite signal, and there is no need to adjust the degree of separation, and there are advantages that it can be easily integrated into an IC.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a circuit implementing the FM stereo demodulation method in an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of the circuit shown in Fig. 1, and Fig. 3 is a block diagram of the PLL circuit of the same circuit. It is. 1...Low-pass filter, 2-5...Sample hold circuit, 6...Cancel signal generation circuit, 7...
...PLL circuit, 8...Difference circuit, 9...Sum circuit, 1
0...Difference circuit, 11...Sum circuit, 12, 13...
Sample hold circuit, 14, 15...Switching circuit, 16, 17...Low pass filter, 18,
19, 20... Difference circuit, 21... Loop filter, 22... Voltage controlled oscillator, 23... Monostable multivibrator, 24... Counter, 25...
Multiplexer, 26, 27...monostable multivibrator.

Claims (1)

[Claims] 1. Stereo composite signal S(t)=(L+R)
+Psinω _s /2t+(L-R)sinω ₃ t, t ₁ =2π/ω _s (2n+1/4) t ₂ =2π/ω _s (2n+5/4) t ₃ =2π/ω _s (2n+3/4) t ₄ =2π/ω _s (2n+7/4) However, Psinω _s /2t: Pilot signal L: Left channel audio signal R: Right channel audio signal ω _s : Subcarrier angular frequency n: 0, 1, 2, 3... ...The signals S ₁ , S ₂ , S ₃ , S ₄ are obtained by sampling and holding them separately at the timing, and the above-mentioned signals S ₁ , S ₂ , S ₃ , S ₄ are obtained.
pilot signal components than at least two of
Obtain Pc, and from the above signals S ₁ , S ₂ , S ₃ , S ₄ and Pc, S ₁ ′=S ₁ −Pc S ₂ ′=S ₂ +Pc S ₃ ′=S ₃ −Pc S ₄ ′=S ₄ +Pc and convert the above signal S ₁ ' to t=t ₂ or t=t ₃ or t=t ₄
At the same timing, the signal S ₂ ' is changed to t=t ₁ or t=t ₄
Alternatively, obtain the left channel audio signal component by sequentially and alternately sampling and holding at the timing of t = t ₃ , and convert the above signal S ₃ ' to t = t ₄ or t = t ₂ or t =
At the timing t ₁ , the signal S ₄ ' is changed to t=t ₃ or t=
An FM stereo demodulation method characterized in that a right channel audio signal component is obtained by sequentially and alternately holding samples at timings _t1 or t= _t2 . 2. The FM stereo demodulation method according to claim ₁ , which obtains a pilot signal component of Pc=(S ₁ −S ₂ +S ₃ −S ₄ )/4 from the signals S ₁ , S ₂ , S _{3 ,} and S 4 .