JPH05207497A - Digital color demodulation circuit - Google Patents

Abstract

PURPOSE:To attain color demodulation with a SIN table only in the SIN table and a COS table having been used for color demodulation through addition of a few circuits and to reduce the circuit scale. CONSTITUTION:A shifter 17 advancing a phase output (h) by 90 deg. or not advancing for each half clock of a clock (g) is provided between a SIN table 18 and a DTO 16, and a selector 19 separating signals whose phase is led and not led is provided after the SIN table 18, then a digital sine wave (n) and a digital cosine wave (m) are generated by the one SIN table 18 and color demodulation is attained by the SIN table 18 only through new addition of a few circuits to reduce the circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital color demodulation circuit in a digital color television receiver.

[0002]

2. Description of the Related Art In recent years, the trend toward digitalization in television signal processing has increased with the improvement in image quality and multifunction of television receivers, and digital color demodulation circuits for digitally demodulating color signals have been developed. It is considered important.

A conventional digital color demodulation circuit will be described below with reference to FIG. FIG. 3 is a block diagram showing the configuration of a conventional digital color demodulation circuit. In FIG. 3, reference numeral 31 is a first multiplier, which inputs the digital carrier color signal a and the digital sine wave j and outputs the multiplication output b. 32 is a second multiplier, which is used for digital carrier color signal a and digital cosine wave i
Is input and the multiplication output c is output. Reference numeral 33 denotes a first low-pass filter, which inputs the multiplication output b, removes the harmonic component, and outputs it as the U signal d of the color difference signal. A second low-pass filter 34 receives the multiplication output c, removes the harmonic component, and outputs it as the V signal e of the color difference signal. 35 is the PLL
Then, the V signal e is input and the phase frequency f for phase adjustment between the color burst and the digital subcarrier is output. 36 is a DTO, which inputs the phase frequency f and the clock g and outputs the phase output h of the digital subcarrier to the clock g.
Output every time. A COS table 37 receives the phase output h and outputs a digital cosine wave i. A SIN table 38 receives the phase output h and outputs a digital sine wave j.

The operation of the digital color demodulation circuit thus constructed will be described below with reference to FIG. First,
The digital carrier color signal a is the first multiplier 31 for demodulating the U signal.
To a digital sine wave j, and a multiplication output b containing a harmonic in the U component is output. Multiplication output b
Is input to the low-pass filter 33, unnecessary harmonic components are removed, and the U signal d is output. Similarly, for demodulation of the V signal, the digital carrier color signal a is used for the V signal demodulation second
Is input to the multiplier 32 of FIG. 1 and is multiplied by the digital cosine wave i, and the multiplication output c including the harmonic component in the V component is output.
The multiplication output c is input to the low-pass filter 34, and unnecessary harmonic components are removed to output the V signal e. The V signal e is input to the PLL 35 for phase adjustment between the color burst and the digital subcarrier, and the phase frequency f with the phase error corrected is output. The phase frequency f is input to the DTO 36, and the phase output h of the digital subcarrier is the clock g.
It is output every time. The phase output h is input to the COS table 37 and the SIN table 38, and the digital cosine wave i and the digital sine wave j for color demodulation are output.

[0005]

However, in the above configuration, the digital sine wave and the digital cosine wave required for color demodulation are stored in two Rs of the SIN table and the COS table.
It is generated by the OM table and has a redundant circuit configuration.

The present invention has been made in consideration of the above problems, and SI is added by adding a few circuits.
An object of the present invention is to provide a digital color demodulation circuit capable of reducing the circuit scale by generating a digital sine wave and a digital cosine wave only with the N table so that color demodulation can be performed.

[0007]

In order to solve the above-mentioned problems, the digital color demodulation circuit of the present invention has, in addition to the conventional digital color demodulation circuit, a phase between the SIN table and the DTO every half clock. A shifter for advancing or not advancing by 90 degrees is provided, and after the SIN table, a selector for separating a signal for advancing the phase and a signal for not advancing the phase is provided.

[0008]

According to the present invention, the SIN and CO
Using the relationship of S, sin (θ + 90) = cos θ, D
Phase output as output from TO to SIN table,
By advancing or not advancing 90 degrees in time division during one clock, digital sine wave and digital cosine wave can be generated in one SIN table, and a few circuits are newly added. As a result, color demodulation can be performed only with the SIN table.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital color demodulation circuit according to an embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a digital color demodulation circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a first multiplier, which inputs the digital carrier color signal a and the digital sine wave n and outputs a multiplication output b. A second multiplier 12 receives the digital carrier color signal a and the digital cosine wave m and outputs a multiplication output c. 13 is a first low-pass filter, which is a multiplication output b
Is input to remove the harmonic component and output as the U signal d of the color difference signal. A second low-pass filter 14 inputs the multiplication output c, removes the harmonic component, and outputs it as the V signal e of the color difference signal. Reference numeral 15 is a PLL, which receives the V signal e and outputs a phase frequency f for phase adjustment between the color burst and the digital subcarrier. A DTO 16 receives the phase frequency f and the clock g and outputs the phase output h of the digital subcarrier for each clock g. 17 is a shifter,
The phase output h and the clock g are input, and the phase output k is advanced or not advanced 90 degrees every half clock.
Is output. A SIN table 18 receives a shifter output k and outputs a sine output 1 for the input phase. 19
Is a selector which inputs the sine output 1 and the clock g, separates the sine output and the cosine output that appear every half clock, and outputs them as a digital sine wave n and a digital cosine wave m.

The operation of the digital color demodulation circuit thus constructed will be described below with reference to FIG. First,
The digital carrier color signal a is the first multiplier 11 for demodulating the U signal.
To a digital sine wave n, and outputs a multiplication output b in which the U component contains a harmonic wave. The multiplication output b is input to the low-pass filter 13, the unnecessary harmonic components are removed, and the U signal d is output. Similarly, for demodulation of the V signal, the digital carrier color signal a is input to the second multiplier 12 for V signal demodulation, is multiplied by the digital cosine wave m, and the multiplication output c containing the harmonic in the V component is output. It The multiplication output c is input to the low-pass filter 14, the unnecessary harmonic component is removed, and the V signal e is output. The V signal e is input to the PLL 15 for the phase adjustment between the color burst and the digital subcarrier, and the phase frequency f with the phase error corrected is output. The phase frequency f is input to the DTO 16, and the phase output h of the digital subcarrier is the clock g.
It is output every time. The phase output h is input to the shifter 17, and is multiplexed into a phase that advances the phase by 90 degrees and a phase that does not advance every half clock, and is output as a shifter output k. The shifter output k is input to the SIN table 18, and the sine output 1 corresponding to the input phase value is output. The sine output 1 is input to the selector 19, separates the sine output and the cosine output that appear alternately every half clock, and outputs them as a digital cosine wave m and a digital sine wave n for color demodulation.

As described above, according to this embodiment, in addition to the conventional digital color demodulation circuit, the SIN table 18 and the DTO are provided.
A shifter 17 for advancing or not advancing the phase by 90 degrees every half clock is provided between 16 and, after the SIN table 18, a signal for advancing the phase and a signal for not advancing the phase are separated. By providing the selector 19, the phase output as the output from the DTO 16 to the SIN table 18 is advanced 90 degrees in a time division manner in one clock by utilizing the relationship between SIN and COS, sin (θ + 90) = cos θ. By turning it on or off, it is possible to generate the digital sine wave n and the digital cosine wave m in one SIN table 18. By adding a few circuits, the color of only one ROM table can be obtained. Demodulation is possible.

FIG. 2 is a block diagram showing a digital color demodulation circuit according to the second embodiment of the present invention. In FIG. 2, reference numeral 21 denotes a multiplier, which inputs a sine output q having a digital carrier chrominance signal a and a subcarrier frequency and time-division-multiplexed with a digital sine wave and a digital cosine wave every half clock, and performs multiplication To do. A selector 22 receives the multiplication output p of the multiplier 21 and the clock g, outputs the multiplication value of the time-division-multiplexed digital sine wave as the selector output b, and outputs the multiplication value of the digital cosine wave to the selector output c. Output as. 23 is the first low-pass filter, which is the selector output b
Is input to remove the harmonic component and output as the U signal d of the color difference signal. A second low-pass filter 24 receives the multiplication output c, removes the harmonic component, and outputs it as the V signal e of the color difference signal. 25 is a PLL, which inputs the V signal e,
The phase frequency f for adjusting the phase between the color burst and the digital subcarrier is output. A DTO 26 receives the phase frequency f and the clock g and outputs the phase output h of the digital subcarrier for each clock g. Reference numeral 27 denotes a shifter which inputs the phase output h and the clock g and outputs the output k of the phase which is advanced or not advanced by 90 degrees every half clock. 28 is a SIN table, shifter output k
Is the output for the input phase, that is,
It outputs a sine output q as a digital sine wave and a digital cosine wave.

The operation of the digital color demodulation circuit thus configured will be described below with reference to FIG. First,
The digital carrier color signal a is input to the color demodulation multiplier 21, is multiplied by a sine output q obtained by time-division-multiplexing a digital sine wave and a digital cosine wave every half clock, and a multiplication output p including a harmonic is output. It The multiplication output p is the selector 22
To the selector output b, and the multiplication value with the digital cosine wave is output as the selector output c. The selector output b is input to the low-pass filter 23, the unnecessary harmonic component is removed, and the U signal d is output. The selector output d is input to the low-pass filter 24, the unnecessary harmonic component is removed, and the V signal e is output. The V signal e is input to the PLL 25 for the phase adjustment between the color burst and the digital subcarrier, and the phase frequency f with the phase error corrected
Is output. The phase frequency f is input to the DTO 26, and the phase output h of the digital subcarrier is output every clock h. The phase output h is input to the shifter 27, and is multiplexed into a phase in which the phase is advanced by 90 degrees and a phase in which the phase is not advanced every half clock, and is output as a shifter output k. The shifter output k is input to the SIN table 28, and is output as a sine output q obtained by time division multiplexing a digital cosine wave and a digital sine wave for color demodulation, which are outputs for the input phase value.

As described above, according to this embodiment, in addition to the conventional digital color demodulation circuit, the SIN table 28 and the DTO are provided.
A shifter 28 for advancing the phase by 90 degrees every half clock is provided between 26, and the phase is advanced after the multiplier 21 for multiplying the output of the SIN table 28 by the digital carrier color signal. By providing the selector 22 for separating the signal of the signal which has not been advanced,
Using the relation sin (θ + 90) = cos θ, DTO
The phase output from 26 to the SIN table 28 is
It is possible to generate a digital sine wave and a digital cosine wave in one SIN table by advancing by 90 degrees in time division during 1 clock or leaving it as it is, and add a few circuits newly. By that, RO
Color demodulation of only one M table is possible.

[0015]

As described above, according to the present invention, in addition to the conventional digital color demodulation circuit, the SIN table and the DTO are provided.
A shifter for advancing or not advancing the phase by 90 degrees every half clock is provided between and, and after the SIN table, a selector for separating the signal of the phase advancing and the signal of not advancing the phase. By providing SIN and COS
DT using the relationship of sin (θ + 90) = cos θ
The phase output from O to the SIN table is 1
By advancing by 90 degrees in time division between clocks or leaving it as it is, digital sine wave and digital cosine wave can be generated in one SIN table, and a few circuits are newly added. , SIN table can be used for color demodulation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital color demodulation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a digital color demodulation circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional digital color demodulation circuit.

[Explanation of symbols]

 11 First Multiplier 12 Second Multiplier 13, 23 First Low Pass Filter 14, 24 Second Low Pass Filter 15, 25 PLL 16, 26 DTO 17, 27 Shifter 18, 28 SIN Table 19, 22 Selector 21 Multiplier

Claims (2)

[Claims] 1. A first multiplier for inputting a digital sine wave having a digital carrier chrominance signal and a subcarrier frequency and performing multiplication, and a digital cosine wave having the digital carrier chrominance signal and a subcarrier frequency, A second multiplier for performing multiplication and the output of the first multiplier are input,
First to remove the harmonic component and output the U component of the color difference signal
Inputting the output of the second low-pass filter and the second multiplier, removing the harmonic component and outputting the V component of the color difference signal, and the output of the second low-pass filter. , PL for outputting phase frequency for phase adjustment between color burst and digital subcarrier
L, a DTO that inputs the output of the PLL and a clock, and outputs the phase of the digital sine wave for each clock,
A shifter for inputting the output of the DTO and the clock to switch the phase of the digital sine wave to a phase advanced by 90 degrees and a phase not advanced for each half clock of the clock and outputting the shifter, and the shifter output. A SIN table for inputting and outputting a sine output corresponding to the input phase, an output of the SIN table and the clock are input, and a digital sine wave whose phase is not changed by the shifter is input to the first multiplier. A digital color demodulation circuit having a selector for controlling the output by the clock so as to output the digital cosine wave whose phase is advanced by the shifter to the second multiplier. 2. A multiplier for inputting a digital carrier chrominance signal, a signal obtained by multiplexing a digital sine wave and a digital cosine wave having a subcarrier frequency for each half cycle of a clock, and performing multiplication, and an output of the multiplier. And the clock, and the first signal multiplied by the digital sine wave,
A selector for separating a second signal multiplied by the digital cosine wave, and a first low pass for inputting the first signal of the selector, removing a harmonic component, and outputting a U component of a color difference signal. A filter, a second low-pass filter that inputs the second signal of the selector, removes a harmonic component, and outputs a V component of the color difference signal, and an output of the second low-pass filter, input the color A PLL that outputs a phase frequency for adjusting the phase between the burst and the digital subcarrier, a DTO that inputs the output of the PLL and the clock, and outputs the phase of the digital sine wave every clock, and a DTO of the DTO. Input the output and the above clock, and switch the phase of the digital sine wave advanced by 90 degrees and the phase that does not advance every half clock of the above clock and output. That the shifter and receives the shifter output, digital color demodulator circuit sinusoidal output according to the input phase and a the SIN table for output to the multiplier.