JPH0541792A - Picture processor - Google Patents

Abstract

PURPOSE:To surely detect an area even to a complicated graph by obtaining two kinds of data based on adjacent picture element patterns to a different azimuth with respect to an object picture element so as to combine the data. CONSTITUTION:A picture processing circuit 26 uses a data forming means 100 to input sequentially a binarization data corresponding to an original picture. Then the means 100 generate an optional object picture element data D and a closed loop picture element candiate data B corresponding to combined adjacent data PM1, PM2. Furthermore, a data forming means 200 inputs sequentially the binarization data corresponding to an original picture to generate the optional object picture element data D and a closed loop picture element object data A corresponding to combined adjacent data PM3, PM4 different combination from the PM1, PM2. Moreover, an area in closed loop, an outer area and a closed loop forming area, etc., are distinguished from each other even in the case of a complicated picture based on the combination of the data D, B, A. Furthermore, the area in the closed loop is painted out as black level information to clearly detect the area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for detecting a closed loop area for a complicated figure.

[0002]

2. Description of the Related Art An image of a copying machine which extracts only an image of a desired area or makes a copy in which only the area is erased without cutting and pasting an original, and an image of a facsimile which transfers only an image of the desired area. Processor required. In this type of device, detection of the designated area is the greatest point.

In a conventional image processing apparatus of this type, the coordinate data of the diagonal points of the area to be designated is input using the ten-key pad provided on the operation board, or the original image is read by the CRT display device. Is displayed, and the area is specified with a cursor, light pen, mouse, etc. while looking at the image. According to the former, it is troublesome to read and input the coordinates of the designated area of the document, and the designated area is practically limited to a simple shape such as a rectangle.
Further, according to the latter, since the apparatus is large and complicated such as having a CRT display, the cost is high, and real-time processing is not possible due to the addition of intermediate processing of reading an original image and displaying it on the CRT display. Is not suitable for copiers and facsimiles used in the office.

[0004]

As a response to this, Japanese Patent Publication No. 60-33333 discloses an apparatus for detecting an L-shape of a predetermined color written on a manuscript. According to this, the area is designated only by writing the mark on the document. However, since the L-shaped display is made up of two adjacent sides of a rectangle, the designated area is necessarily limited to a rectangle, and a color discrimination means is required to detect the L-shaped mark of a predetermined color. There is. In addition,
A device for detecting a designated area by detecting a mark drawn at a constant density has been proposed in Kogaku No. 62-159570. However, the concave area A as shown in FIG.
When the concave portion Ar2 is at the rear end in the sub-scanning direction in r1, the concave area Ar1 + the concave portion Ar2 is detected as the area, and the area Ar3 surrounded by the double closed loop as shown in FIG. In the above, the internal area Ar4 of the closed loop inside the area Ar3 + was detected as the area. That is, there is a drawback that erroneous detection is performed on a specific figure.

The present invention is shown in FIG. 41 (a) and FIG.
It is an object of the present invention to reliably detect a region even for a complicated figure as shown in (b).

[0006]

An image processing apparatus according to the present invention sequentially inputs binarized data corresponding to an original image, and outputs arbitrary target pixel data (D) and data adjacent to the pixel data (D). Data forming means (10) for forming first closed loop pixel candidate data (B) corresponding to the combination (PM1, PM2) of
0); Binary data corresponding to the original image is sequentially input, and a combination of the first data forming means (100) of arbitrary target pixel data (D) and data adjacent to the pixel data (D) (PM1, P
Second data forming means (200) for forming second closed loop pixel candidate data (A) corresponding to a combination (PM3, PM4) different from M2); instruction means (K1, 5); and instruction When there is an instruction from the means (K1, 5), the target pixel data (D), the first closed loop pixel candidate data (B), and the second closed loop pixel candidate data (A)
Output means (203, 204, 500) for converting the data corresponding to the closed loop area or the concave area of the original image into a predetermined value and outputting the data. The symbols in parentheses are the corresponding elements of the examples described later.

[0007]

According to this, the first data forming means (10
(0) sequentially inputs binary data corresponding to the original image,
First closed-loop pixel candidate data (B) is formed corresponding to a combination (PM1, PM2) of arbitrary target pixel data (D) and data adjacent to the pixel data (D). Further, the second data forming means (200) sequentially inputs the binarized data corresponding to the original image, and the arbitrary target pixel data (D) and the pixel data (D)
Second closed-loop pixel candidate data (A) is formed corresponding to a combination (PM3, PM4) different from the combination (PM1, PM2) of the first data forming means (100) of the data adjacent to. ..

That is, by obtaining two kinds of data in pixel patterns adjacent to the target pixel in different directions, by combining these data, when a closed loop exists in the original image, at least the data inside the closed loop and the outside of the closed loop. Data can be different data.

Further, by combining the target pixel data (D), the first closed-loop pixel candidate data (B), and the second closed-loop pixel candidate data (A), even in a complicated image, a closed loop area, It is possible to distinguish the closed loop outer region, the region forming the closed loop, and the like, and by filling the closed loop inner region with black information, the closed loop inner region can be filled. Note that these operations are instructing means.
It is performed in response to the instruction of (K1,5).

According to a preferred embodiment of the present invention,
Data conversion means (500 ') for converting the data output from the output means (203, 204, 500) into predetermined color image data;
Equipped with. Therefore, by using a recording unit capable of color recording as the recording unit, it is possible to change the color inside and outside the closed loop of the original image and perform image recording. Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

[0011]

FIG. 1 shows the appearance of a digital copying machine equipped with the image processing apparatus of the present invention. This digital copying machine is a general digital copying in which a document set on a document table (contact glass) is exposed and scanned to read an image, and the read image is subjected to predetermined processing to form an image on a transfer paper. The machine is equipped with a "closed loop fill" function. The instruction of “closed loop filling” is performed by pressing the input key K1 provided on the operation unit 5.

FIG. 2 is a block diagram showing a schematic configuration of the digital copying machine shown in FIG. 1, and FIG. 3 is a block diagram showing a schematic configuration of the image processing unit 2 shown in FIG. The document set on the document table with the surface to be read facing down is the document reading means 1
The exposure light is scanned by the exposure light, and the exposure light is input to the CCD image sensor 11 of the document reading unit 1. The analog image signal output from the CCD image sensor 11 is amplified by the amplifier 21 and converted into digital image data (for example, 6 bits or 8 bits) by the A / D converter 22. The digital image data is corrected by the correction circuit 23 by shading correction,
In response to corrections such as MTF correction and smoothing, the magnification changing circuit 24 performs magnification changing processing in the main scanning direction (magnification changing in the sub-scanning direction is performed optically by changing the scanning speed during document scanning. ). Further, the image data is binarized by the binarization processing unit 25. After that, various processing including the processing of the present invention is performed in the image processing circuit 26, and the reproduced image is recorded by the image recording unit 3 based on the image data subjected to the image processing. A signal obtained by pressing the key K1 provided on the operation unit 5 is input to the image processing unit 2 via the control unit 4, and when the copy operation is performed in the state in which "closed loop filling" is instructed by the key K1, the original document is displayed. An image in which the closed-loop image of is filled is obtained as a reproduced image.

FIG. 4A shows the main scanning direction and the sub-scanning direction with respect to the original, and hereinafter, the main scanning direction is x and the sub-scanning direction is y, unless otherwise specified. Figure 4
In (a), L1, L2, ..., L4, etc. are referred to as main scanning lines or simply scanning lines, respectively. Further, the letter "A" written as a contour character on the document indicates an image on the document. FIG. 4B shows the state when the key K1 is input.
It shows a reproduced image for the original image shown in (a).
In contrast to the outline character "A" on the original, the inside of the outline is the character "A" in the reproduced image. In the present invention, the closed loop on the original is painted in this way and the area signal in the closed loop is generated. Hereinafter, the image processing circuit 2
The process of the present invention will be described in detail centering on the process in 6.

In FIG. 5, the closed loop image on the original is read and x
1 shows an example of image data in which pixels are decomposed in the y and y directions and the image density is binarized into black 1 and white 0 for each image. It should be noted that the data 0 representing white is not shown in the figure for the sake of clarity. That is, in FIG. 5, each section is a pixel, 1 in the pixel indicates that the pixel is black, and a pixel in which nothing is entered indicates white.

In the process of actual reading and writing, two-dimensional image data as shown in FIG. 5 is not obtained at the same time, and each main scanning line and even within one line is in the main scanning direction (indicated by arrow Aa in the figure). Direction), image data is sequentially obtained for each pixel, and when one line of image data is completed,
Image data of the next line in the y direction is also obtained pixel-sequentially in the main scanning direction. Writing is also performed line by line in synchronization with this scanning of reading and image processing. The binarization processing circuit 25 binarizes the image data according to its density as shown in FIG.

The operation and action of the processing circuit 26 for detecting a closed loop and generating image data and a closed loop area signal for which the closed loop is filled in the image data of FIG. 5 will be described below with reference to FIGS. 6 to 22. Explain.

FIG. 6 shows a process of detecting a pixel which is the first candidate in the closed loop. When it is a candidate, the first candidate flag B corresponding to the pixel is set to B = 1. In the initial state, that is, before inputting image data, B = 0. First, in the data input shown in step b1, the binarized image data D is input line by line and in pixel order in the direction of the arrow Ab in FIG. The reason why the data is input in the direction opposite to the main scanning direction is simply to simplify the configuration of the entire processing circuit, and obtaining image data in the direction of the arrow Ab will be described later with a circuit. like,
It can be easily obtained by reversing the order of writing and reading data to the line memory.

The image data D input in the Ab direction in the pixel order is processed differently depending on whether D = 1 or not, and D = 1.
In this case, the value of B is "B = B- _y " (step b
2, b6). Here, B _−y is the value of B of the pixel that is adjacent to the pixel to be processed and is one pixel before in the y direction. For example, in FIG. 5, if the pixel to be processed is (x ₁₅ , y ₂ ), B _−y is the B value of the pixel of (x ₁₅ , y ₁ ). The initial state of this B _-y also B _-y = 0.

On the other hand, if D ≠ 1, the process proceeds to step b3 to check whether the data distribution is PM1. Here, PM1 has a pattern as shown in FIG. 10A, and hatched pixels are pixels to be processed. Not limited to FIG. 10A, all the pixels shown by hatching in FIG. 10 indicate pixels to be processed, the number 0 or 1 in the pixel indicates binarized image data, and the x mark indicates 0 or 1. Either is shown. That is, in step b3, when the target pixel is 0 and the pixel one above is 0 as in PM1 shown in FIG. 10A, the process proceeds to step b6 and B = B _−y
And If the target pixel is 0 and the pixel one above is not 0, the process proceeds to the next step b4 to check whether the data is PM2. Note that PM2 has the pattern shown in FIG.

If the data is PM2, that is, if the pixel of interest is 0, the pixel immediately above is 1 and the pixel on the right is 0, the process proceeds to step b7 and B = B _{+ y} . If PM2 is not set at step b4, B = (inverted signal of B _{+ y} ). The inverted signal is shown with an overline in the figure. As is clear from the pattern matching up to this point, the case where the PM2 is not PM2 in step b4 is only in the case of the data distribution pattern as shown in FIG.

FIG. 7 is a diagram showing the value of B when the detection process shown in FIG. 6 is sequentially performed on the image shown in FIG. For example, in (x ₁₈ , y ₁ ), since D = 1, B =
It becomes 0. At (x ₁₆ , y ₂ ), it is not “PM2” but FIG.
Since it is the pattern shown in (c), B = (inversion of B _{+ x} ) =
It becomes 0.

Next, FIG. 8 shows a process of detecting a pixel which is a second candidate in the closed loop, and when it is a candidate, the second candidate flag A corresponding to the pixel is set to A = 1. In the initial state, that is, before inputting image data, A = 0. In the data input of step a1, the binarized image data D is sequentially input line by line and in pixel order in the direction of arrow Aa in FIG. At this time, in synchronization with the input of the pixel to be processed, B
Is also read and used to determine A.

The image data D input in the Aa direction in the pixel order is processed differently depending on whether D = 1 or not, and D = 1.
In this case, the value of A is “A = A _−y ” (step a
2, a6). Here, A _−y is the value of A of the pixel adjacent to the pixel to be processed and one pixel before in the y direction.

On the other hand, if D ≠ 1, the process proceeds to step a3 to check whether the data distribution is PM3. Here, PM3 has a pattern as shown in FIG. 10D, and the hatched pixel is the pixel to be processed. When the target pixel is 0 and the pixel one above is 0 as in PM3 shown in FIG. 10D, the process proceeds to step a6 and A = A _−y
And If the target pixel is 0 and the pixel above it is not 0, the process proceeds to step a4, where it is checked whether the data distribution is PM4. Note that PM4 has the pattern shown in FIG.

If the data is PM4, that is, if the pixel of interest is 0, the pixel immediately above is 1 and the pixel on the right is 0, then the processing advances to step a7, where A = A _-x . If PM4 is not set at step a4, A = B is set (a5). As is clear from the pattern matching so far, the case where PM4 is not used in step a4 is only the case of the data distribution pattern shown in FIG.

FIG. 9 shows the image data of FIG.
Using the flag data shown in, A in pixel order and line order
The value of A in the case of sequentially performing the processing for obtaining (FIG. 11) is shown. For example, in (x ₃ , y ₂ ) of FIG. 5, since D = 1, A = A _−y = 0. For (x ₄ , y ₂ ), FIG.
Since it matches with (f), A = B = 1. Also (x ₈ ,
In y ₄ ), “PM4” but A = A _−x = 1.

In FIG. 9, at least all pixels inside the closed loop have A = 1, and all pixels outside the closed loop have A = 0. Further, the value of A of the pixel corresponding to the original image (“1” in FIG. 5) forming the closed loop is 0 or 1. Therefore, the closed loop inner region signal, the closed loop outer region signal, and the closed loop inner fill signal can be created by a simple logical operation of the value of A (FIG. 9) and the image data (FIG. 5). For example, A · (inverted signal of D) (note that · is AND logic) indicates a region inside the closed-loop boundary line, and A + D (+ is OR logic) indicates the closed-loop boundary line and the filling inside thereof.

FIG. 11 is a block diagram of a circuit for obtaining the in-closed loop candidate flags B and A by executing the processing shown in FIGS. 6 and 8 in the image processing circuit 26 shown in FIG. The output Y = B in the logic processing circuit. The circuit 200 is a logic processing circuit for obtaining A, and the output Y1 = A. Also, Y0 = D, Y2 = A + D, Y3
= A · (inverted signal of D). In addition, + means OR, and * means AND. Reference numeral 500 is an output circuit for obtaining predetermined image data. Signal D is binarized data, S
YNC is a synchronizing signal of the main scanning line, CK is a pixel clock in the main scanning direction, XG is a gate signal indicating a data valid period in the main scanning direction, and a period of XG = 1 is a valid signal of image data. A time chart of these signals is shown in FIG.
And shown in FIG. The signal YG is a signal indicating a data valid period in the sub-scanning direction, and the period YG = 1 is a valid signal.

FIG. 13 is a block diagram showing the structure of the circuit 100 shown in FIG. 101, 102, 104, and 105 are RAMs, and in these RAMs, D
i is a data input terminal, Do is a data output terminal, AD is an address terminal group, and WE is a write enable terminal with an overline added. 103, 106,
Reference numerals 109 and 110 denote selectors, and when S = 0, input A is output Y (Y = A), and when S = 1, input B is output Y (Y = B). An up counter 107 counts up the clock CK from the initial value = 0 during the period of XG = 1. A down counter 108 counts down the clock CK from the initial value M during the period of XG = 1. The initial value M is the maximum count value M of the up counter 107, that is, the x-direction pixel address value M corresponding to the right edge of the document in FIG. 4A. Further, 111 is a D type flip-flop (D-
FF), 112 and 113 are AND gates. Thirty
Reference numeral 0 is a first flag detector for obtaining the flag B by pattern matching.

Next, the operation of the circuit 100 will be described with reference to FIG. The output signals a and b of the D-FF 111 have a relation of “a = (inversion of b)”, and they perform an inverting toggle operation between 0 and 1 for each line. For example, in the line of a = 0, since Y = SA in the selector 109, the output signal Au of the up counter 107 is given to the address terminals AD of the RAMs 101 and 104, and the input SA of the selector 109 becomes SA = Au. .. Also gate 1
A signal C is generated by 12 and applied to the RAMs 101 and 104. On the other hand, at this time, b = 1 and the selector 11
At 0, Y = SB, so that the output signal A of the down counter 108 is applied to the address terminals AD of the RAMs 102 and 105.
d is given, the input SA of the selector 110 is SA = A
It becomes d. Further, the signal d is not generated by the action of the gate 113, and the write enable signal (the inverted signal of WE) to the RAMs 102 and 105 is not generated.

After all, in the line a = 0 (b = 1), the RAMs 101 and 104 perform the write operation while the address is being counted up, and the RAMs 102 and 10
5 performs a read operation while the address is being counted down. On the other hand, in the line a = 1 (b = 0), the RAMs 101 and 104 perform the read operation while the address is being counted down, and the RAMs 102 and 105 are the write operation while the address is being counted up.

Since the binarized image data D is input to the RAMs 101 and 102, these RAM read outputs are image data obtained by reading D written one line before in the direction of arrow Ab in FIG. Is. When a = 0, the select terminal S becomes S = b = 1 by the selector 103, so Y = SB is selected. Conversely, when a = 1, Y = S.
A is selected. Therefore, the output Y of the selector 103 is delayed by one line with respect to the input image data D, and A of FIG.
This is image data sequentially generated in the b direction.
This Y corresponds to the data input in the "data input" of FIG. In the first flag detector 300, the presence or absence of the data distribution pattern of "D = 1", "PM = 1", "PM = 2" shown in FIG. 6 is detected (pattern matching), and the value of B is determined. Output to the output terminal Y.

RAMs 104 and 105 and selector 10
The combination of 6 performs the same operation as the combination of the ROMs 101 and 102 and the selector 103. Therefore, the output Y of the selector 106 is flag data that is delayed by one line with respect to the output signal of the detector 300 and that is sequentially generated in the direction of arrow Aa in FIG. Y is in the direction of arrow Aa because the input signals to RAMs 104 and 105 are in the direction of arrow Ab in FIG.

After all, the output Y of the first flag detector 300
Is output in the direction of arrow Aa in FIG. 5 with a delay of two lines from D with respect to the input image data D and in synchronization with D.
Is a signal representing the candidate flag B.

FIG. 14 shows the configuration of the first flag detector 300 shown in FIG. 301 and 311 are FiFo (First
In First Out) line memory, eg NEC μPD42
It is 505C. Input data P in synchronization with the clock signal CK
While i is sequentially written in the memory, it has a function of reading already written data in the same order as the writing order in synchronization with the clock signal. A detailed description of the μPD42505C is omitted here, but as an example of use in the present invention, this FiFo is used as a one-line digital delay line. That is, the output Do is delayed by one line with respect to the input Di and is read in the same order as Di in synchronization with Di. For example, if Di is (x ₅ , y ₄ ) in FIG.
As for o, (x ₅ , y ₃ ) is output. In addition, WCK given to the μPD42505C to perform the operation as a digital delay line,
Control signals such as RCK and WE inversion signals, RE inversion signals, RSTW inversion signals, and REST inversion signals are shown in FIG.
Is omitted. Further, 302 and 312 are D type flip-flops, and 303 to 310 are logic gates.

Next, the operation of the first flag detector 300 will be described. The input signal D corresponds to, for example, the processing target pixel shown in FIG. 10A, the output Do of 301 corresponds to the pixel above the processing target pixel, and the output Q of 302 corresponds to the pixel on the right side of the processing target pixel. It corresponds. The gate 303 corresponds to “PM1”, and the gate 306 corresponds to “D = 1” or the flow toward “B = B _−y ” when “PM1”. The gate 307 generates “B = B _−y ”, and the output Do of 311 corresponds to B _−y as described later. The gate 304 corresponds to “PM2”, and the gate 30
8 generates "B = B _{+ y} ". As will be described later, the output Q of 312 corresponds to B _{+ y} . When the gate 305 is not “PM2”, that is, corresponding to the pattern shown in FIG. 10C, the gate 309 generates “B = (inversion of B _{+ y} )”. The output of the gate 310 corresponds to the flag B and is output as the signal Y. As is clear from the fact that the signal Y is B, the output Do of 311 is B _-y and the output Q of 312 is Q.
Is an inversion signal of B _{+ y} , and an inversion signal of Q is an inversion signal of B _−y .

FIG. 15 is a block diagram showing the structure of the circuit 200 shown in FIG. Reference numerals 201 and 202 denote FiFo line memories, which are used as digital delays like the detector 300. Reference numeral 400 is a second flag detector for obtaining A by pattern matching. Also, 203,
204 is a logic gate. The input signal D in FIG. 15 is the input signal D in FIG. The input signal B is the output Y of the circuit 100 shown in FIG. Therefore, it is the same signal as the output signal Y in FIG. As is apparent from the operation of the circuit 100 described with reference to FIG. 13, the input signal B is delayed by two lines with respect to the input signal D. To compensate for this delay, the input signal D is delayed by two lines at 201 and 202, and then the second flag detector 400
Are typing in. Therefore, the inputs D and B in the first flag detector 300 are the image data D and the flag B corresponding to the same pixel.

Second flag obtained by the second flag detector 400
The candidate flag A is output as the signal Y1. Signal Y0
Is image data of the same pixel as the signal Y1. Gate 20
3 outputs Y2 = Y0 + Y1 (+ is OR), and the gate 204 outputs Y3 = Y1. (Y0 inverted signal)
(Note that · is AND) is output.

FIG. 16 shows the configuration of the second flag detector 400 shown in FIG. FiFo line memories 401 and 411 are used as digital delay lines like the FiFo line memory shown in the detector 300. 402,4
12 is a D-type flip-flop, which is 403-41
0 is a logic gate.

Next, the operation of the second flag detector 400 will be described. The input signal D corresponds to, for example, the processing target pixel shown in FIG. 10D, the output Do of 401 corresponds to the pixel above the processing target pixel, and the output Q of 401 corresponds to the pixel to the left of the processing target pixel. It corresponds. Gate 403 is "P
Corresponding to "M3", the gate 306 corresponds to the flow toward "A = A- _y " when "D = 1" or "PM3". The gate 407 generates “A = A _−y ”,
As will be described later, the output Do of 411 corresponds to A- _y . The gate 404 corresponds to “PM4”, and the gate 408.
_Produces "A = A- _x ". As will be described later, output Q of 412
Corresponds to A _-x . When the gate 405 is not “PM4”, that is, corresponding to the pattern shown in FIG. 10F, the gate 409 generates “A = B”. Gate 40
The input signal 9 is the first candidate flag B obtained by the circuit 100. The outputs of 407, 408, and 409 are input to the OR gate 410, and the output of the OR gate 410 corresponds to the flag A and is output as the signal Y. As is apparent from the signal Y being A, the output D0 of 411 is A _-y and the output Q of 422 is A _-x .

The above is the configuration and operation of the circuit means for executing the process for obtaining the candidate flag B (FIG. 6) and the process for obtaining the candidate flag A (FIG. 8), and the candidate flag A and the image. This is an operation of generating a closed loop inner area signal and a closed loop inner filling signal from the data D. For example,
The closed loop fill signal Y2 (the output of the circuit 200) is used as the output of the output circuit 500, and the image of the image recording unit 3 shown in FIG. Filled,
A closed loop filled image is obtained. When the output of the circuit 500 is set to Y3, an image in which the area inside the boundary line of the closed loop is painted is obtained. In the circuit description above, setting of the initial state of the flip-flop, counter, RAM, FiFo memory, etc. is omitted, but the signal XG,
Of course, YG, XSYNC, CK, etc. set appropriate initial states.

FIG. 17 is a block diagram showing an example of an output circuit 500 different from the above (when the output of the circuit 200 is directly used as the output of the output circuit 500).
= A, image data Y0 = D, and image data of the pattern generator (character generator) 501, a means for obtaining image data in which the closed loop is filled with a specific image pattern is shown. By performing image recording based on the output signal Y4, for example, with respect to a closed-loop original image as shown in FIG. 18 (a), the character (A) “A” as shown in FIG. It is possible to obtain a reproduced image that has been painted over.

Further, FIG. 19 shows an example of an output circuit different from the above-mentioned output circuit 500. In this circuit 500 ', the color data addition circuit 504 receives a color designation input from the operation unit,
The respective data of Y0, Y1, Y2 and Y3 are converted into designated color data. In this conversion, data is converted into magenta, cyan, and yellow data at a predetermined ratio corresponding to the color so that a color image designated at the time of image formation is formed. This data is output via the magenta, cyan, and yellow buffers 505, 506, and 507. Accordingly, if a recording device capable of recording a plurality of colors such as a color recording device is used for the image recording unit 3 (FIG. 2), for example, the signal Y0 = D and the signal Y3 = A. (Inverted signal of D) By recording and in different colors, it is also possible to obtain an image in which the closed-loop frame (boundary line) and the inside of the frame are recorded in different colors. It is also possible to obtain an image in which different colors are recorded outside the closed loop.

(Modification 1) FIG. 20 shows a processing flow which replaces the other processing for obtaining the candidate flag B shown in FIG. The difference from the processing shown in FIG. 6 is step b6 in FIG.
“B = B _−y ” in this case becomes “B = A _−y ”. Further, FIG. 21 shows another processing flowchart which replaces the processing for obtaining the candidate flag A shown in FIG.

22 and 23 are similar to FIGS. 20 and 2.
It is a figure for demonstrating the calculation method of B and A corresponding to the flow of 1. The original image is the same as the image shown in FIG. First, the process of obtaining B will be described with reference to FIG. Now, it is assumed that A is obtained up to the Y3 line and B of the Y4 line is obtained. For example, (x ₁₈ , y ₄ ) is “D = 1”
Therefore, B = A _−y = 0. (X ₁₅ , y ₄ ) is “P
Since M1 ”, B = A _−y = 1. (X ₁₁ , y ₄ )
Is not "PM2", that is, B = (inverted signal of B _{+ x} ) = 0 as shown in FIG. (X ₁₀ , y
₄ ) is “PM2”, that is, B = B _{+ x} = 0 as shown in FIG. (X ₇ , y ₄ ) is “PM1”
That is, as shown in FIG. 10A, B = A _−y = 1
Is. In this way, B of the Y4 line is obtained as shown in FIG.

Next, referring to FIG.
The process of obtaining A of the line will be described. Since (x ₂ , y ₄ ) is not “PM4”, that is, the pattern shown in FIG. 10E, A = B = 0. (X ₃ , y ₄ ) is “PM = 4”
Therefore, A = B = 1. (X ₄ , y ₄ ) is “PM
4 ”, so A = A _−x = 1. Similarly (x ₅ ,
y ₄ ), (x ₆ , y ₄ ), and (x ₇ , y ₄ ) also have A = A _−x = 1. (X ₈ , y ₄ ) is B = 0, but A is “PM4”
Therefore, A = A _−x = 1. (X ₉ , y ₄ ) is also "P
Since M4 ”, A = A _−x = 1. (X ₁₉ , Y ₄ )
Is not "PM4", A = B = 0. In this way, A of the Y4 line is obtained as shown in FIG.

When A of the Y4 line is obtained, then B of the Y5 line is obtained as shown in FIG. By repeating the above processing in the order of lines Y4 → Y5 → Y6 → ..., The correction flag A is finally obtained for all images.

A of the Y4 line is obtained, and A is A = 1 at least for pixels inside the closed loop, and A = 0 for pixels outside the closed loop. From A and the image data, a closed loop area signal (inside the boundary line) and a closed loop in-fill signal (boundary line and inside) can be obtained.

FIG. 24 is a block diagram showing a second flag detector 600 that executes the flow shown in FIG. The second flag detector 600 is used in place of the above-mentioned second flag detector 400. 6 of the second flag detector 600
01 and 602 are D-type flip-flops, 602 to 6
Reference numeral 05 is a logic gate. The input image data D corresponds to the number of images to be processed, and the output Q of 601 corresponds to the pixel on the left of the pixel to be processed. The gate 602 corresponds to “PM4”, and the gate 603 corresponds to “PM =“ A =
A _-x "is generated. The gate 604 generates "A = B" when it is not "PM4". The output of the OR gate 605 is the flag A, which is output as the signal Y. Since the input D of 606 is A, the output Q is A _−x and is input to 603.

The above is the description of the processes and circuit operations of the flows shown in FIGS.

(Modification 2) FIG. 25 shows still another second flag A detecting process in place of the process shown in FIG. Further, FIG. 26 shows a data pattern corresponding to PM5 in step b13 of FIG. In FIG. 27, the second flag detector 700 (the above-mentioned detector 40) that executes the processing shown in FIG.
(Corresponding to 0). 701 is a FiFo line memory, 7
02 and 703 are D flip-flops, and 703 to 711 are logic gates. The operation of the detailed part of the logic is the same as the operation shown in FIGS. 11 to 17, and the combination of these operations is only slightly different, so the details will be omitted.

(Modification 3) FIGS. 28 to 32 show a process in which another process is added to the above-described process (closed-loop pixel detection process). In this case, first, the candidate flags B and A are obtained, and the final candidate flag C can be obtained from the results of B and A. FIG. 28 shows a flow for obtaining B. Similar to the process shown in FIG. 6, B is obtained in the pixel order in the direction of the arrow Ab shown in FIG. Step b2 in FIG. 28
FIG. 29 shows the processing contents of "B = _C'-x " shown in FIG. FIG. 30 shows a flow for obtaining A. The pixel order is obtained in the direction of arrow Aa in FIG. “A” shown in step a37 of FIG.
31 shows the processing contents of "= _C'-y ". FIG. 32 shows A,
The flow which calculates | requires C from B is shown. Each of the candidate flags A and B is flag data represented by 2 bits,
"00" is outside the closed loop, "11" is inside the closed loop, "0"
"1" represents a change from outside the closed loop to inside the closed loop, and "10" represents a change from inside the closed loop to outside the closed loop. C is C = 0 as shown in FIG.
In the closed loop, it is 1-bit flag data with C = 1.

The process for obtaining B, A and C shown in FIGS. 28 to 32 will be described with reference to FIGS. 33 to 35. First, in FIG. 33, it is assumed that C has been obtained up to the Y2 line. At this time, B on the Y3 line is as shown in FIG. For example, at (x ₁₇ , y ₃ ), it is not “PM2” at step b24 in FIG. 28, and “B _{+ x} = 00” at step b25, so that “B = 01”.

In FIG. 34, it is assumed that the Y2 line has been obtained. At this time, B on the Y3 line is as shown in FIG. For example, at (x ₄ , y ₃ ), since it is “PM3” at step a33 in FIG. 30, “A = _C′-y ”. "A = _C'-y " is "C- _y = 0" in FIG.
Since (the value of C in (x ₄ , y ₂ ) is C = 1),
It becomes "A = 11".

As shown in FIGS. 33 and 34, when B and A of the Y3 line are obtained, the process shown in FIG.
C can be obtained like the Y3 line shown in. For example (x ₃ ,
In y ₃ ), B = 11, A = 01, so C = 1. Thus, by obtaining B and A for each line and obtaining C from the result, C is obtained for each line, and finally C is obtained for the entire image.

FIG. 36 shows a configuration for obtaining the closed loop fill signal Y2 and the closed loop in-region signal Y3 from the final candidate flag C and the image data D '(D' is data obtained by delaying D).

(Modification 4) FIGS. 37 to 40 show still another example of the closed loop pixel detection processing. First, the candidate flag B is obtained by scanning in the B direction by the processing shown in FIG. 37, and then the candidate flag A is obtained by scanning in the A direction by the processing shown in FIG. The pattern PM6 is shown in FIG.
Fig. 39 (b) shows PM7 and Fig. 39 (c) shows PM8.
Fig. 39 (d) shows PM9 and Fig. 10 (c) shows PM10.
Fig. 10 (b) shows PM2 and Fig. 39 (e) shows PM11.
The PM 12 corresponds to FIG. 39 (f). The case of not being "P11" in step b48 of FIG. 37 is the case of the pattern of FIG. 39 (g), and the case of not being "P12" in step b50 is the case of the pattern of FIG. 39 (h). In FIG. 37, "B = A _{+ xy} "
"A _{+ xy} " in the scanning direction (Ab
This is the meaning of the candidate flag A of the pixel that is one before in the direction) and one before in the sub-scanning direction, that is, the pixel that is diagonally adjacent to the pixel to be processed. Further, "B _{+ x} = A _-y " is the candidate flag "B _{+ x} " of the pixel immediately before in the scanning direction (Ab direction) with respect to the processing target pixel, and 1 in the sub-scanning direction with respect to the processing target pixel. It is determined whether or not the candidate flag “A _−y ” of the _{immediately preceding} pixel matches, and the method of determining the candidate flag B of the pixel to be processed differs depending on the result.

The pattern PM13 shown in FIG. 38 is shown in FIG.
9 (i), PM14 corresponds to FIG. 39 (j), PM15 corresponds to FIG. 39 (k), and PM4 corresponds to FIG. 10 (e). Obliquely "A _-xy" in one front in the scanning direction (Aa direction) with respect to the processing target pixel and immediately preceding pixel in the sub-scanning direction, i.e. the pixel to be processed in the "A = A _-xy" This means the candidate flag A of the pixel adjacent to. Finally, the candidate flag A becomes "1" inside the closed loop and becomes "0" outside the closed loop. From this A and the image data D, the closed loop inner area signal in the closed loop inner filling signal is obtained.
The logical processing for realizing the processing flows of FIGS. 37 and 38 can be performed in the same manner as the above-described example, and various modifications can be made.

As described above, the method shown in FIGS. 6 and 8 is used as a representative example to show how to obtain the candidate flags B and A according to various other modified embodiments. Further, FIGS. As shown in FIG. 40, the method for obtaining C is described. As shown in FIG. 40, (a) a plurality of closed loops are in contact, (b) a closed loop is multiplexed, and (c) a loop. If part of is open and not in closed loop,
And (d) in the case of a closed loop having a complicated shape with irregularities, the response (value of the flag) corresponding to etc. is only slightly different. For example, for the closed loop of FIG. The flag C is set to 1.

Although the embodiment of the present invention has been described above, it goes without saying that the present invention is not limited to this embodiment and various modifications can be made. For example, the flow for obtaining the flag B or A can be variously modified, and the pattern matching pattern can be variously modified. Further, the logic for obtaining the flag can be modified in various ways. Further, although the example of generating the closed loop fill signal (Y2) and the closed loop inner region signal (Y3) is shown in the embodiment, the application of the present invention makes it easy to detect the outside of the closed loop and to generate the closed loop outer fill signal and the closed loop outer region signal. Of course,

[0061]

As described above, according to the present invention, first of all,
The data forming means (100) sequentially inputs binarized data corresponding to the original image, and combines arbitrary target pixel data (D) and data adjacent to the pixel data (D) (PM1, PM2) Corresponding to the first closed loop pixel candidate data (B). Further, the second data forming means (200) sequentially inputs the binarized data corresponding to the original image, and the first data of the arbitrary target pixel data (D) and data adjacent to the pixel data (D) The second closed-loop pixel candidate data (A) is formed corresponding to the combination (PM3, PM4) different from the combination (PM1, PM2) of the data forming means (100). That is, when two types of data are obtained with pixel patterns adjacent to each other in different directions with respect to the target pixel, and when a closed loop exists in the original image due to the combination of the data, at least the data inside the closed loop and the data outside the closed loop are It can be different data.

Furthermore, by combining the target pixel data (D), the first closed-loop pixel candidate data (B), and the second closed-loop pixel candidate data (A), even in a complicated image, a closed-loop inner area, It is possible to distinguish the closed loop outer region, the region forming the closed loop, and the like, and by filling the closed loop inner region with black information, the closed loop inner region can be filled. Note that these operations are instructing means.
It is performed in response to the instruction of (K1,5).

Further, since the data conversion means (500 ') for converting the data output from the output means (203, 204, 500) into predetermined color image data is provided, it is possible to use the recording means capable of color recording as the recording means. It is possible to record an image by changing the color inside and outside the closed loop of the original image.

[Brief description of drawings]

FIG. 1 is a perspective view showing an appearance of a digital copying machine equipped with an image processing apparatus of the present invention. ..

FIG. 2 is a block diagram of a schematic configuration of the digital copying machine shown in FIG.

3 is a block diagram of a schematic configuration of an image processing unit 2 shown in FIG.

4A is a plan view of a document showing main scanning and sub-scanning directions with respect to the document, and FIG. 4B is a diagram showing a document image shown in FIG. 4A when a key K1 is input. It is a top view which shows a reproduction | regeneration image.

FIG. 5: Reading the closed loop image on the original, x and y
3 is a data map showing an example of image data that is decomposed into pixels in a direction and binarized into image density of 1 for black and 1 for image density (0 is omitted in the figure).

FIG. 6 is a flowchart showing a process of detecting a pixel that is a first candidate in a closed loop.

7 is a data map showing the value of B when the detection process shown in FIG. 6 is sequentially performed on the image shown in FIG.

FIG. 8 is a flowchart showing a process of detecting a pixel that is a second candidate in the closed loop.

9 is a data map showing the value of A when the process of obtaining A in pixel order and line order (FIG. 11) using the flag data shown in FIG. 7 is sequentially performed on the image data of FIG. .. ..

FIG. 10 is a block diagram showing a pattern of data matching, (a) is PM1, (b) is PM2, and (c).
6 shows a data pattern when PM2 is not PM2 in step b4 in FIG. 6 (or PM10 in Modification 4), PM3 is (d), PM4 is (e), and PM4 is PM4 in FIG. 87 (f). Data patterns are shown respectively.

11 is a block diagram showing a schematic configuration of the image processing circuit 26, and is a block diagram showing a circuit configuration for executing the processing shown in FIGS. 6 and 8 to obtain candidate flags B and A in the closed loop.

FIG. 12 is a time chart showing binarized data D, a main scanning line synchronization signal SYNC, a main scanning direction pixel clock CK, a main scanning direction data valid period gate signal XG.

13 is a block diagram showing a configuration of the circuit 100 shown in FIG.

14 is a block diagram showing a configuration of a first flag detector 300 shown in FIG.

15 is a block diagram showing a configuration of a circuit 200 shown in FIG.

16 is a configuration block diagram of a second flag detector 400 shown in FIG.

FIG. 17 shows the output of the circuit 200 directly to the output circuit 500.
FIG. 6 is a block diagram showing an example of an output circuit 500 different from the case where the output of FIG. 3 is shown, showing a means for obtaining image data in which the inside of a closed loop is filled with a specific image pattern.

18A is a plan view showing an example of a closed-loop original image, and FIG. 18B is a plan view showing an example of a reproduced image obtained by performing image recording based on the output signal Y4 of the present invention. ..

19 is a block diagram showing a schematic configuration of an output circuit 500 'different from the output circuit 500 shown in FIG.

20 is a flowchart showing a process (modification 1) which is an alternative to the process of obtaining the candidate flag B shown in FIG.

FIG. 21 is a flowchart showing a process (modification 1) which is an alternative to the process of obtaining the candidate flag A shown in FIG.

22 is a data map of a candidate flag B formed by the processing shown in FIG. 20, showing a part thereof.

FIG. 23 is a data map of a candidate flag A formed by the processing shown in FIG. 21, showing a part thereof.

FIG. 24 is a block diagram showing a schematic configuration of a second flag detector 600 that executes the flowchart shown in FIG. 21.

25 is a flowchart showing another process (modification 2) different from the process shown in FIG.

FIG. 26 is a block diagram showing a data pattern corresponding to PM5 in step b13 of FIG. 25.

27 is a block diagram showing a schematic configuration of a second flag detector 700 that executes the processing shown in FIG.

FIG. 28 is a first candidate flag B different from the processing shown in FIG.
9 is a flowchart of a process (variant 3) for obtaining

FIG. 29 shows “B = C ′” shown in step b27 of FIG.
_-x "is a flowchart showing the processing contents.

30 is a second candidate flag A different from the processing shown in FIG.
9 is a flowchart of a process (variant 3) for obtaining

FIG. 31 shows “A =” shown in step a37 of FIG.
7 is a flowchart showing the processing contents of "C- _y ".

FIG. 32 is a flowchart showing a process (modified example 3) of obtaining a candidate flag C from the second candidate flag A and the first candidate flag B.

FIG. 33 is a data map of the candidate flag B formed by the processing shown in FIGS. 28 and 29, showing a part thereof.

34 is a data map of the candidate flag A formed by the processing shown in FIG. 30 and FIG. 31, showing a part thereof.

FIG. 35 is a data map of the candidate flag C formed by the processing shown in FIG. 32, showing a part thereof.

FIG. 36 shows a candidate flag C and image data D ′ (D ′ is D
To the closed loop fill signal Y
FIG. 2 is a block diagram showing a configuration for obtaining a closed loop inner region signal Y3.

37 is a first candidate flag B different from the processing shown in FIG.
14 is a flowchart of a process (variation 4) for obtaining

38 is a second candidate flag A different from the processing shown in FIG.
14 is a flowchart of a process (variation 4) for obtaining

FIG. 39 is a block diagram showing a pattern of data matching, (a) PM6, (b) PM7, (c).
PM8, (d) PM9, (e) PM11, (f)
PM12, (i) PM13, (j) PM14,
(K) shows PM15, respectively. Also, (g) is shown in FIG.
7 shows a data pattern when it is not "P11" at step b48 of FIG. 7, and (h) shows "P11" at step b50 of FIG.
The data patterns when it is not 12 ”are shown.

FIG. 40 (a) is a case where a plurality of closed loops are in contact, (b) is a case where the closed loops are multiple, (c)
When a part of the loop is open and not a closed loop, (d) is a closed loop having a complicated shape with unevenness,
It is a top view showing an example of the figure.

41A is a plan view showing an example of a figure having a concave portion on the rear end side in the sub-scanning direction, and FIG. 41B is a plan view showing an example of a figure in which closed loops are multiplexed.

[Explanation of symbols]

1: Image reading unit 2: Image processing unit 3: Image recording unit 4: Control unit 5: Operation unit 26: Image processing circuit 100: Circuit for performing first candidate detection of pixels in closed loop
(First Data Forming Means) 200: Circuit for Performing Second Candidate Detection of Pixels in Closed Loop
(Second Data Forming Means) 203, 204: Logic Gate Circuit 300: Detector of Circuit 100 400: Detector of Circuit 200 500: Output Circuit (203, 204, 500: Output Means) 500 ′: Output Circuit 500 Transformation circuit (data conversion means)

Claims (2)

[Claims] 1. A method of sequentially inputting binarized data corresponding to an original image and forming first closed-loop pixel candidate data corresponding to a combination of arbitrary target pixel data and data adjacent to the pixel data. No. 1 data forming unit; sequentially inputs binary data corresponding to an original image, and supports a combination of arbitrary target pixel data and data adjacent to the pixel data, which is different from the combination of the first data forming unit. Second data forming means for forming second closed-loop pixel candidate data; instructing means; and, when instructed by the instructing means, target pixel data, first closed-loop pixel candidate data, and second closed-loop pixel An image processing apparatus comprising: output means for converting data corresponding to a closed loop region or a concave region of a document image into a predetermined value and outputting the data by combining candidate data. 2. The image processing apparatus according to claim 1, further comprising data conversion means for converting data output from the output means into predetermined color image data.