JPH05151353A - Image processor - Google Patents

Abstract

PURPOSE:To express a rugged sense of a shadow in the case of adding a shadow to an original image having ruggedness. CONSTITUTION:By an edge detecting circuit 10, an edge image EO is detected by binarized data DO of an original image A, and by a shadow edge generating circuit 20, a shading edge image group (line image group) Em delayed by an (m) picture element portion in both the (x) and the (y) directions is generated from this edge image EO, plural edge images delayed by an arbitrary picture element portion are synthesized, and a shaded image is synthesized by a shaded image synthesizing circuit 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for adding a solid shadow to an image such as a character.

[0002]

2. Description of the Related Art Generally, when a shadow is added at the lower right of 45 ° to an original image such as characters and symbols, an edge image in which the original image changes from black to white is detected and this edge image is delayed. A shadow image as shown in FIG. 23 can be generated from the image data group. Note that in the example shown in FIG. 23, points E that form an image such as the symbol ("),
In F, G, P, Q, R, line segments GP, PQ, QR,
The edges of RE are detected and the line segments HI, IJ, and J are respectively detected.
A three-dimensional shadow can be added by extending the area to K and KL, and filling the extended area with black or halftone, or with a predetermined color or pattern.

Conventionally, as this type of image processing apparatus, for example, as shown in a conventional example of Japanese Patent Application Laid-Open No. 2-290367, a shadow image or a shadow image area is obtained from an image data group in which image data is delayed, or JP-A-2-290367
As disclosed in the invention of the publication, the shadow area is obtained by delaying or counting the shadow length data.

[0004]

However, in the above-described conventional example, since the shadow area is filled with black or halftone, a predetermined color or pattern, in the example shown in FIG. 23, the uneven points P, Q, R, and That is, the line segment PQ,
The position inside the shadow corresponding to QR cannot be expressed,
There is a problem that there is no unevenness.

In view of the above conventional problems, it is an object of the present invention to provide an image processing apparatus capable of expressing a feeling of unevenness of a shadow when adding a shadow to an original image having unevenness.

[0006]

In order to achieve the above object, a first means is an edge detecting means for detecting an edge of an original image to which a shadow is added, and an unevenness of the edge detected by the edge detecting means. And a shadow generating means for generating a shadow pattern according to the above.

The second means generates a shadow pattern by shifting the edge detected by the edge detecting means in the shadow direction by the shadow generating means of the first means to generate a plurality of line images. Is characterized by.

The third means includes first edge detecting means for detecting a first edge in the first direction of the original image to which a shadow is added, and first edge detecting means for detecting a first edge in the second direction of the original image to which a shadow is added. The second edge detecting means for detecting the second edge and the first and second edges detected by the first and second edge detecting means respectively cause the shadow in the first direction and the shadow in the second direction. And a shadow generating means for generating a shadow so that the shadows are different.

The fourth means is characterized in that the shadow generating means of the first or third means changes the image pattern to generate a shadow.

A fifth means is characterized in that the shadow generating means of the first or third means generates a shadow by changing the image density.

The sixth means is characterized in that the shadow generating means of the first or third means changes the color of the image to generate a shadow.

[0012]

According to the first means, the shadow pattern corresponding to the unevenness of the edge of the original image is generated by the above-described structure, so that the unevenness of the shadow can be expressed when adding the shadow to the original image having unevenness. it can.

In the second means, since the shadow pattern is generated by a plurality of line images generated by shifting the edges of the original image in the shadow direction, the shadow pattern is added when the shadow is added to the original image having irregularities. The unevenness can be expressed by a plurality of line images.

According to the third means, since the shadows of the edges having different directions are different, the unevenness of the shadow can be expressed by different shadows when adding the shadow to the original image having unevenness.

According to the fourth means, since the shadow is generated by changing the image pattern, the unevenness of the shadow can be expressed by different image patterns when adding the shadow to the original image having unevenness. ..

In the fifth means, since the shadow is generated by changing the image density, when adding the shadow to the original image having unevenness, the unevenness of the shadow can be expressed with different image density. ..

In the sixth means, since the shadow is generated by changing the color of the image, the unevenness of the shadow can be expressed by different colors when adding the shadow to the original image having unevenness. ..

[0018]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention, FIG. 2 is a perspective view for explaining the outline of a digital copying machine equipped with the image processing apparatus of FIG. 1, and FIG. FIG. 4 is a block diagram for explaining the flow of image data and a control signal in the digital copying machine, FIG. 4 is an explanatory diagram showing the scanning direction of the reading section of FIG. 2, and FIG. 5 is an explanation showing image data of symbols to which shadows are added. 6 is an explanatory diagram showing a shaded image, FIG. 7 is an explanatory diagram showing an edge image of the shaded image of FIG. 6, FIG. 8 is a block diagram showing a detailed configuration of the edge detection circuit of FIG. 1, and FIG. 1 is a block diagram showing a detailed configuration of an edge image group generation circuit of the shadow edge generation circuit of FIG. 1, and FIG. 10 is a block diagram showing a detailed configuration of an edge image group synthesis circuit of the shadow edge generation circuit of FIG. FIG. 11 shows a detailed configuration of the shaded image synthesizing circuit of FIG. It is a block diagram.

First, the configuration of a digital copying machine to which the image processing apparatus of this embodiment is applied will be described with reference to FIGS. The document to be image-processed is placed on the document table 1 with its reading surface facing downward, and read by the reading unit 2. Although the detailed configuration of the reading unit 2 is omitted in the drawing, a light source for illuminating the original, a CCD image sensor for main scanning the original in the main scanning (x) direction, an original and a CCD image sensor are provided. It has a mechanism system or the like for relatively moving in the sub-scanning (y) direction to scan the document in the sub-scanning direction. In the reading unit 2, the image signal read by the CCD image sensor is also amplified and
/ D conversion is performed, and shading correction is performed according to the light amount unevenness of the light source and the sensitivity error of the CCD image sensor.

The image data read by the reading unit 2 is subjected to filter processing, scaling processing, γ conversion, gradation processing, etc. according to the characteristics of the original image by the image processing unit 3 and will be described later. A three-dimensional shadow is added to the image such as characters and is recorded on the recording paper by the writing unit 4. The writing unit 4 is composed of an electrophotographic laser beam printer, which modulates image data with a laser beam to form an electrostatic latent image on a photoconductor and then develops it with toner, and the toner images are formed into cassettes 4a and 4b. It is transferred to the recording paper set in advance and fixed. The operation unit 5 can preset various conditions of the three-dimensional shadow addition mode in addition to the gradation processing mode, the recordable density, the scaling factor, etc., and the control unit 6 can set various conditions set through the operation unit 5. The reading unit 2, the image processing unit 3, and the writing unit 4 are controlled accordingly.

Next, the configuration of the image processing unit 3 of this embodiment will be described with reference to FIGS. 1 and 4 to 11. Reading unit 2
As shown in FIG. 4, when a document is read line by line with a CCD image sensor and an image A on the document is read, as shown in FIG. 5, it is read for each pixel like a grid divided in the xy directions. Although only the outer frame of the image A is shown in FIG. 4, the points E, F, and
The inner area of the image A surrounded by G, P, Q, and R is black.

The edge detection circuit 10 shown in FIG.
The edge image E0 of the line segments GP, PQ, QR, RE shaded in the original image A is detected as shown in FIG. Note that the image Em in FIG. 7, an image E ₀ x, both m (m = 1,2~) in the y-direction shows an edge image for with shadow delayed by pixels, the shadow image E _m is Figure When an edge image delayed by an arbitrary pixel is combined as shown in FIG. 6, it can be expressed by the logical expression of Expression 1.

[0023]

## EQU1 ## K = (E ₃ + E ₄ ) + (E ₇ + E ₈ ) + (E ₁₁ + E ₁₂ ) + ... + (E ₂₇ + E ₂₈ ) + (E ₃₁ + E ₃₂ ) (However, the symbol “+” is A detailed structure of the edge detection circuit 10 will be described with reference to FIG. 8. Binary data (black = “1”, white = “0” of the original image A read by the reading unit 2 is described. )) D
₀ is first delayed by one line by the one-line delay buffer 11 and then output to one input terminal of the AND gate 12. Therefore, the signal at the output terminal of the 1-line delay buffer 11 has the same pixel position in the x direction as the signal at the input terminal D _i , and is the pixel data one line before in the y direction. The 1-line delay buffer 11 is, for example, a FIFO memory “μPD42505” of NEC Corporation.
It can be realized by "C".

The binarized data D0 is also sent to the inverter 13
Is output to the other input terminal of the AND gate 12 and one input terminal of the AND gate 15 via the
₀ is further delayed by one pixel by the pixel clock CK by the D flip-flop 14 and output to the other input terminal of the AND gate 15. The output signals of the AND gates 12 and 15 are output to the edge image E ₀ via the OR gate 16.

That is, since the AND gate 12 outputs the logical product signal "1" when the current pixel is "0" and the pixel one line before is "1", the AND line 12 has the line segments PQ and RE shown in FIG. Then, the edge image in the sub-scanning direction is detected. Also, A
Since the ND gate 12 outputs a logical product signal "1" when the current pixel is "0" and the previous pixel is "1",
An edge image in the main scanning direction is detected like line segments GP and QR shown in FIG. Therefore, the OR gate 16 outputs the edge image E _{0 in} both directions by the logical sum of the edge images in the main scanning direction and the sub scanning direction.

In the shadow edge generation circuit 20 shown in FIG.
Edge image E detected by the edge detection circuit 10
_{From 0} , as shown in FIG. 7, a shadowing edge image group (line image group) E delayed by m pixels in both the x and y directions
_m is generated and synthesized. This shadow edge generation circuit 2
The detailed configuration of 0 will be described with reference to FIGS. 9 and 10. The edge image E ₀ of the original image A is first delayed by one line by the one-line delay buffer 201, and then
1 by pixel clock CK by D flip-flop 211
It is delayed by the number of pixels and output as a signal E ₁ . That is, the output signal E ₁ is a line image that is shifted from the input signal E ₀ by one pixel in the xy directions.

The signal E ₁ is delayed by 1 line by the 1-line delay buffer 202 and then delayed by 1 pixel by the pixel clock CK by the D flip-flop 212, so that it is 2 in both the xy direction and the input signal E ₀ . The line image E ₂ shifted by the pixel is output. Therefore, by providing the 1-line delay buffer 201 and the D flip-flops 211 in a plurality of stages, signals E1 to Em that are shifted by 1 to _m pixels are provided.
Is output.

When a plurality of edge images delayed by arbitrary pixels are combined as shown in FIG. 6, they can be combined by an OR signal of the OR gate 220 as shown in FIG. K is represented by the above-mentioned equation 1. The synthesized signal K and the signal D ₀ of the original image A can be synthesized by the OR gate 301 as shown in FIG. 11, and the shaded image as shown in FIG. 6 can be generated by the synthesized signal DK. You can The composite signal DK of the shaded image is output to the writing unit 4 shown in FIG. 3 and recorded on recording paper.

Therefore, according to the above embodiment, the edge detection circuit 10 causes the binarized data D of the original image A to be obtained.
_The edge image E ₀ is detected by ₀ , and the shadow edge generation circuit 20 outputs m from the edge image E ₀ in both the x and y directions.
An edge image group E _m for shadowing delayed by pixels is generated to synthesize a plurality of edge images delayed by arbitrary pixels, and a shadowed character is synthesized by the OR gate 301 of the shaded image synthesis circuit 30. Therefore, as shown in FIG. 6, the concave / convex points of the original image A, that is, the positions inside the shadow corresponding to the line segments PQ and QR can be expressed.

FIG. 12 shows shaded characters in the second embodiment. In FIG. 12, D ₀ is the original image, D ₁ ,
D ₄ , D ₇ are white areas, D ₂ , D ₃ , D ₅ , D ₆ , D ₈ ,
D ₉ indicates a black area, and the black and white areas D _{1 to} D ₉ and the black areas D ₂ , D ₃ , D ₅ , D ₆ , D ₈ and D ₉ form a shadow of the original image D ₀ . In this embodiment, without generating an edge image group E _m for the edge image E ₀ and shadow of the original image A, the delay signal D _{m (m} = 1,2 by binary data D ₀ of the original image A, 3) is generated, and a black and white shadow can be formed by the delayed signal D _m . The shadow image in this case can be expressed by the logical expression shown in the following expression (2). The mathematical expression 3 in the mathematical expression 2 is a kind of logical expression for shadowing in the conventional example shown in FIG.
4 is a logical expression for generating white areas D1, D4, D7 having a shape similar to the edge image E0.

[0031]

[Equation 2]

[0032]

[Equation 3]

[0033]

[Equation 4]

As a method of generating the delay signal D _m from the binarized data D ₀ of the original image A, in the first embodiment, a circuit (FIG. 9) for generating the edge image group E _m for shadowing is used. Can be done, and K shown in Equation 2
Can be easily generated by combining AND and OR logic circuits.

The present invention is not limited to the logical expressions and logical circuits described in the above embodiments and the direction and length of the shadow, and various modifications are possible. Further, the density and color of the shadow image can be changed. For example, as shown in FIG. 13, the interval for thinning the shadow image from the shadow region to form a white region is associated with the magnitude of the delay amount from the original image D _0. As a result, it is possible to generate a dynamic shaded image with a feeling of unevenness.

Next, a third embodiment will be described with reference to FIGS. FIG. 14 is an explanatory diagram showing a shaded image,
FIG. 15 is an explanatory diagram showing an operation of generating a right edge image for shadow, FIG. 16 is an explanatory diagram showing an operation of generating a lower edge image for shadow, and FIG. 17 is a left and bottom edge image of the original image. FIG. 18 is a block diagram showing an edge detection circuit for detection.
Is a block diagram showing a pattern area generating circuit, FIG. 19 is a block diagram showing a shaded image synthesizing circuit, FIG. 20 is an explanatory diagram showing a first pattern, FIG. 21 is an explanatory diagram showing a second pattern, and FIG. It is a block diagram showing an address generation circuit of the pattern generation circuit.

In the third embodiment, as shown in FIG. 14, a rightward shadow is formed by the first pattern RK and a downward shadow is formed by the second pattern UK, so that edges of different directions are formed. The shadows are formed to have different patterns RK _and UK. Since humans have the visual characteristic that the area ratio of white and black in a small area is perceived as the overall density, the uneven points P of the original image D,
The first pattern RK and the second pattern are drawn inside the shadows corresponding to Q and R.
Since it can be expressed as a boundary line of the pattern UK, it is possible to express a shaded image having unevenness even inside the shadow.

Next, the configuration and operation of the third embodiment will be described in detail. First, as shown in FIG. 15, a shadow delayed from the right edge image DR of the original image D by m pixels in both the x and y directions. First right edge image DR _m up to
Region of the pattern RK of the original image D is generated from the lower edge image DU of the original image D as shown in FIG.
Lower edge image DU for shadow delayed by m pixels in both directions
Regions of the second pattern UK up to _m are generated.

This circuit configuration will be described with reference to FIGS. 17 and 18. First, the edge detection circuit 10 shown in FIG.
The left edge image DR and the lower edge image DU of the original image are independently detected by a. That is, the signal of the original image D is delayed by one pixel by the pixel clock CK by the D flip-flop 101, and then the AND gate 102.
Applied to one input terminal of the
Is applied to the other input terminal of the AND gate 102 and one input terminal of the AND gate 106 having a three-terminal input, and after being delayed by the one-line delay element 104, applied to one input terminal of the AND gate 106. To be done.

The left edge image signal DR of the AND gate 102 is applied to one input terminal of the AND gate 106 via the inverter 105, and the AND gate 10
From 6, the lower edge image signal DU is output. Since this operation is almost the same as the operation of the edge detection circuit 10 shown in FIG. 8, a detailed description thereof will be omitted, but the inverter 105
Is the right edge and the bottom edge, AND gate 1
06 is used so as not to output the lower edge image signal DU. Then, the pattern region generation circuit 40 shown in FIG. 18 generates the region signal DRK for the shadow of the right edge from the left edge image signal DR. In addition, the 1-line delay elements 201 and 202 of the preceding stage and the D flip-flop 21.
1 to 212 are the same as the shadow edge generation circuit 20 shown in FIG.
Are generated edge images DR ₁ and DR ₂ for shadowing delayed from the left edge image signal DR by m (m = 1, 2 ...) Pixels in both the x and y directions. Therefore, the edge images DR ₁ and DR ₂ for shadows are OR gates 22.
The logical sum of 1 can be combined into the shadow region signal DRK of the right edge. Although not shown, a similar circuit can be used to combine the lower edge image signal DU into the shadow edge area signal DUK of the lower edge, and the respective logical expressions are shown in Expressions 5 and 6, respectively.

[0041]

## EQU00005 ## DRK = DR ₁ + DR ₂ + ... DR _m + ... + DR _M

[0042]

[6] _{DUK = DU 1 + DU 2 +} ... DU m + ... + DU M Next, explaining the shaded image synthesizing circuit 30a with reference to FIGS. 19 to 22, the pattern generating circuit _41, 42,
According to the pixel address signals in the x and y directions from the address generation circuit shown in FIG. 22, the first pattern R having 2 × 2 pixels as one unit as shown in FIGS.
K and the second pattern UK are repeatedly generated. Then, this first pattern RK is AND gate 43 by the area signal DRK for the shadow of the right edge.
The second pattern UK is output from the AND gate 44 by the area signal DUK for the shadow of the lower edge, and then the original image D is output by the OR gate 45.
And the rightward shadow of the first pattern RK and the downward shadow of the second pattern UK are combined.

In the address generating circuit shown in FIG. 22, the signal X ₀ which is the least significant bit LSB of the pixel address signal in the x direction and the signal Y ₀ which is the least significant bit LSB of the pixel address signal in the y direction are exclusive. Logical OR signal is XOR
Applied to the pattern generation circuit 41 through the gate 46,
The logical sum signal of the signals X _{0 and} Y ₀ is applied to the pattern generation circuit 42 via the AND gate 47. Therefore, the pattern generating circuit 41 generates the first pattern RK as shown in FIG. 20, and the pattern generating circuit 42 generates the second pattern UK as shown in FIG.

Therefore, in the third embodiment as well, the rightward shadow of the original image D is formed by the first pattern RK and the downward shadow is formed by the second pattern UK. As shown, it is possible to represent the positions inside the shadow corresponding to the uneven points P _, Q _, R of the original image A _, that is, the line segments PQ _, QR.

Similarly, in the case of the third embodiment, various modifications are possible without being limited to the logical expression, the logical circuit, the direction and length of the shadow, and FIGS. 20 and 21. The pattern is not limited to the pattern shown in (1), and the shadow and the color of the shadow image may be changed to express shadows having different directions. In addition, in the third embodiment, the shadow image is generated by the binarized data of the original image. However, a device having multi-valued image data capable of expressing the gradation of the density or a multi-valued image data is used. A device having a recordable writing unit can represent shadows in different directions with different densities.

[0046]

As described above, the invention according to claim 1 responds to the edge detecting means for detecting the edge of the original image to which the shadow is added, and the unevenness of the edge detected by the edge detecting means. Since the shadow generating means for generating a shadow pattern is provided, it is possible to express the unevenness of the shadow when adding the shadow to the original image having the unevenness.

According to a second aspect of the present invention, the shadow generation means according to the first aspect shifts the edges detected by the edge detection means in the shadow direction to generate a plurality of line images, thereby generating a shadow pattern. Therefore, when a shadow is added to an original image having unevenness, the unevenness of the shadow can be expressed by a plurality of line images.

According to a third aspect of the present invention, first edge detecting means for detecting a first edge in the first direction of the original image to which a shadow is added, and second edge detecting means of the original image to which a shadow is added. The second edge detecting means for detecting the second edge in the first direction and the first and second edges detected by the first and second edge detecting means respectively cause the shadow and the second shadow in the first direction. Since the shadow generating means for generating a shadow so that the shadows in different directions are provided is provided, the unevenness of the shadow can be expressed by different shadows when adding a shadow to an original image having unevenness.

The invention according to claim 4 is the invention according to claim 1 or 3.
Since the described shadow generating unit generates a shadow by changing the image pattern, when the shadow is added to the original image having the unevenness, the unevenness of the shadow can be expressed by different image patterns.

The invention according to claim 5 is the invention according to claim 1 or 3.
Since the described shadow generation means generates a shadow by changing the image density, when adding a shadow to an original image having unevenness, the unevenness of the shadow can be expressed with different image densities.

The invention according to claim 6 is the same as claim 1 or 3
Since the described shadow generating means generates a shadow by changing the color of the image, the unevenness of the shadow can be expressed by different colors when adding the shadow to the original image having unevenness.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a perspective view for explaining the outline of a digital copying machine including the image processing apparatus of FIG.

3 is a block diagram for explaining the flow of image data and control signals in the digital copying machine of FIG.

FIG. 4 is an explanatory diagram showing a scanning direction of a reading unit in FIG.

FIG. 5 is an explanatory diagram showing image data of a symbol to which a shadow is added.

FIG. 6 is an explanatory diagram showing a shaded image.

7 is an explanatory diagram showing an edge image of the shaded image of FIG.

FIG. 8 is a block diagram showing a detailed configuration of the edge detection circuit of FIG.

9 is a block diagram showing a detailed configuration of an edge image group generation circuit of the shadow edge generation circuit of FIG.

10 is a block diagram showing a detailed configuration of an edge image group combining circuit of the shadow edge generating circuit of FIG.

11 is a block diagram showing a detailed configuration of a shaded image synthesizing circuit in FIG. 1. FIG.

FIG. 12 is an explanatory diagram showing a shaded image of the second embodiment.

FIG. 13 is an explanatory diagram showing a modified example of the shaded image of the second embodiment.

FIG. 14 is an explanatory diagram showing a shaded image of the third embodiment.

FIG. 15 is an explanatory diagram showing an operation of generating a right edge image for a shadow.

FIG. 16 is an explanatory diagram showing an operation of generating a lower edge image for shadow.

FIG. 17 is a block diagram showing an edge detection circuit that detects edge images on the left and bottom of the original image.

FIG. 18 is a block diagram showing a pattern area generation circuit.

FIG. 19 is a block diagram showing a shaded image combining circuit.

FIG. 20 is an explanatory diagram showing a first pattern.

FIG. 21 is an explanatory diagram showing a second pattern.

FIG. 22 is a block diagram showing an address generation circuit of the pattern generation circuit.

FIG. 23 is an explanatory diagram showing a shaded image in a conventional example.

[Explanation of symbols]

 10, 10a Edge detection circuit 20 Shadow edge generation circuit 30, 30a Shadowed image composition circuit 40 Pattern area generation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 1/387 8839-5C // G09G 5/36 8121-5G

Claims (6)

[Claims] 1. An image processing device for forming a shadow image in a region shifted from at least a part of an original image in a certain direction, the edge detecting means detecting an edge of an original image to which a shadow is added, and the edge detection. An image processing apparatus, comprising: a shadow generation unit that generates a shadow pattern according to the unevenness of the edges detected by the unit. 2. The shadow generating means generates a shadow pattern by shifting an edge detected by the edge detecting means in a shadow direction to generate a plurality of line images. The image processing device described. 3. An image processing apparatus for forming a shadow image in a region shifted in a certain direction from at least a part of an original image, wherein a first edge in a first direction of the original image to which a shadow is added is detected. First edge detecting means, second edge detecting means for detecting a second edge in the second direction of the original image to which a shadow is added, and the first and second edge detecting means respectively detect the second edge. An image processing apparatus comprising: a first and a second edge; and a shadow generating unit that generates a shadow so that the shadow in the first direction and the shadow in the second direction are different from each other. 4. The shadow generating means generates a shadow by changing an image pattern.
5. The image processing device according to any one of 3 and 3. 5. The image processing apparatus according to claim 1, wherein the shadow generating unit generates a shadow by changing an image density. 6. The image processing apparatus according to claim 1, wherein the shadow generation unit generates a shadow by changing a color of the image.