JP3021073B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and, more particularly, to an image processing method for processing an image signal having a frame around an image.

[0002]

2. Description of the Related Art Conventionally, in a microfilm having a negative image, a negative image is recorded in a frame f of a microfilm F as shown in FIG. 28A, and the periphery of each frame f becomes transparent. I have. When this microfilm F is printed out by a negative-positive reversal information recording device, the transparent portion around the frame f is developed. As a result, as shown in FIG. 28B, a solid black frame B is printed around the image area G on the transfer material P, which not only impairs the appearance of the printed image but also increases the toner consumption. There was a problem.

In order to solve the above problem, an area of the image frame f of the microfilm F is detected, and an area to be recorded on the transfer material P is controlled based on an area determined based on the image area. As a result, an information recording apparatus has been proposed in which a print without a frame portion is obtained as shown in FIG.

In this apparatus, image reading information at the time of image scanning is binarized by a predetermined threshold value and stored in a memory such as a RAM. This information is, for example, as shown in FIG. 29, where L _X and L _Y in the figure correspond to the horizontal and vertical lengths of the transfer paper P, respectively.

[0005] Then, the arithmetic circuit such as the CPU in order from the bit sequence of l ₁ data in RAM, which performs a determination of whether the first column contains all 0 or 1, one column are all 0
, This determination is sequentially repeated as l ₁ , l ₂ , l ₃ .
Then (l ₆ in the illustrated example) first when found columns l _n containing 1, CPU is the value L _F of the image recording region and n.

Further, the above operation is similarly performed at the left end and the upper and lower ends of the image area G, and the image recording areas l _x1 , l _x
Y and _lY2 are determined.

[0007]

However, the above conventional example has the following disadvantages.

R for storing image information of the entire image area
Because AM is required, a large amount of RAM is required,
The device is expensive and bulky.

Further, since it is necessary to store the image information in the shared memory, it takes a long processing time.

[0010] Since only a rectangular frame can be erased, FIG.
A frame remains when the image is inclined as shown in FIG. Further, when there are two or more images in one screen, a frame remains between them as shown in FIG. 30B, so that the image quality may be degraded.

After the frame is erased, the size and position of the image portion (or the original) are not well understood because the interval of the image portion is unclear as shown in FIG.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has an input means for inputting an image signal representing an image and a peripheral portion thereof, and an image signal input from the input means. Detecting means for detecting a boundary between the image and the peripheral part, converting means for converting an image signal outside the boundary detected by the detecting means into a specific signal, and detecting the boundary detected by the detecting means. And a forming means for forming an image signal representing a frame corresponding to the image processing apparatus.

[0013]

FIG. 1 is an external view of the present invention applied to a digital film reader printer for microfilm, and FIG.
Shows a schematic mechanism diagram thereof.

In FIGS. 1 and 2, reference numeral 1 denotes a scanner for projecting or reading a microfilm on a screen to perform image processing and the like. 2 denotes a scanner for processing image information read by the scanner 1 and then printing it out on plain paper. A laser beam printer, 3 is an operation unit for performing various settings and display, and 4 is a roll carrier having a mechanism for sending and rewinding a photographed image of a roll film to a projection position by using a knob on the operation unit 3. Reference numeral 5 denotes a projection zoom lens having a zoom mechanism, 6 denotes a screen for projecting a microfilm image, 7 denotes a halogen lamp for irradiating the microfilm, and 8 denotes a diffused light of the halogen lamp. The condenser lens 9 is a microfilm sandwiched by a pressure plate glass (not shown) in a roll carrier, Is a reflection mirror for reflecting the projection light, 11 is a sliding mirror for selecting between screen projection and projection image reading, 12 is an axis for rotating the sliding mirror 11, and 13 is for reading a projection image. Are line sensors 14 and 15 for detecting the position of the line sensor.

The operation of image reading in the above configuration will be described.

First, the sliding mirror 11 is usually located at a position shown by a broken line. At this time, the light irradiated on the microfilm 9 by the halogen lamp 7 and the condenser lens 8 is reflected by the reflection mirror 1.
0, projected on the screen 6 through the sliding mirror 11 (broken light path).

When a copy button provided on the operation unit 3 is pressed, first, the sliding mirror 11 moves to a position indicated by a solid line about the axis 12, and the microfilm projection light follows the optical path indicated by the solid line. At this time, the line sensor 13 separates from the home position sensor 14 and starts moving in the direction A (this direction is hereinafter referred to as a previous scan). When the line sensor 13 moves to the end position of the image light, the line sensor 13 is applied to the start position sensor 15 and starts reversing movement in the direction B (hereinafter, this direction is referred to as main scan). Thereafter, when the line sensor 13 reaches the home position 14, the movement of the line sensor 13 stops, and the sliding mirror 11 returns to the position indicated by the broken line.

FIG. 3 is a schematic block diagram of an embodiment of the present invention, and FIG. 4 is an image processing circuit 26 and a frame detection circuit 24.
The detailed block diagram of FIG. In the following description, the inversion of the signal is represented by * (for example, the inversion of the signal A is represented by the signal A).
*)

In FIG. 3, reference numeral 21 denotes the line sensor 1.
3, an amplifier for amplifying the image signal output; and 22, an A for converting the output signal of the amplifier into a digital 8-bit signal.
A / D converter 23, a shading correction circuit for shading correction of the digitized image signal,
24 is a frame detection circuit for detecting a frame of an image from the shading-corrected image signal, 25 is a data setting control for the frame detection circuit, and reads the setting of the operation unit,
Alternatively, the CPU 26 for performing display or the like is an image processing circuit that performs various image processing on the image signal subjected to shading correction.

Next, an image processing circuit 26 and a frame detection circuit 24
Will be described with reference to FIG.

Reference numeral 101 denotes a binarization circuit for simply binarizing an original image signal VM having 8-bit gradation, 102 a block bit addition circuit for bit-wise adding the binarized image signal VMB, Reference numeral 103 denotes a binarization circuit for determining the value obtained by adding the block bits, reference numeral 104 denotes a signal binarized by the binarization circuit 103, and a detection signal for detecting a boundary point between the image portion and the frame portion by using the SIG. MBI, MBI
This is a detection signal generation circuit for generating T.

Reference numeral 105 denotes a 13-bit counter which counts by the image block GCLK in synchronization with the main scanning direction synchronizing signal. Reference numeral 106 denotes an address correction circuit for correcting a delay (K) in the main scanning direction that occurs at the time of blocking. A 13-bit adder 107 is a picture section rising address latch circuit that latches an address in the main scanning direction at the rising edge of the detection signal MBIT, and 108 is an image section rising address latch circuit that latches an address in the main scanning direction at the rising edge of the detection signal MBI. This is a downstream address latch circuit.

Reference numeral 109 denotes a synchronizing signal HS generated for each T line.
A T line latch circuit for latching and delaying the output address signal NB of the rising address latch circuit 107 in response to the YNT signal, and a T line latch circuit 110 for latching the output address signal NA of 108 in response to the HSYNT signal.

Reference numeral 11 denotes an address / timing conversion circuit A, which generates timing based on NB and NA address signals.
Reference numeral 12 denotes an address / timing conversion circuit B for generating timing from the output signals PB and PA of 109 and 110.

Reference numerals 113 to 117 denote gate circuits, which will be described later in detail.

Reference numeral 118 denotes an edge emphasizing circuit for emphasizing the edge of the original image signal VM. 119, an error diffusion circuit for further performing pseudo halftone processing on the edge-enhanced 8-bit gradation image signal by an error diffusion method. Reference numeral denotes an image delay circuit for correcting a delay in the sub-scanning direction that occurs at the time of blocking.

FIG. 5 is a schematic circuit diagram showing an example of the block bit addition circuit 102. Reference numeral 121 denotes a GCKW signal as shown in FIG. (In FIG. 16, one block is formed for every eight pixels.) Latch circuits for engraving are provided. 122 to 129 are line memories that are cleared in each cycle of the HSYNC signal. 130 is an output signal VMB 'of the latch circuit 121 and line memories 122 to 122. Addition circuits A and 131-138 for adding the outputs (a-i) of the 129 are latch circuits for latching the 4-bit output of the addition circuit A130 with the GCKW signal;
Reference numeral 9 denotes the output of the adder circuit A130 and the latch circuits 131 to 13
8 is an adder circuit B for adding the outputs (A to I) of FIG.

FIG. 6 is a circuit diagram showing an example of the adder circuit A130. Reference numerals 48, 49, 50, 51 and 52 denote 1-bit full adders, and 53 and 54 denote 1-bit half adders.

FIG. 7 is a circuit diagram showing an example of the adder circuit B139. Reference numerals 55, 56, 57 and 58 denote 4-bit adders,
9, 60 is a 5-bit adder, 61 is a 6-bit adder, 6
2 is a 7-bit adder.

FIG. 8 is a circuit diagram showing an example of the detection signal generation circuit 104. Reference numeral 41 denotes a binarization circuit
An AND gate for ANDing the coded signal SIG and the frame erasing area signal AREA, and 42 is an AND gate 4
D-latch 43, which is connected to the output of the image clock signal G1 to generate an MBI signal that is inverted by the image clock signal GCLK.
This is a JK flip-flop for generating an MBIT signal that rises at the first rise of the G signal and falls at the fall of the next HSYNC * signal.

FIG. 9 shows a rising address latch circuit 107.
44 is a circuit diagram showing an example of a falling address latch circuit 108, 44 is a D latch that latches at the rising edge of the MBIT signal, 45 is a D latch that further latches the signal at the rising edge of the HSYNT signal, and 46 is a latching latch at the rising edge of the MBI signal The D latch 47 is a D latch that further latches the signal at the rising edge of the HSYNT signal.

FIG. 10 is a circuit diagram showing an example of the address / timing conversion circuit A111. Reference numeral 63 denotes a 13-bit adder for calculating an address obtained by subtracting the dot width D of the black frame in the main scanning direction from address NB, and reference numeral 64 denotes the same. Address N
1 for calculating the address obtained by adding the dot width D from A
A 3-bit adder, 65-68, outputs 1GCLK when the address of each A input matches the count address in the main scanning direction.
The 13-bit equality comparators 69 and 70 that output the minute pulses are NL from the pulses from the comparators 65 and 67 and the pulses from the comparators 66 and 68, respectively.
This is a JK flip-flop for generating M and NL signals.

FIG. 11 shows an address / timing conversion circuit B.
FIG. 12 is a circuit diagram showing an example of the circuit 112, and the connection is the same as that in FIG.

Reference numerals 71 and 72 denote 13-bit adders, 73 to
76 is a 13-bit equality comparator 77, 78
Is a JK flip-flop.

12 to 14 are schematic circuit diagrams showing an example of the delay circuit. Reference numeral 81 denotes a serial-to-parallel conversion circuit for serially converting the binary image signal VDI, reference numeral 82 denotes latches for latching at the rising edge of the SPCLK signal, and reference numerals 83 and 84. Is RAM
(1) a three-state gate circuit for selecting an output signal to the 95 or the RAM (2) 96; 85, an inverter; 86, an 8-bit selector for selecting an input signal from the RAM (1) 95 or the RAM (2) 96; 87 is a latch for latching the output of the 8-bit selector at the rising edge of the PSLAT signal, 88 is a parallel-to-serial conversion circuit for parallel-to-serial conversion of the output of the latch 87, 89 is a RAM (1) 95, RA
M1RD that controls writing and reading to M (2) 96
*, M1WR *, M2RD *, M2WR * A selector which is a signal generation circuit.

90 is a latch for setting the line count number, 91 is an 8-bit equality comparator that compares the output of the 8-bit counter 93 and outputs a pulse when they match, 92 is an inverter, 94 is an 8-bit equality comparator Is a JK flip-flop for generating an inverted signal MSEL for each output.

The operation will be described below step by step.

The original image signal VM has passed through basic correction circuits such as shading correction and gamma correction as shown in FIG. 3, for example, and has undergone some filtering processing.

The original image signal VM is defined as a value of refl, (r
efl is linked to the photometric value by the prescan), and is converted into a binary signal of 1 or 0 by the binarization circuit 101. The block corresponding to one point X on the image has 9 × 9 sample points as shown in FIG. 22. Each sample point has a GCKW signal interval (8 pixels here) in the main scanning direction and a sub scanning direction. HSYNW signals are separated by an interval (here, eight pixels). Therefore, the size of the block is 64 × 64 pixels.

Dust and dust on the microfilm are magnified by the enlargement magnification. However, if dust is present in the frame portion, if the judgment block is small, malfunction may occur due to the enlarged dust and dust. However, it is an effective method to have discrete sampling points in order to eliminate the malfunction of dust and dust with a minimum memory since the larger the determination block is, the more memory is required.

With this size, for example, when a 400 dpi sensor is used, a malfunction does not occur even for an enlarged dust and dust having a width of about 2 mm.

FIG. 5 shows the block bit addition circuit 102, which is an image signal VM converted by the binarization circuit 101.
B is sliced at the rising edge of the GCKW signal by the D latch 121, and is sequentially stored by the line memories 122 to 129 at intervals of the HSYNCW signal.

The signals of nine lines (a to i) are
Bit addition is performed at intervals of the CKW signal. For example, FIG.
When the signals a to i are output as shown in FIG.
The 4-bit output of output A of 0 (FIG. 6) is as shown in the figure.

Further, 4-bit latches 131 to 138 sequentially store data at intervals of GCKW signals in the main scanning direction. Then, the sum of the bit addition signals for nine lines at points A to I is calculated by the addition circuit B139. At this time, the 4-bit signals A to I are as shown in FIG. 18 when considered along FIG. Then, the summation circuit B139 (FIG. 7)
Output SUM results in the result shown by SUM in FIG.

The adder circuit A130 is, for example, as shown in FIG. 6. The signals a, b and c are added by a 1-bit full adder 48 and converted into a 2-bit signal. Similarly, the signals of d, e, and f are added by a 1-bit full adder 49 and converted into a 2-bit signal. Further, the signals of g, h, and i are added by a 1-bit full adder 50 and converted into a 2-bit signal.

The upper 1 bit and lower 1 bit of each 2-bit converted signal are separately operated by 1-bit full adders 51 and 25, and further converted to 4-bit signals by half adders 53 and 54 (maximum 9).

The adder circuit B139, for example, as shown in FIG. 7, adds 4-bit signals A and B, C and D, E and F, and G and H first by using 4-bit adders 55 to 58, respectively. ,
The signal is converted into 5 bits, and the 5-bit signal is added by 5-bit adders 59 and 60 to be converted into 6 bits.
The 6-bit signal is added by a 6-bit adder 61, converted into 7 bits, and finally a 4-bit signal of I is added by a 7-bit adder 62, and the sum SUM of A to I is added.
Is output.

The SUM obtained in this way is a binarizing circuit 1
03, the binary signal S of 1 or 0 as compared with ref2
Convert to IG. Therefore, since this SIG is a signal obtained on average from the surrounding pixels, it has the effect of applying a large-area low-pass filter, and is a stable signal against noise and dust. I have.

Next, the signal SIG is limited by the AND gate 41 by the frame erasing area signal AREA in the detection signal generating circuit 104 shown in FIG.
The image falling detection signal MBI is output by the flip-flop 43.
And an image rising detection signal MBIT is generated. Basically MBI
T rises at the first rising point of the SIG and falls at the next rising edge of the HSYNC signal in order to catch the edge of the image portion coming first from the main scanning synchronization signal HSYNC in terms of timing. In addition, the MBI inverts the SIG in order to catch the edge of the last image portion as viewed from HSYNC.

The 13-bit counter 105 is a synchronous counter, which is cleared by the HSYNC * signal as shown in FIG. 15, and counts up at the rising edge of GCLK. 13 bits is a bit number assuming main scanning of 400 dpi A3 size, and differs depending on the resolution of the sensor and the image reading width.

Although the blocking causes a delay in both the main scanning and the sub-scanning, the address is corrected in the main scanning direction by correcting the address using the 13-bit adder 106. The correction value is K, but the following timing is K for convenience.
= 0. The address value of the main scanning direction counter corrected in this way is set to HAD.

Address latch circuits 107, 1 shown in FIG.
At 08, when an image is present, the H latch signal is latched once per line by the D latches 44 and 46, and the HAD signal is latched once at least by the MBI signal. For synchronization, the outputs of the D latches 44 and 46 are latched again by the D latches 45 and 47 at the rising edge of the HSYNT signal. The address signal thus latched is N
B, NA. Then, the address signals NB, NA
Are further latched at the rising edge of the HSYNT signal are the address signals PB and PA.

Then, in the address / timing conversion circuit A111 shown in FIG. 10, the address of NB-D is calculated by the 13-bit adder 63, and the address of NA + D is calculated by the same 13-bit adder 64. At the timing when the address values of NB-D, NB, NA + D, and NA match the address value HAD of the main scanning direction counter, the 13-bit equality comparator 6
Pulses are output from 5-68. Then, by the JK flip-flops 69 and 70, the NLM signal rises at the output of the 13-bit equality comparator 65, falls at the output of the 13-bit equality comparator 67, and rises at the output of the 13-bit equality comparator 66. An NL signal falling at the output of the parity comparator 68 is output.

Similarly, PLM and PL signals are output from the address signals PB and PA by the address / timing conversion circuit 112 shown in FIG.

FIGS. 19 and 20 are timing charts showing the process of forming a black frame at the edge of the image portion (hereinafter referred to as HS).
YNT is HSYNC (one line)).

In FIG. 19, the top signal is HSYNC *,
Pulses falling at an interval of one pulse (two GCLK cycles) are output to one line. The image area is HSYNC *
It exists between the signal pulses, but in relation to the printer,
One ordinary line has a clock timing equal to or longer than the image reading width, and non-image areas exist before and after the image area.

FIG. 19 is a timing when an image appears from a state where there is no image in the sub-scanning direction.
The signal becomes 1. However, in the image portion, the SIG signal sometimes becomes 0 because the character portion is close to the density of the frame portion. At this time, the address signal NB indicates the first rising point of the SIG signal, and the address signal NA indicates the last falling point of the SIG signal in one line.

Since the MBIT signal becomes 1 at the first rise of the SIG signal and becomes 0 at the next HSYNC * signal, the NB address is latched at the rise of the MBIT signal. Since the MBI signal rises several times in the image portion, it is latched several times. However, since the last rising address NA is latched in one line, NB is latched at the next rising edge of the HSYNC signal. , NA addresses are latched.

Accordingly, the newly created timings NL and NLM are as shown in the figure, and the timings PL and PLM created by the PB and PA addresses latched by the HSYNC again are as shown in the figure.

The EXOR gate 11 shown in FIG.
3, 114 output

[0061]

[Outside 1] And the OR output is

[0062]

[Outside 2] Then, edge enhancement, error diffusion, and AND output of image signals VD and NLM through a delay circuit are output.

[0063]

[Outside 3] FIG. 19 shows the waveforms at the respective points. Image signal VD
Is indicated by oblique lines.

As a result, in the line where the image first appears, the entire image area is set as a black line, and the line after the next line (H
If SYNT is not HSYNC and every nth line is the next nth line), the edge of the image portion in the main scanning direction becomes a black band with the width set by D (see VDO signal).

As shown in FIG. 20, when the SIG changes, the width of the black band changes like the VDO signal. Due to this change, the image as shown in FIG.
The image is converted into an image as shown in FIG.

The edge emphasis circuit 118 uses a Laplacian 3 × 3 convolution mask. The mask coefficients are shown in FIG. Further, the halftone reproduction characteristic is improved by the error diffusion circuit 119. As is well known, the error diffusion method (ED method) compares a pixel of interest with a certain threshold,
This is a method of diffusing the generated error (difference value between the density of the target pixel and the threshold) to the density of the next plurality of pixels, and is one of typical pseudo halftone processing.

The delay circuit 120 is described in detail in FIGS.
It is configured as follows.

In FIG. 13, the CPU (not shown) first sets D
The number of delay lines is set in the latch 90 at the register write timing. The 8-bit counter 93 is cleared by the sub-scanning synchronizing signal VSYNC * and outputs the main-scanning synchronizing signal HSY.
It counts up at the rise of NC. This counter 93
Is output to the 8-bit equality comparator 91, is compared with the number of delay lines, and when they match, a positive pulse for one line cycle is output.

The positive pulse becomes a negative pulse by the inverter 92, and the 8-bit counter 93 is reset. At the same time, the previous match signal is input to the JK flip-flop 94, and the toggled signal MS is output each time the match signal is output.
Output EL.

The output count signal of the 8-bit counter 93 is connected to the address buses MA10 to MA17 of the RAM (1) 95 and the RAM (2) 96. Also RA
M (1) 95, RAM (2) 96, address bus MA9
To MA0 are address signals HAD12 to HAD12 obtained by adding a correction value to the count signal of the 13-bit counter 5 in the main scanning direction.
AD3 is connected. The reason why the lower three bits are not used is that data is converted from serial to parallel.

In FIG. 12, the output signal VD of the error diffusion circuit 19 is
I is converted into a serial-parallel signal by an 8-bit serial-parallel converter 81.

The SPCLK signal is applied to the GC as shown in FIG.
The signal of the serial-parallel conversion is latched by the D latch 82 by the SPCLK signal with a signal of 1/8 cycle of the LK signal.
As a result, the serial signal carved with GCLK is GCLK /
It is converted to an 8-bit parallel signal that is ticked at 8. This signal is a 3-state gate 8 when the previous MSEL signal is High.
The data is output from 3 to the RAM (2) 96, the 3-state gate 84 becomes high impedance, and when the MSEL signal is low, the 3-state gate 84 outputs the RAM from the RAM.
(1) Data is output to 95 and the 3-state gate 83
Becomes high impedance.

At the same time, when the MSEL signal is High, a signal from the RAM (1) 95 is output to the output S of the 8-bit selector 86, and when the MSEL signal is Low, the output S of the 8-bit selector 86 is set to the RAM (1). 2) The signal from 96 is output. This signal is latched by the D latch 8F at the rise of the PSLAT signal.

The PSLAT signal is GCLK as shown in FIG.
This signal is a 1/8 cycle of the signal, and its rising point is SPCLK.
This is a half of the signal rising cycle. Next, the output signal of the D latch 8F is input to the parallel-serial converter 88,
The data is loaded by the SLOAD * signal, and the serial image data V is output at the clock rising timing of the GCLK signal.
D is output.

The MSEL signal is also a select signal of the 4-bit selector 89, and M1RD *, M1RD
WR *, M2RD *, and M2WR * are input to the RAM (1) 95 and the RAM (2) 96 at the timing shown in FIG. As a result, the read (RD) and write (WR) timings of the RAM (1) and RAM (2) are as shown in FIG. The memory write signal MWR * used for M1WR * and M2WR * is output at the timing shown in FIG.

With the above control, the serial image signal VDI is output as the serial image signal VD delayed by the set number of delay lines. Here, the serial-to-parallel conversion is performed in order to control a high-speed image signal with a low-speed (long access time) and inexpensive RAM.

As described above, since image processing is performed by pipeline processing and automatic frame erasure is performed, only a few lines are required as an image memory, and an inexpensive and compact device can be provided. In addition, since processing such as storing image information in the entire image area is uneasy, processing can be performed at high speed.

Further, since the frame can be erased not to a rectangular shape but to an almost arbitrary shape, unnecessary frame portions can be erased with high accuracy, toner consumption can be reached, and image quality copy can be performed. Can be obtained.

Further, by forming a border around the image portion (the inner portion of the frame), the ring gap of the image portion is raised,
The size and position of the image portion can be clarified.

(Other Embodiments) Although the line memories 1 (22) to 7 (28) shown in FIG. 5 use 1-bit line memories, the cycle of HSYNW * is as long as eight lines. In addition, since a static line memory must be used, the cost increases. Therefore, the line memory shown in FIG.
FIG. 2 shows an example using D42505V (manufactured by NEC).
It is shown in FIG.

Read clock RC for line memory 79
The GCLKW signal is supplied to the K and write clock WCK terminals, and the HSYNC signal is supplied to the read reset RSTR * and write reset RSTW * terminals. Therefore, although the contents of the line memory are rewritten for each line, the SEL terminal of the 8-bit selector 80
Since the HSYNW signal is connected, HSYNW becomes n
In the case of the line cycle, the content written once in the memory (n-1) line is rewritten in a refreshing manner.

Therefore, on the nth line, a new VMB 'is written into the line memory of the 0th bit, and thereafter, the contents of the line memory of the 0th bit are the 1st bit, and the contents of the line memory of the 1st bit are 2 bits. The data is shifted and written one bit at a time to the eyes. Thus, a line memory of eight lines can be performed every n lines.

In the above description, the original is a microfilm image. However, the present invention is not limited to the original, and may be applied to, for example, a digital copying machine or a paper scanner. In such an apparatus, since the same-size copying is mainly performed, the influence of dust and dust is small because it is not expanded like a microfilm, and the block bit addition circuit 102 may be simplified, and may be omitted in some cases. It is possible.

Also, since the border width can be changed separately in the main and sub-scanning directions, the border shown in FIGS. 26A and 26B can be obtained. However, a configuration in which the border width is changed simultaneously in the main and sub-scan directions. Can be easily achieved.

The edge emphasis circuit 118 and the error diffusion circuit 119 are not particularly necessary constituent elements, and may be any image processing. Also, as shown in FIG. 27, if it is permissible to copy a part of the frame remaining at the rear end, the delay circuit 120
Is also unnecessary.

Although one of the inputs of the AND gate 116 uses the NLM signal, any one of NL, PL, and PLM can equivalently erase the frame. However, in each signal, there is a slight difference in frame displacement when the frame position is slightly shifted and the border function is turned off.

As described above, at the time of image reading, an evaluation signal indicating an image portion or a frame portion corresponding to a read signal of two main scanning direction lines separated by a predetermined section in the sub-scanning direction is taken out, and further, this evaluation is performed. A signal having a boundary line width added to both ends of the image portion of the signal is extracted, and a non-rectangular frame is automatically erased from these signals, and at the same time, a black border is drawn on the entire image portion by drawing a boundary line between the image portion and the frame portion. By increasing the quality of the output image,
The size and position of the image can be clarified by enhancing the image region.

Further, this system requires only a few line memories as an image memory, and the processing can be performed almost in real time by pipeline processing. Image processing can be performed.

[0089]

As described above, according to the present invention, a boundary between an image and a peripheral portion is detected based on an image signal representing the image and its peripheral portion, and an image signal outside the detected boundary is specified. Since the image signal is converted into a signal and an image signal representing a frame is formed in accordance with the detected boundary, the frame is formed by performing automatic non-rectangular frame erasing and simultaneously drawing a boundary line between the image portion and the frame portion. By doing so, the image quality of the output image can be improved, and the image area can be emphasized to clarify the size and position of the image.

[Brief description of the drawings]

FIG. 1 is an external view of a digital reader printer.

FIG. 2 is a mechanism diagram of a digital reader printer.

FIG. 3 is a circuit block diagram of a digital reader printer.

FIG. 4 is a block diagram of an image processing circuit and a frame detection circuit.

FIG. 5 is a block diagram of a block bit addition circuit.

FIG. 6 is a block diagram of an adding circuit A.

FIG. 7 is a block diagram of an adding circuit B;

FIG. 8 is a block diagram of a detection signal generation circuit.

FIG. 9 is a block diagram of a rising / falling address latch circuit.

FIG. 10 is a block diagram of an address / timing conversion circuit A;

FIG. 11 is a block diagram of an address / timing conversion circuit B;

FIG. 12 is a block diagram of a delay circuit.

FIG. 13 is a block diagram of a delay circuit.

FIG. 14 is a block diagram of a delay circuit.

FIG. 15 is a timing chart.

FIG. 16 is a timing chart.

FIG. 17 is a timing chart.

FIG. 18 is a timing chart.

FIG. 19 is a timing chart.

FIG. 20 is a timing chart.

FIG. 21 is a timing chart.

FIG. 22 is a diagram showing sample points.

FIG. 23 is a diagram showing an output example of an image.

FIG. 24 is a diagram showing filter coefficients.

FIG. 25 is a diagram showing another configuration of the line memory.

FIG. 26 is a diagram showing an output example of an image.

FIG. 27 is a diagram showing an output example of an image.

FIG. 28 is a diagram showing a conventional image output example.

FIG. 29 is a diagram showing the contents of a memory RAM.

FIG. 30 is a diagram showing a conventional image output example.

[Explanation of symbols]

 Reference Signs List 13 line sensor 24 frame detection circuit 26 image processing circuit 102 block bit addition circuit 104 detection signal generation circuit 107 rising address latch circuit 108 falling address latch circuit 111 address / timing conversion circuit A 112 address / timing conversion circuit B 120 delay circuit

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Claims (1)

(57) [Claims] An input unit for inputting an image signal representing an image and a peripheral portion thereof; a detection unit for detecting a boundary between the image and the peripheral portion based on the image signal input from the input unit; Conversion means for converting an image signal outside the boundary detected by the detection means into a specific signal; and formation means for forming an image signal representing a frame corresponding to the boundary detected by the detection means. An image processing apparatus characterized by the above-mentioned.