JPH0541658A - Cmos logical gate circuit - Google Patents

Abstract

PURPOSE:To easily reduce power consumption by serially inserting diode loads into a CMOS inverter constituting the logical gate circuit. CONSTITUTION:Gate electrodes G connected to an input terminal 1 are the common transistor for a P channel MOS transistor 5 and an N channel MOS transistor 6. An N channel MOS transistor 7 having the gate electrodes and drain electrodes with the same electric potential and having substrate electrodes with the same potential with an earth terminal 4 is serially connected between source electrodes N3 of the transistor 5 and a power supply terminal 3. When an input terminal 1 is at 'L' level, an output terminal 2 becomes 'H' level. The potential V2 rises only to the potential descended by the threshold voltage VT7 of the transistor 7 from the power supply terminal 3. Therefore, the voltage amplitude of the output terminal 2 reduces by the voltage VT7, and the charge/ discharge current can be reduced, resulting in low power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS logic gate circuit, and more particularly to a CMOS logic gate circuit suitable for a low power consumption digital integrated circuit.

[0002]

2. Description of the Related Art Recently, as the scale of integrated circuits becomes larger and the operating frequency becomes higher, there is a demand for further reduction of power consumption per gate. In the conventional CMOS logic gate circuit, a method of reducing the power supply voltage, a method of reducing the output load capacitance, a method of reducing the size of the transistor to reduce the parasitic capacitance, etc. have been considered as such a method of reducing the power consumption. It was

In the conventional CMOS logic gate circuit, for example, in the case of the 2-input NAND gate shown in FIG. 4, P-channel MOS transistors 24 and 25 are connected in parallel between the output terminal 2 and the power supply terminal 3, and the output terminal is 2 and the ground terminal 4, N-channel MOS transistors 26 and 27 are connected in series, and further P-channel MOS transistor 2
4 and N channel MOS transistor 26, P channel M
The gate electrodes of the OS transistor 25 and the N-channel MOS transistor 27 are connected to the input terminals 8 and 9, respectively.

That is, P-channel MOS transistors 24 and 25 are provided between the output terminal 2 and the power supply terminal 3, N-channel MOS transistors 26 and 27 are provided between the output terminal 2 and the ground terminal 4, and the P-channel MOS transistor 2 is also provided.
If the P-channel MOS transistors 26 and 27 are connected in parallel, the N-channel MOS transistors 26 and 27 are connected in series. On the contrary, if the P-channel MOS transistors 24 and 25 are connected in series, the N-channel MOS transistors 26 and 27 are connected in parallel. It is configured by connecting to a connection. The P channel MOS transistors 24 and 25 and the N channel MOS
The gate electrodes of the transistors 26 and 27 form a pair and are connected to the input terminals 8 and 9.

With such a configuration, the input terminals 8 and 9
In the steady state of "H" level or "L" level, neither the paired P-channel MOS transistors 24 and 25 and the N-channel MOS transistors 26 and 27 become conductive at the same time, and the steady current is Not flowing.
Only when the input terminals 8 and 9 change from "H" level to "L" level or vice versa, the P-channel MOS transistors 24 and 25 and the N-channel MOS transistors are formed.
There is a state where both the transistors 26 and 27 are conducting, and a transient through current flows between the power supply terminal 3 and the ground terminal 4. In addition, a current iC that charges and discharges the load capacitance C of the output terminal 2 in accordance with changes in the signals S8 and S9 of the input terminals 8 and 9.
Flows.

Therefore, although a transient current flows, almost no current flows steadily, and only a leak current such as a junction leak current or a subthreshold leak current of a MOS transistor flows. For this reason, the conventional C
The MOS logic gate circuit has an excellent point that the power consumption is extremely low when the number of transient changes is small, that is, when the operating frequency is small.

[0007]

In this conventional CMOS logic gate circuit, the method of lowering the power supply voltage in order to reduce the current consumption has a relationship with the power supply voltage used in the electronic device, and therefore can be easily changed. I can't. Moreover, it is difficult to change the same power supply voltage as other integrated circuits.

Next, there is a method of reducing the output load capacity.
The wiring capacitance is dominant as the output load capacitance in the logic circuit, and rather, it depends on the fine processing technology of the manufacturing process, and it is difficult to devise the circuit.

Further, the method of reducing the size of the transistor increases the signal transmission delay time, and the wiring capacitance is dominant as the load capacitance of the logic circuit as described above. However, there is a problem in that the current consumption due to high-frequency operation cannot be reduced because it cannot be expected.

[0010]

In the CMOS logic gate circuit of the present invention, a first P-channel gate electrode is connected to an input terminal.
Channel MOS transistor and first N-channel MOS
One or more series-connected transistors having a transistor, in which the gate electrode and the drain electrode have the same potential and the substrate electrode has the same potential as the ground terminal, between the source electrode and the power supply terminal of the first P-channel MOS transistor. Second N channel MOS
One or more second series-connected transistors in which the gate electrode and the drain have the same potential and the substrate electrode has the same potential between the source electrode and the ground terminal of the first N-channel MOS transistor and the substrate electrode has the same potential. It is configured to have at least one of a P-channel MOS transistor.

[0011]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of the first embodiment of the present invention. This inverter has an N-channel MOS transistor 7 in which the gate electrode and the drain electrode have the same potential and the substrate electrode has the same potential as the ground terminal 4, the gate electrode G is connected to the input terminal 1 and the drain electrode N2 is connected to the output terminal 2. P channel M
It is connected in series between the source electrode N3 of the OS transistor 5 and the power supply terminal 3.

An N-channel MOS transistor 6 is connected between the output terminal 2 and the ground terminal 4. The transistors 5 and 6 are CMOS transistors having a common gate electrode G.

With this structure, when the input terminal 1 is at "H" level, the P channel MOS transistor 5
Is in the off state, the N-channel MOS transistor 6 is in the on state, and the output terminal 2 is inverted and becomes the "L" level. In this case, the potential V2 of the output terminal 2 becomes the ground potential VG and operates in the same manner as the conventional CMOS inverter. On the other hand, when the input terminal 1 is at "L" level, the N-channel MOS transistor 6 is off and the P-channel MOS transistor 5 is on. At this time, the output terminal 2 becomes "H" level. In this case, unlike the conventional CMOS inverter shown in FIG. 4, the potential V2 of the output terminal 2 rises only to a potential lower than that of the power supply terminal 3 by the threshold voltage VT7 of the N-channel MOS transistor 7. Therefore, the voltage amplitude of the output terminal 2 in this embodiment is smaller than that of the conventional CMOS inverter by the threshold voltage VT7 of the N-channel MOS transistor 7, and the charging / discharging current can be reduced by that much, resulting in lower power consumption. It will be possible.

FIG. 2 is a graph for comparing and explaining the power consumption of the first embodiment and the conventional CMOS inverter. Here, the power supply voltage is 5 V, the channel length of the P-channel MOS transistor 5 is 1.0 μm, and the N-channel MO transistor is
The channel length of the S transistors 6 and 7 is 0.8 μm, and the channel width is 15 μm for both P and N channels.
The absolute value of the threshold voltage of both the channel and the N channel was set to 0.7V. As is apparent from FIG. 2, the power consumption 12 according to the present embodiment can be reduced to about 70% from the conventional power consumption 11.

When the voltage amplitude of the output terminal 2 becomes small as described above, the next-stage gate may malfunction, but there is no problem if the next-stage gate has the same circuit configuration as that of this embodiment. Further, since it can be configured only by additionally connecting one MOS transistor to the conventional CMOS logic gate circuit, it can be realized very easily.

FIG. 3 is a circuit diagram of a 2-input NAND gate showing a second embodiment of the present invention. In this embodiment, an N-channel MOS transistor 18 in which the gate electrode and the drain electrode have the same potential and the substrate electrode has the same potential as the ground terminal 4, and the P-channel MO transistor whose gate electrode is connected to the input terminals 8 and 9 is used.
The source electrodes N3 of the S transistors 13 and 14 and the power supply terminal 11 are connected in series.

A P-channel MOS transistor in which the gate electrode and the drain electrode have the same potential and the substrate electrode has the same potential as the power supply terminal 3
The transistor 17 is connected in series between the N-channel MOS transistor 16 whose gate electrode is connected to the input terminals 8 and 9 and the ground terminal 4. In this case, when the potential of the output terminal 2 is at "L" level, the P channel M
The potential becomes higher by the absolute value of the threshold voltage of the OS transistor 17 and becomes lower than the power supply terminal 3 by the threshold voltage of the N-channel MOS transistor 18 at the “H” level.

Therefore, the voltage amplitude of the output terminal 2 is the same as that of the conventional CM.
It becomes smaller than the OS logic gate circuit by the sum of the threshold voltages of the P-channel MOS transistor 17 and the N-channel MOS transistor 18, and as a result, the charge / discharge current iC can be reduced and the power consumption can be reduced.

The power supply voltage is 5 V, the channel length of the P-channel MOS transistor is 1.0 μm, the channel length of the N-channel MOS transistor is 0.8 μm, both channel widths are 15 μm, and the absolute value of the threshold voltage VT is 0.7.
When V is set, the power consumption can be reduced to about 60% in this embodiment as compared with the conventional CMOS logic gate circuit.

[0020]

As described above, according to the present invention, it is possible to easily reduce the power consumption as compared with the conventional CMOS logic gate circuit by inserting a diode load in series to the CMOS inverter which constitutes the logic gate circuit. Become.

[Brief description of drawings]

FIG. 1 is an inverter circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a power consumption characteristic diagram for explaining the effect of the circuit of the embodiment of FIG.

FIG. 3 is a circuit diagram of a 2-input NAND gate showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an example of a conventional CMOS logic gate circuit.

[Explanation of symbols]

1,8,9,19,20 Input terminal 2,10,21 Output terminal 3,11,22 Power supply terminal 4,12,23 Ground terminal 5,13,14,17,24,25 P channel MO
S transistor 6,7,15,16,18,26,27 N channel MOS transistor

Claims (1)

[Claims] 1. A first gate electrode connected to an input terminal
P-channel MOS transistor and first N-channel M
The first P-channel MOS having an OS transistor
One or more second N-channel M connected in series between the source electrode and the power supply terminal of the transistor, the gate electrode and the drain electrode of which have the same potential, and the substrate electrode of which has the same potential as the ground terminal.
One or more serially connected gate electrodes and drains having the same potential and substrate electrodes having the same potential as the power supply terminal are connected in series between the OS transistor and the source electrode and the ground terminal of the first N-channel MOS transistor. C at least one of the P-channel MOS transistors of
MOS logic gate circuit.