JPH0541485A - Manufacture of mos semiconductor element - Google Patents

Abstract

PURPOSE:To eliminate the possibility of wrong ignition at the time of operation or a short circuit caused when an electrode pair is press-contacted with a substrate so as to improve the reliability of an MOS semiconductor element by removing not only the source electrode of a faulty unit element, but also all of the gate electrode, source area, and wafer area below the faulty source electrode. CONSTITUTION:After the surface of a substrate is covered with a protective film 9 except a faulty unit IGBT 15, the substrate is etched with an etching liquid of phosphoric acid or nitric acid. Then, after exposing a silicon substrate by etching a PSG film 51 on a gate electrode 6 with an HF buffer liquid, the substrate is etched together with the gate electrode 6 with an etching liquid prepared by mixing nitric acid, hydrofluoric acid, and acetic acid. As a result, a recessed section 10 is produced. Since a source electrode 7, n<+> source area 4, and gate electrode 6, etc., are removed, the faulty unit IGBT 15 does not give any adverse influence to the entire body of this MOS semiconductor element. Therefore, even when the voltage applied across the entire body of the element abruptly changes, the occurrence of an abnormal phenomenon, such as wrong ignition, can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention integrates a plurality of unit elements each having a MOS structure and a main electrode on one surface of a semiconductor substrate, and press-contacting an electrode plate to the main electrodes. The present invention relates to a method for manufacturing a MOS semiconductor device in which each unit device is connected in parallel.

[0002]

2. Description of the Related Art For example, a MOS field effect transistor
In a semiconductor element such as an insulated gate bipolar transistor (hereinafter referred to as an IGBT) that controls a main current by an input signal to a gate electrode, a current flowing through a large-area main electrode must be controlled. Therefore, when increasing the capacity, for example, as described in JP-A-63-278264, elements having a size of several mm square are arranged in a container, and source electrodes thereof are arranged.
A method is used in which modules are connected in parallel by connecting them by Al wire bonding or the like.

However, in such a method, the number of elements must be increased in order to increase the capacitance. However, as the number of elements increases, the wiring of the conductive wire to be bonded becomes complicated, and the number of elements increases. Breakages are likely to occur. Even finer conductors are prone to breakage due to heat when a large current is applied.

In order to solve this problem, it is possible to integrate a large number of unit elements on one semiconductor substrate. If a pressure contact structure in which a common electrode body is pressed against the main electrode of each element is used, not only will the reliability of the connection be improved, but the inductance and resistance of the connection conductor will be reduced, and the board will be cooled from both sides. Therefore, the cooling efficiency can be improved. As a result, the characteristics and reliability of the semiconductor device are improved.

On the other hand, when a large number of unit elements are formed on one substrate, not all unit elements are not defective,
There is a defective unit element. For such defective unit device, the source electrode is removed by etching or the like, or the gate electrode and the source electrode of the defective unit device are short-circuited to prevent the gate voltage from being applied, and then an insulating film is covered on the source electrode. Has been taken conventionally.

[0006]

However, even if the source electrode of the defective unit element is removed or the gate electrode is short-circuited with the source electrode, if the voltage applied between both main electrodes has a sharp rise, that is, If dv / dt is large, false ignition may occur. Alternatively, the electrode body that is in pressure contact with the source electrode may contact the gate electrode or the semiconductor substrate at the portion where the source electrode is removed, and an uncontrollable current may flow to the defective unit element. If the source electrode is made significantly thicker, contact between the electrode body and the gate electrode or the substrate can be avoided, and some problems will be solved, but this is unacceptable in the manufacturing process.

It is an object of the present invention to provide a method of manufacturing a MOS type semiconductor device having a high reliability even when there is a defective device among the unit devices by solving the above problems.

[0008]

In order to achieve the above-mentioned object, the present invention provides that a second region of the second conductivity type is selectively formed in the surface layer of the first region of the first conductivity type. A third region of the first conductivity type is selectively formed in each surface layer of the second region, and a portion sandwiched between the first region and the third region of the second region is formed on it as a channel forming region. A gate electrode is provided via a gate insulating film, and a plurality of unit elements in common with the source electrode in contact with the second region and the third region are formed on one semiconductor substrate, and are common to the source electrodes of the unit elements. In the method for manufacturing a MOS type semiconductor device in which the electrode body is pressed into contact with each other, after measuring the electrical characteristics of each unit element, the source electrode, gate electrode, third area and second area Shall be removed. Then, it is effective to cover the unit elements other than the defective unit element with a protective film, and then remove the source electrode, the gate electrode, the third region and the second region by etching with an etching solution suitable for each. It is also effective to fill the removed portion of the semiconductor substrate with an insulator.

[0009]

[Operation] By removing the source electrode, gate electrode, third region (source region), and second region of the defective unit element,
This unit element does not adversely affect the entire device. Therefore, the sudden change in the voltage applied to the entire element,
That is, even when a large dv / dt occurs, an abnormal phenomenon such as false firing can be avoided. Further, since the electrode body does not come into contact with the gate electrode or the semiconductor substrate, an uncontrollable current does not flow through the defective unit element.

[0010]

EXAMPLE FIG. 2 shows an entire IGBT semiconductor substrate. A unit IGBT 12 of about 100 silicon substrates 11 having a diameter of 4 inches is integrated. The gate electrode of each unit IGBT 12 is connected to a gate lead-out portion 14 via a gate lead 13.
This silicon substrate 11 is housed in a flat container and each unit IGB is
One metal electrode plate is pressure-contacted with the source electrode insulated from the gate electrode of T12, current is taken out in parallel, and a gate terminal is connected to the gate take-out portion 14 to input a control signal. When the electrical characteristics of each unit IGBT 12 of the substrate 11 are evaluated, several% of defective unit elements are found. In the figure, the defective unit element 15 is shown with a cross.

FIGS. 1 (a) to 1 (d) show a defective unit IGBT separating step of an embodiment of the present invention. In (a), the entire thickness of the substrate is shown, but in (b) to (d), the backside portion is omitted. In FIG. 1A, the p ⁺ drain layer 2 is provided on one side of the n ⁻ layer (first region) 1, and the p ⁺ well (second region) 3 is selectively formed in the surface layer on the other side. n ⁺ source region (third region) 4 selectively in the surface layer of p ⁺ well 3
Are formed respectively. A portion of the p ⁺ well 3 sandwiched between the n ⁻ layer 1 and the n ⁺ region 4 is a channel region, and a gate electrode 6 made of polycrystalline silicon is provided across the two channel regions via a gate oxide film 5. The source electrode 7 insulated from the gate electrode 6 by the PSG film 51 is in common contact with the p ⁺ well 3 and the n ⁺ source region 4. The drain electrode 8 is in contact with the p ⁺ drain layer 2. This structure is a known IGBT structure. In the figure,
If the portion indicated by the arrow is the defective unit IGBT15, the surface of the portion other than the defective unit IGBT15 is covered with the protective film 9. The protective film 9 was formed by applying a positive photoresist with a spin coater, exposing 15 defective unit IGBTs based on the data at the time of electrical characteristic evaluation using a stepper exposure machine, and further developing. It is a thing.

In the state shown in FIG. 1A, the substrate surface is etched with a phosphoric acid / nitric acid type etching solution having a phosphoric acid / nitric acid ratio of 10: 1. The source electrode 7 having a thickness of about 10 μm exposed at a temperature of about 60 ° C. in a few minutes disappears as shown in FIG. The substrate is thoroughly washed with water, and then the PSG film 51 on the gate electrode 6 is etched with an HF buffer solution which is a mixed solution of HF and NH ₃ F. This state is shown in Figure (c). When the silicon substrate was exposed in this way, nitric acid, hydrofluoric acid, and acetic acid were added in a 3:
The substrate is etched to a depth of about 30 μm together with the gate electrode 6 made of polycrystalline silicon using an etching solution mixed at a ratio of 2: 1. As a result, the recess 10 as shown in FIG. Below the gate electrode 6, the oxide film 5 is about 0.
Since it exists in a thickness of 6 μm, etching is delayed as compared with other regions, but this is not a problem. In this way, since the source electrode 7, the n ⁺ source region 4 for supplying electrons at the time of turn-on, the gate electrode 6 for forming a channel, and the like are eliminated, the defective unit IGBT 15 never affects the entire device. Therefore, erroneous ignition can be avoided even when a sudden dv / dt is applied to the entire device. Further, there is no possibility that the electrode body is pressed against the substrate of the defective unit element portion. However, in order to complete insulation, it is also effective to remove the resist 9 and then apply polyimide resin or the like to fill the recess 10 or a part thereof of the substrate.

Although the above embodiment is the case of the IGBT,
It is obvious that the vertical MOSFET or the p-channel MOS type semiconductor device in which the conductivity types are switched can be similarly implemented.

[0014]

According to the present invention, in a MOS type semiconductor device in which a large number of unit devices are integrated on one semiconductor substrate and the electrode body is commonly pressed against the electrodes of each unit device, the source of a defective unit device is Not only the electrode, but the gate electrode below it,
By removing all of the source region and the well region, the possibility of erroneous firing during operation or short circuit due to pressure contact of the electrode body with the substrate was eliminated, and a very reliable MOS type semiconductor device was obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing an IGBT manufacturing process of an embodiment of the present invention in the order of (a) to (d).

FIG. 2 is a plan view of an example of an IGBT semiconductor substrate.

[Explanation of symbols]

1 n ^- layer 2 p ⁺ drain layer 3 p ⁺ well 4 n ⁺ source region 5 gate oxide film 51 PSG film 6 gate electrode 7 source electrode 8 drain electrode 9 protective film 10 recess 11 silicon substrate 12 unit IGBT 15 defective unit device

Claims (3)

[Claims] 1. A second region of the second conductivity type is selectively formed in the surface layer of the first region of the first conductivity type, and the first conductivity type is selectively formed in each surface layer of the second region. A third region of the mold is formed, a portion sandwiched between the first region and the third region of the second region is used as a channel forming region, and a gate electrode is provided thereon via a gate insulating film. A plurality of unit devices whose source electrodes are commonly in contact with the third region are
In a method for manufacturing a MOS type semiconductor device formed on a single semiconductor substrate and having an electrode body commonly pressed against the source electrode of each unit device, a defective unit that does not satisfy the specified characteristic value after measuring the electrical characteristics of each unit device. A method of manufacturing a MOS type semiconductor device, characterized in that the source electrode, the gate electrode, the third region and the second region of the device are removed. 2. The unit element other than the defective unit element is covered with a protective film, and then the source electrode, the gate electrode, the third region and the second region are removed by etching with an etching solution suitable for each of them. Manufacturing method of MOS type semiconductor device. 3. The method for manufacturing a MOS semiconductor device according to claim 1, wherein the removed portion of the semiconductor substrate is filled with an insulator.