JPH0541450A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To prevent the generation of side wall separation in a chip unavailable region of a semiconductor chip and inhibit the generation of dust produced by film separation between formed films and enhance the production yield of the semiconductor chips. CONSTITUTION:Any arbitrary functional films located on the upper layer side out of various kinds of functional films 30 to 40 formed on the surface of a semiconductor wafer in a chip unavailable region based on a semiconductor manufacturing process are formed in multilayer so as to produce a semiconductor wafer in such a fashion that they may cover the terminal sections 35a to 39a on a scribe side of at least one layer of functional films.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a semiconductor wafer,
In particular, it relates to a semiconductor wafer capable of reducing dust after dicing.

[0002]

2. Description of the Related Art As shown in FIG. 4, when a plurality of semiconductor chip regions 4 are formed on the surface of a semiconductor wafer 2, chip invalid regions 6 in which semiconductor chips are not formed are formed on the outer peripheral surface of the semiconductor wafer 2. Is formed. In order to form various integrated circuits in the semiconductor chip area 4, the semiconductor wafer 2
Are processed by various semiconductor manufacturing processes. At that time, as shown in FIG. 5, the functional thin films 8, 10, 12, 13, and 14 having a predetermined pattern are formed in each semiconductor chip region 4 by the thin film forming technique. At the same time, the functional thin films 9 to 14 are also formed in the chip invalid region 6, and the functional thin films in those portions are left as they are without being etched.

That is, conventionally, in the chip invalid area 6,
Various functional thin films 9 to 14 for forming the semiconductor chip region 4 in a predetermined pattern are simply laminated as they are, and the surface of the wafer 2 is exposed in the vicinity of the scribe line 16 which is a dividing line between the semiconductor chip region 4 and the chip ineffective region 6. The end portion 18 of the laminated film is etched at a steep step so as to be exposed.
Therefore, the side wall 20 is formed at the end portion 18 of the laminated film.
Will be formed. The reason why the sidewall 20 is formed can be explained as follows, for example, as shown in FIG.

On the surface of the semiconductor wafer 2, the functional thin films 9, 1
After 0 and 11 are formed in a predetermined pattern, the functional thin film 1
2 is formed on the entire surface of the wafer 2 and is etched by the resist film 22 in a predetermined pattern. At that time, an etching residue is generated at the end portion 18 of the laminated film, so that the sidewall 20 is formed. It is formed. The etching is performed so that the surface of the wafer is exposed in the vicinity of the scribe line 16 so that dicing along the scribe line 16 can be easily performed.

[0005]

Conventionally, based on the idea that the chip invalid area 6 is a portion to be discarded in a later process, the side wall 20 is left as it is even if it is formed in the chip invalid area 6. is the current situation. However, it has been found by the present inventor that when the chip invalid region 6 is structured as shown in FIG. 5, the following adverse effects occur. That is, for example, when the semiconductor wafer 2 is diced along the scribe line on the wafer sticking tape, the semiconductor chip is picked up and die-bonded, or in the wafer process step, the sidewall 20 of the chip invalid region 6 has a whisker shape. It may be peeled off and become dust, which may stick to the surface of the semiconductor chip and cause a wiring short circuit. Further, since the end portion 18 of the laminated film has a steep step, it is particularly between the functional thin films 11 and 13 that will be the metal wiring layer and the functional thin films 10, 12 and 14 that will be the interlayer insulating film or the overpassivation film. There is a risk that film peeling will occur, which will cause dust and cause inconveniences such as wiring shorts.

The present invention has been made in view of such circumstances, and prevents the generation of dust due to the peeling of the sidewalls in the chip ineffective region of the semiconductor wafer or the peeling of the films between the laminated films, and the production yield of the semiconductor chips. It is an object of the present invention to provide a semiconductor wafer capable of improving

[0007]

In order to achieve the above-mentioned object, in the semiconductor wafer of the present invention, any of the various functional thin films formed on the surface of the chip ineffective region by the semiconductor manufacturing process is located on the upper layer side. The functional thin film is laminated so as to cover at least one or more functional thin films located below the functional thin film on the scribe line side end.

[0008]

In the semiconductor wafer of the present invention, an arbitrary functional thin film located on the upper side of the functional thin films in the chip ineffective region covers the end portion of at least one or more functional thin films located below the scribe line side. Since the layers are stacked in this manner, the side wall is not formed, and the side wall does not peel off to become dust. Further, at the end of the laminated functional thin films on the scribe line side, the upper film is laminated so as to cover the end of the lower film, so that peeling between the films is less likely to occur. Therefore, it is possible to prevent dust from being generated due to film peeling.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor wafer according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of a main part of a semiconductor wafer according to an embodiment of the present invention, FIG.
FIG. 3 is a plan view showing an example of a reticle, and FIG. 3 is a cross-sectional view of essential parts of a semiconductor wafer according to another embodiment of the present invention.

As shown in FIG. 1, in the semiconductor wafer 30 of this embodiment, the semiconductor chip region 31 is the same as the semiconductor chip region 4 of the semiconductor wafer 2 according to the conventional example shown in FIGS. A plurality of grids are formed on the surface of the central part of. A chip invalid region 32 is formed on the surface of the wafer 30 located on the outer periphery of the semiconductor chip region 31. The semiconductor wafer 30 is diced along the scribe line 16 in order to divide the semiconductor chip regions 31 from each other or the semiconductor chip region 31 and the chip invalid region 32 in a later step.

In this embodiment, various semiconductor circuits are formed by forming various impurity diffusion layers or buried layers on the surface of the semiconductor wafer 30 corresponding to each semiconductor chip region 31 by means such as ion implantation. A thin film forming technique is used to stack various functional thin films having a predetermined pattern on the surface. When forming various semiconductor circuits in each semiconductor chip region 31, the diffusion layer 33 and the like are also formed on the surface of the wafer 30 corresponding to the vicinity of the scribe line 16. In order to insulate various semiconductor circuits formed in the semiconductor chip region 31 along the wafer surface, the surface of the wafer 30 is selectively oxidized (LOCOS) 3 as a functional thin film.
4 are formed in a predetermined pattern.

In this embodiment, in each semiconductor chip region 31, a polysilicon film 35 as various functional thin films, a first interlayer insulating film 36, and a first metal electrode film 3 are formed in a predetermined pattern.
7, the second interlayer insulating film 38, the second metal electrode film 39, and the overcoat film 40 are laminated in this order. However,
Since only the end of the semiconductor chip region 31 on the scribe line side is shown in FIG. 1, it seems that only some of the films 36, 38, 39, 40 are laminated in the semiconductor chip region 31. . In reality, the semiconductor chip area 3
1, the films 35 to 40 described above are laminated in a predetermined pattern. Then, at the end of the scribe line, the film 36,
In order to prevent the peeling of the films among the layers 38, 39, 40, the ends of the films located on the upper layer side are laminated so as to cover the ends of the films located on the lower layer side.

The interlayer insulating films 36 and 38 are not particularly limited. For example, a silicon oxide film, a silicon nitride film, a phosphorus-doped silicon oxide film (PSG film), a boron-doped silicon oxide film (BSG), an arsenic-doped silicon oxide film (AsSG). Membrane) etc. are illustrated. These are formed by, for example, a CVD method or a plasma CVD method. What kind of insulating film is used as the interlayer insulating film is determined according to the type of the semiconductor device. For example, if the semiconductor device has a MOS structure, AsSG, BSG, PSG or the like is used, if it is a semiconductor memory, BSG, PSG or the like is used, and if it is a semiconductor device having a bipolar structure, silicon nitride by plasma CVD method is used. A film or the like is used.

The overcoat film 40 is not particularly limited, but a film made of the same material as the interlayer insulating films 36 and 38,
Alternatively, a polyimide resin film or the like is used. The metal electrode films 37 and 39 are not particularly limited, but aluminum electrode films or the like are used.

In the chip invalid area 32, various functional thin films 35 to 40 for stacking in a predetermined pattern on the semiconductor chip area 31 are stacked as they are in a predetermined stacking order and remain. In this embodiment, an arbitrary thin film of such thin films is laminated so as to sequentially cover the scribe line side end portions 35a to 39a of the thin films located below the thin films in a stepwise manner.

In order to obtain such a structure, the outermost effective shot line 44 formed on the reticle 42 for reduction projection exposure as shown in FIG. 2 may be shifted for each etching. The offset width corresponds to the width over which the upper layer film covers the lower layer film, and the width is not particularly limited, but is several μm.
It is a degree. The reticle 42 is for sequentially etching the thin films 35 to 40 in a predetermined pattern, and exposes four semiconductor chip regions in one shot. Line 16a formed on this reticle 42
Corresponds to the scribe line. Also, the reticle 42
The outer circumference of is covered with a light shielding film 46 made of a chromium thin film. In the present embodiment, since it is only necessary to shift the processing dimension of the outermost effective shot line 44 on the reticle 42,
The number of manufacturing processes does not increase as compared with the conventional one.

The semiconductor wafer 30 as described above is diced along the scribe line 16.
Any thin film located on the upper layer side of the thin films 35 to 40 is
Since the layers are laminated so as to cover the scribe line side end portions 35a to 39a of the thin films located therebelow, the side wall is not formed and is not peeled off to become dust. Further, at the scribe line side end portions 35a to 39a of the laminated thin films, since the upper film is laminated so as to cover the end portions of the lower films, peeling between the films is less likely to occur. Therefore, it is possible to prevent dust from being generated due to film peeling.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, in the above-described embodiment, the end portions 15a to 39a of the functional thin film located in the chip invalid area 32 are formed.
Was configured to cover the stairs, but is not limited to this,
Any structure can be used if any functional thin film located on the upper layer side of the functional thin film is laminated so as to cover the scribe line side end of at least one or more functional thin films located below it. Good.

For example, as shown in FIG. 3, the functional thin films 35 to 35 are formed so that the end portions of the semiconductor chip region 31 and the chip invalid region 32a are partially symmetrical with respect to the scribe line 16. Semiconductor wafer 30a in which the upper film is laminated so that the upper film covers the end of the lower film.
Is also within the scope of the present invention. Further, the number of laminated functional thin films is not particularly limited, and the present invention can be applied to all wafers in which a plurality of functional thin films are laminated on a semiconductor wafer.

[0020]

As described above, according to the present invention, any functional thin film located on the upper layer side of the functional thin films in the chip invalid area is at least one functional thin film located below the functional thin film. Since they are laminated so as to cover the end portion on the scribe line side, the side wall is not formed, and the side wall is prevented from peeling off to become dust. Further, at the end of the laminated functional thin films on the scribe line side, the upper film is laminated so as to cover the end of the lower film, so that peeling between the films is less likely to occur. Therefore, it is possible to prevent dust from being generated due to film peeling. As a result, the yield for manufacturing semiconductor chips from a semiconductor wafer is improved. Further, in order to obtain the semiconductor wafer of the present invention, for example, it is only necessary to shift the processing dimension of the outermost peripheral line of the effective shot on the reticle, so that the number of manufacturing steps does not increase as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor wafer according to an embodiment of the present invention.

FIG. 2 is a plan view showing an example of a reticle.

FIG. 3 is a cross-sectional view of essential parts of a semiconductor wafer according to another embodiment of the present invention.

FIG. 4 is a plan view of a semiconductor wafer.

5 is a cross-sectional view of a main part of a conventional semiconductor wafer, showing a cross section taken along the line AA shown in FIG.

FIG. 6 is a cross-sectional view of essential parts showing an example of a conventional manufacturing process of a semiconductor wafer.

[Explanation of symbols]

16 ... Scribe line, 30, 30a ... Semiconductor wafer, 31 ... Semiconductor chip region, 32, 32a ... Chip ineffective region, 35-40 ... Functional thin film, 35a-39a ... End portion

Claims (2)

[Claims] 1. A plurality of semiconductor chip regions are formed on a surface of a central portion, and a chip invalid region is formed on an outer peripheral surface, and the semiconductor chip region and the chip invalid region are diced along a scribe line. In the semiconductor wafer described above, any functional thin film located on the upper side of various functional thin films formed on the surface of the chip ineffective region by the semiconductor manufacturing process is replaced by at least one functional thin film located below the functional thin film. A semiconductor wafer, which is laminated so as to cover an end portion on the scribe line side. 2. The functional thin film located on the upper layer side of the various functional thin films formed on the surface of the chip ineffective region covers stepwise ends of the functional thin films located on the lower layer sequentially on the scribe line side. A semiconductor wafer characterized by being laminated.