JPH0541414Y2 - - Google Patents

Description

[Detailed description of the invention] (Industrial application field) This invention relates to a small signal detection circuit that detects the presence or absence of a small signal, and in particular detects a small optical signal that is easily affected by disturbance as an electrical signal. This invention relates to a small signal detection circuit capable of detecting small signals.

(Prior Art) Generally, a double integration circuit is sometimes used for signal detection and measurement. For example, JP-A-57-148423
No. 2 has been disclosed. In this case, as _shown in Figure ₉ , the input voltage _V The time _tX until the return time tX is measured, and the measured input voltage _VX is detected from this return time _tX . In other words, _there is _a relationship between the parameters t ₀ , t _X , V _{0 ,} and _{V X} as t ₀ ×V _X = _t V _X can be found by measuring .

(Problem that the invention attempts to solve) However, according to such a double integration circuit, when the input voltage V _X is large, the measurement time t _X becomes long, and when the input voltage _V time to calculate
Although _t For this reason, even if the conventional double integration circuit is used as is, it is difficult to easily measure input signals with high precision in a short time.

Therefore, this invention utilizes a double integration circuit,
It is an object of the present invention to provide a small signal detection circuit that can perform good detection even if the input signal is small.

(Means and actions for solving the problem) In order to achieve this purpose, according to this invention,
An AC amplifier 5 that amplifies an input signal, an inversion circuit 7 that inverts the amplified output of this amplifier 5, and an AC amplifier 5 that amplifies an input signal;
The outputs of the amplifier 5 and the inverting circuit 7 are sequentially integrated for the same time in a constant polarity direction within a first integration time, and then integrated in a predetermined second integration time in the opposite polarity direction using a predetermined reference signal. Double integration circuit 9
and a determination circuit 11 that determines whether the output value of this double integration circuit 9 is larger or smaller than a predetermined threshold at the end of the second integration time of this double integration circuit 9. Be prepared.

According to such a configuration, when there is an input signal, AC amplification is performed according to the magnitude of the input signal, and a light reception change signal at the moment when the light is emitted and a light reception change signal at the moment when the light emission is turned off are generated. By performing integration and double integration for a limited time, reliable signal discrimination is possible even in a short time.

(Embodiments of the invention) Examples of the invention will be described below with reference to the accompanying drawings. Note that the same reference numerals in each figure indicate similar objects.

FIG. 1 is a system diagram of a small signal detection circuit according to an embodiment of this invention. According to the figure, a signal (S ₁ ) detected by a signal detection circuit 1 is amplified by an AC signal amplification circuit 3 to become a signal (S ₂ ), which is further input to an AC signal amplifier 5. The output (S ₃ ) of the AC signal amplification circuit 5 is supplied to the double integration circuit 9 and is also input to the inversion circuit 7 to invert the polarity and form an inversion signal (S ₄ ). This inverted signal (S ₄ ) is also supplied to the double integration circuit 9. The integral timing control circuit 10 determines the timing of supplying such a signal (S ₃ ) and the inverted signal (S ₄ ) to the double integration circuit 9, and causes the double integration circuit 9 to perform a predetermined integration operation. The output signals are ( _S5 ) to ( _S7 ). The final integrated value (S ₈ ) of the double integration circuit 9 is compared with the reference signal of the determination circuit 11, and the signal detection circuit 1
It is determined whether the detected signal (S ₁ ) is a signal to be considered. These will be explained in detail below.

FIG. 2 has a signal detection circuit 1 consisting of a phototransistor 20 and a transistor 21 connected in Darlington, and an AC signal amplification circuit 3 at the subsequent stage.
An AC signal amplification group 5 and an inversion circuit 7 are shown. These circuits are biased by the reference voltage generating circuit (FIG. 4) which rises to the reference voltage V _R as shown in FIG. 3a when the power of the entire circuit is turned on. The signal detection circuit 1 is
When the phototransistor 20 receives a predetermined input signal, it generates a detection signal (S ₁ ) as shown in FIG. 3b. However, as shown in Figure 5, the signal light (A) may arrive superimposed on the external light disturbance (B) (for example, when detecting the signal light under electric lighting, The ambient illuminance (L) varies with time (t) based on the power supply frequency), and it is necessary to eliminate the influence of this disturbance (B) in order to perform reliable signal detection. Otherwise, if the signal is small with respect to the disturbance, the signal at time (t ₁ ) will be detected, but the signal at time (t ₂ ) will not be detected. For this purpose, AC amplification with different gains is performed on the input signal frequency using the signal amplification circuit 3 and the amplifier 5 having operational amplifiers 22 and 23.
We are trying to eliminate the effects of such disturbances. The output signal (S ₂ ) of such a signal amplification circuit 3
is as shown in FIG. 3c, and is amplified by the AC signal amplifier 5 (an AC amplifier may be used) to obtain an AC amplified signal (S ₃ ) as shown in FIG. 3d. The falling signal (S ₃ a) of this output signal (S ₃ ) indicates the start time (falling edge) of the detection signal (S ₁ ), and the rising signal (S ₃ b) indicates the end time of the detection signal S ₁ (rise). Furthermore, these signals (S ₃ a) and (S ₃ b) include waviness due to disturbance.

Then, the double integration circuit 9 first integrates the falling signal (S ₃ a). Next, the rising signal (S ₃ b) is inverted by the inverting circuit 7, and the resulting inverted signal (S ₄ b) is integrated.

Finally, by adding these two integral values, an integral value (-(S ₃ a+S ₄ b)) of the detection signal is obtained in which the waviness due to disturbance is canceled. In other words, since the disturbance is considered to be approximately equal before and after the inversion, the sum of the inverted and non-inverted disturbances is approximately zero. Therefore, the originally necessary integral value can be obtained by removing the disturbance component, and effective integration is possible even for minute signals.

FIG. 6 shows the configuration around the double integration circuit 9. According to the figure, the double integration circuit 9 is
operational amplifier 31, comparator 32, inverter 33,
It is equipped with a flip-flop 34, an output transistor 35, etc., and supplies each signal k (S ₃ ), l (S ₄ ), and reference signal V ₀ for inverse integration through analog switches 36 to 39, or a double integration circuit 9. A closed circuit is constructed to perform zeroing in which is in an integrable standby state. Analog switch 3 like this
The integral timing control circuit 10 (FIG. 1) drives the shift register 40 and the integral timing generating circuit 41 as shown in FIG.
Drive signal generation circuit 42, 1/2
It is operated by a frequency divider 43 and a flip-flop 44. FIG. 7 is a timing chart showing the output signals of each part in FIG. 6 including such components, and the symbols (a) to (m) of each waveform in FIG. ) to (m). In addition, when the same signal is given a code different from that in other drawings, the corresponding signal is written later in brackets in the drawing.

First, when the circuit starts up, the drive signal generation circuit 42
generates the clock signal (a) and also generates the reset signal (R ₁ ). This clock signal (a) is converted into a frequency-divided output (b) by a 1/2 cycle 43. The reset signal (R ₁ ) is sent to the shift register 40 and the frequency divider 43.
is cleared and flip-flop 44 is set. This frequency-divided output (b) is supplied to a shift register 40, and the shift register 40 is connected to a flip-flop 4.
It starts under the output signal (c) of 4. The activated shift register 40 outputs the outputs (Q ₁ ) to 1 of each stage according to the timing of the frequency-divided clock signal (b).
Signals (d) to (g) are sequentially generated at (Q ₄ ). Here, the first output (d) of the stage (Q ₁ ) of the shift register 40 is sent to the drive signal generation circuit 42 in order to reset the flip-flop 44 (by the (R ₂ ) signal), and is also sent to the analog The switch 39 is turned on, the input and output terminals of the operational amplifier 31 are shorted, the integrating capacitor is discharged, zeroing is executed, and the D latch is cleared. Then the second
The stage (Q ₂ ) of the shift register 40 that occurs in
The output (e) is input to an integral timing generation circuit 41, which divides the duration of the signal (e) into signals (i) and (j). The signal (i) turns on the analog switch 36, supplies the output signal (k) (S ₃ ) of the AC signal amplifier 5 (Fig. 1 or 2) to the double integration circuit 9, and starts integration. . The signal (j) following this signal (i) turns on the analog switch 37 and generates an inverted signal l( S ₄ ) is supplied to the double integration circuit 9 and the integration is subsequently performed. Third
The stage of the shift register 40 (Q ₃ ) that occurs in
The output (f) turns on the analog switch 38, supplies the reference signal _V0 , and causes the double integration circuit 9 to start integration in the opposite direction (inverse integration).
The output (p) of such a double integration circuit 9 is obtained at the output terminal of the operational amplifier 31, and the state of this output (p) is
Shown in Figure p. The determination circuit 11 consists of a comparator 32, an inverter 33, a D latch 34, and a transistor 35, and the comparator compares the integral output p with a reference voltage. The comparison output is shaped into a logic signal by an inverter 33 and is input to the D latch.

The output (g) of the fourth stage (Q ₄ ) of the shift register 40 is clocked into the D latch to provide decision timing. Therefore, the determination circuit 11 latches the comparison result between the output integral value (p) of the double integration circuit 9 at the time when the timing signal (m) is generated and its own reference value, and determines the input signal (S ₁ ). Determine whether it is a necessary detection signal. For example, the curve (p1) in FIG. 7 p is determined to be a detection signal, and the curve (p2) is determined not to be a detection signal.

A minute signal detection circuit having such a double integration circuit 9 can be used, for example, in a water supply control device as shown in FIG. According to this type of water supply control device, the light projection driver 7 of the sensor unit 70
An amplifier circuit 3 (corresponding to the signal detection circuit 1 and signal amplification circuit 3 in FIG. 1, respectively) having a sensor 1 detects infrared light reflected by the human body 72 generated by the sensor 1. At this time, since the reflected light is extremely weak and is affected by disturbances such as indoor lighting, desirable control can be achieved by equipping the detection unit 80 with the aforementioned double integration circuit 9 and determination circuit 11.

(Effects of the invention) According to this invention, by AC amplifying the input signal as described above and performing double integration for a certain period of time based on this amplified signal, accurate detection signal discrimination can be performed even in a short time. It is possible to obtain a small signal detection circuit that is capable of Furthermore, since the integration is performed using the AC amplified signal and its inverted signal, the influence of disturbance can be eliminated.

[Brief explanation of the drawing]

Fig. 1 is a schematic system diagram of a small signal detection circuit according to an embodiment of this invention, Fig. 2 is a main part system diagram of a small signal detection circuit according to an embodiment of this invention, and Fig. 3 is a schematic diagram of each part of Fig. 2. FIG. 4 is a circuit diagram of another main part of the minute signal detection circuit according to the embodiment of this invention.
FIG. 5 is an explanatory diagram of the operation of the main parts of the small signal detection circuit according to the embodiment of this invention, FIG. 6 is a system diagram of the main parts of the small signal detection circuit according to the embodiment of this invention, and FIG. FIG. 8 is a system diagram of an application example of the minute signal detection circuit according to the embodiment of the present invention, and FIG. 9 is an explanatory diagram of the operation of the conventional device. In the drawing, 1 is a signal detection circuit, 3 and 5 are AC signal amplification circuits, 5 is an AC signal amplifier, 7 is an inversion circuit, 9 is a double integration circuit, 10 is an integration timing control circuit, 11 is a judgment circuit, and V ₀ is the reference signal.

Claims (1)

[Scope of utility model registration request] An AC amplifier that amplifies an input signal, an inversion circuit that inverts the output of this AC amplifier, and a first
Integrate in a certain polarity direction within an integration time of , and then integrate in a predetermined second
A double integration circuit that integrates within an integration time of A small signal detection circuit comprising a judgment circuit for making a judgment.