JPH0541409A - Adhesive agent and packaging structure using same - Google Patents
Adhesive agent and packaging structure using sameInfo
- Publication number
- JPH0541409A JPH0541409A JP22100891A JP22100891A JPH0541409A JP H0541409 A JPH0541409 A JP H0541409A JP 22100891 A JP22100891 A JP 22100891A JP 22100891 A JP22100891 A JP 22100891A JP H0541409 A JPH0541409 A JP H0541409A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- circuit board
- semiconductor chip
- adhesive agent
- curing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップ等の電子
部品の実装に関し、特にその接着剤及び実装構造に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mounting electronic parts such as semiconductor chips, and more particularly to an adhesive and a mounting structure thereof.
【０００２】[0002]
【従来の技術】ＳｉやＧａＡｓを材料に用いた半導体チ
ップを回路基板に実装する方法として、フリップチップ
法がある。これは、バンプ（突起電極）が形成された半
導体チップをフェイスダウン方式で、回路基板に接続す
る方法である。2. Description of the Related Art A flip chip method is known as a method for mounting a semiconductor chip using Si or GaAs as a material on a circuit board. This is a method of connecting a semiconductor chip having bumps (projection electrodes) to a circuit board by a face-down method.
【０００３】図１に、従来例を示す。同図は、回路基板
10に半導体チップ11を接続した状態の断面図である。こ
こで、12は半導体チップ11上にハンダや金などで形成さ
れたバンプ電極であり、回路基板10上のＩＴＯ（Indium
Tin Oxide）膜などで形成された配線パターン13と接続
される。14は半導体チップ11と回路基板10を固定するた
めの接着剤で、樹脂などが使用される。この樹脂14は、
通常、紫外線などで硬化する光硬化樹脂で、回路基板10
が液晶ガラスなどのように透明であるような場合に、回
路基板10の底面（紙面下方）から、例えば紫外線を照射
し、樹脂14を硬化させることによって、半導体チップ11
と回路基板10を固定するようにしている。FIG. 1 shows a conventional example. The figure shows a circuit board
FIG. 3 is a cross-sectional view showing a state in which a semiconductor chip 11 is connected to 10. Here, 12 is a bump electrode formed of solder or gold on the semiconductor chip 11, and is an ITO (Indium) on the circuit board 10.
It is connected to the wiring pattern 13 formed of a tin oxide film or the like. Reference numeral 14 denotes an adhesive for fixing the semiconductor chip 11 and the circuit board 10, and resin or the like is used. This resin 14 is
A circuit board 10 that is usually a photo-curing resin that cures with ultraviolet rays.
When the semiconductor chip 11 is transparent such as liquid crystal glass, the semiconductor chip 11 is cured by irradiating, for example, ultraviolet rays from the bottom surface of the circuit board 10 (below the paper surface) to cure the resin 14.
The circuit board 10 is fixed.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上述の
ような方法では、単に樹脂14を硬化させたにとどまり、
バンプ電極12と配線パターン13は、接触しているだけで
あるので、接触不良を起こしてしまうことがあった。ま
た、光硬化樹脂を接着剤として用いる場合、光を照射す
ることができないような構造、材料を使用するとき、具
体的には回路基板が透明でないセラミック等を使用した
ときは、このような接着剤を用いた方法では実装できな
いという不具合が生じていた。本発明は、このような問
題を解決し、半導体チップと回路基板の接続において、
接触不良を起こすことのない接着剤及び実装構造を提供
することを目的とする。However, in the method described above, the resin 14 is merely cured, and
Since the bump electrode 12 and the wiring pattern 13 are only in contact with each other, contact failure may occur. In addition, when using a photo-curing resin as an adhesive, when using a structure or material that cannot irradiate light, specifically, when the circuit board uses a non-transparent ceramic, etc. There was a problem that it could not be mounted by the method using the agent. The present invention solves such a problem, and in connecting a semiconductor chip and a circuit board,
An object of the present invention is to provide an adhesive and a mounting structure that do not cause poor contact.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明の接着剤は、所定の条件を印加することによ
り硬化による接着の機能を有し、前記条件と異なる条件
を印加することにより収縮の機能を有するもので、例え
ば、所定の温度によって硬化する熱硬化性接着剤と、前
記熱硬化性接着剤中に施され、前記所定の温度よりも高
い温度によって収縮する熱収縮粒子とから成る。また、
本発明の実装構造は、半導体のチップ等の部品を回路基
板に実装するときの実装構造であって、所定の条件を印
加することにより硬化による接着の機能を有し、前記条
件と異なる条件を印加することにより収縮の機能を有す
る接着剤の硬化により前記部品と回路基板を接着し、接
着剤の収縮による収縮応力で両者を圧接している。In order to achieve the above object, the adhesive of the present invention has a function of adhesion by curing by applying a predetermined condition, and by applying a condition different from the above condition. Having a function of shrinking, for example, from a thermosetting adhesive that cures at a predetermined temperature, and heat-shrinkable particles that are applied to the thermosetting adhesive and shrink at a temperature higher than the predetermined temperature. Become. Also,
The mounting structure of the present invention is a mounting structure when a component such as a semiconductor chip is mounted on a circuit board, and has a function of adhesion by curing by applying a predetermined condition, and a condition different from the above condition is applied. The component and the circuit board are adhered by curing the adhesive having the function of contracting by applying, and the two are pressed against each other by the contracting stress due to the contraction of the adhesive.
【０００６】[0006]
【作用】このようにすると、接着剤は、接着だけでなく
収縮機能も有しているので、例えば、半導体チップのバ
ンプ電極と回路基板の配線パターンが収縮によって圧接
され、接触不良が起こるようなことがない。さらに、硬
化による接着において、例えば、硬化の条件が加熱であ
るような接着剤を用いれば、光を照射できない場合でも
問題はない。In this case, since the adhesive has not only adhesion but also contraction function, for example, the bump electrode of the semiconductor chip and the wiring pattern of the circuit board are pressed against each other due to contraction, resulting in poor contact. Never. Further, in adhesion by curing, if an adhesive whose curing condition is heating is used, there is no problem even when light cannot be irradiated.
【０００７】[0007]
【実施例】以下、本発明の実施例を図面を参照しつつ、
説明する。図２に、本発明を実施した接着剤20の簡略化
した構造を示す。同図において、21は熱硬化性接着剤で
あり、22は21に添加された熱収縮粒子である。21及び22
は、いずれも加熱という条件で硬化あるいは収縮を行な
うが、その硬化、収縮が開始する温度は異なっている。
加熱により、熱硬化性接着剤21及び熱収縮粒子22は、実
線の状態から破線の状態に体積収縮を起こす。前記接着
剤20を使用する場合、まず熱硬化性接着剤21が硬化する
温度に加熱して硬化させることによって、回路基板10と
半導体チップ11を接着する。その後、熱収縮粒子22が収
縮する温度に加熱して収縮させることによって熱収縮粒
子22の体積収縮分だけ接着剤20が収縮し、それに伴なう
応力によって回路基板10の配線パターン13と半導体チッ
プ11のバンプ電極12が圧接される。Embodiments of the present invention will now be described with reference to the drawings.
explain. FIG. 2 shows a simplified structure of the adhesive 20 embodying the present invention. In the figure, 21 is a thermosetting adhesive and 22 is a heat-shrinkable particle added to 21. 21 and 22
Both of them cure or shrink under the condition of heating, but the temperatures at which the curing and shrinkage start are different.
Upon heating, the thermosetting adhesive 21 and the heat-shrinkable particles 22 undergo volume shrinkage from the solid line state to the broken line state. When the adhesive 20 is used, first, the circuit board 10 and the semiconductor chip 11 are bonded to each other by heating and curing the thermosetting adhesive 21 to a temperature at which the adhesive 21 is cured. After that, the adhesive 20 is contracted by the volume contraction of the heat-shrinkable particles 22 by heating the heat-shrinkable particles 22 to a temperature at which the heat-shrinkable particles 22 are shrunk, and the accompanying stress causes the wiring pattern 13 of the circuit board 10 and the semiconductor chip. The bump electrodes 12 of 11 are pressed.
【０００８】図３に、上述の接着剤20を用いて、回路基
板10と半導体チップ11の接続を行なった場合の実装構造
を示す。図１と較べ、回路基板10上の配線パターン13と
半導体チップ11のバンプ電極12の接触の強度が違う。図
３に示す構造の方が圧接された状態であり、より強度が
大きく、実装の信頼性が向上する。FIG. 3 shows a mounting structure in which the circuit board 10 and the semiconductor chip 11 are connected using the above-mentioned adhesive 20. Compared to FIG. 1, the contact strength between the wiring pattern 13 on the circuit board 10 and the bump electrode 12 of the semiconductor chip 11 is different. The structure shown in FIG. 3 is in a state of being pressure-welded, has higher strength, and improves reliability of mounting.
【０００９】図３において、回路基板10が透明で光の照
射が可能である場合は、接着剤20は光硬化性樹脂に熱収
縮粒子を混入したものを使用することができる。この場
合、熱収縮粒子を混入しないときに比較して、接触不良
が起こりにくいのはいうまでもない。In FIG. 3, when the circuit board 10 is transparent and can be irradiated with light, the adhesive 20 may be a photocurable resin mixed with heat-shrinkable particles. In this case, it goes without saying that contact failure is less likely to occur as compared with the case where the heat-shrinkable particles are not mixed.
【００１０】上述の接着剤及び実装構造は、半導体チッ
プに限らず、容量や抵抗などの電子部品の回路基板への
実装にも応用できる。The above-mentioned adhesive and mounting structure can be applied not only to semiconductor chips but also to mounting electronic components such as capacitors and resistors on circuit boards.
【００１１】[0011]
【発明の効果】以上説明したように、本発明によれば、
回路基板と半導体チップの接続を、硬化と収縮の両方の
機能を備えた接着剤を用いて行なうので、接続の強度が
増し、従って実装の信頼性が向上する。また、加熱によ
り硬化を生じる接着剤を用いれば、光の照射ができない
材料の回路基板の場合にも、容易に実装を行なうことが
できる。As described above, according to the present invention,
Since the connection between the circuit board and the semiconductor chip is performed by using the adhesive having both the function of curing and the function of contracting, the strength of the connection is increased and therefore the reliability of mounting is improved. Further, by using an adhesive that is cured by heating, it is possible to easily mount even a circuit board made of a material that cannot be irradiated with light.
【図１】 従来の実装構造を説明するための図。FIG. 1 is a diagram for explaining a conventional mounting structure.
【図２】 本発明を実施した接着剤の構造を示す図。FIG. 2 is a diagram showing a structure of an adhesive embodying the present invention.
【図３】 本発明を実施した実装構造を示す図。FIG. 3 is a diagram showing a mounting structure embodying the present invention.
10 回路基板 11 半導体チップ 12 バンプ電極 13 配線パターン 14 接着剤 20 接着剤 21 熱硬化性接着剤 22 熱収縮粒子 10 Circuit board 11 Semiconductor chip 12 Bump electrode 13 Wiring pattern 14 Adhesive 20 Adhesive 21 Thermosetting adhesive 22 Heat shrinkable particles
Claims (3)
よる接着の機能を有し、 前記条件と異なる条件を印加することにより収縮の機能
を有することを特徴とする接着剤。1. An adhesive characterized in that it has a function of adhesion by curing when a predetermined condition is applied, and has a function of shrinking when a condition different from the above condition is applied.
着剤と、 前記熱硬化性接着剤中に施され、前記所定の温度よりも
高い温度によって収縮する熱収縮粒子と、 から成ることを特徴とする請求項１に記載の接着剤。2. A thermosetting adhesive which cures at a predetermined temperature, and heat-shrinkable particles which are applied to the thermosetting adhesive and shrink at a temperature higher than the predetermined temperature. The adhesive agent according to claim 1.
装するときの実装構造であって、 所定の条件を印加することにより硬化による接着の機能
を有し、前記条件と異なる条件を印加することにより収
縮の機能を有する接着剤の硬化により前記部品と回路基
板を接着し、接着剤の収縮による収縮応力で両者を圧接
していることを特徴とする実装構造。3. A mounting structure for mounting a component such as a semiconductor chip on a circuit board, which has a function of adhesion by curing by applying a predetermined condition, and applies a condition different from the above condition. Thus, the mounting structure characterized in that the component and the circuit board are adhered by curing an adhesive having a contracting function, and the two are pressed against each other by the contracting stress due to the contraction of the adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22100891A JP2655768B2 (en) | 1991-08-05 | 1991-08-05 | Adhesive and mounting structure using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22100891A JP2655768B2 (en) | 1991-08-05 | 1991-08-05 | Adhesive and mounting structure using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0541409A true JPH0541409A (en) | 1993-02-19 |
| JP2655768B2 JP2655768B2 (en) | 1997-09-24 |
Family
ID=16760035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22100891A Expired - Fee Related JP2655768B2 (en) | 1991-08-05 | 1991-08-05 | Adhesive and mounting structure using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2655768B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5783867A (en) * | 1995-11-06 | 1998-07-21 | Ford Motor Company | Repairable flip-chip undercoating assembly and method and material for same |
| US6166433A (en) * | 1998-03-26 | 2000-12-26 | Fujitsu Limited | Resin molded semiconductor device and method of manufacturing semiconductor package |
| US6774493B2 (en) * | 1997-07-21 | 2004-08-10 | M. A. Capote | Semiconductor flip-chip package and method for the fabrication thereof |
| US6933610B2 (en) * | 2002-02-20 | 2005-08-23 | Silicon Pipe, Inc. | Method of bonding a semiconductor die without an ESD circuit and a separate ESD circuit to an external lead, and a semiconductor device made thereby |
-
1991
- 1991-08-05 JP JP22100891A patent/JP2655768B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5783867A (en) * | 1995-11-06 | 1998-07-21 | Ford Motor Company | Repairable flip-chip undercoating assembly and method and material for same |
| US6774493B2 (en) * | 1997-07-21 | 2004-08-10 | M. A. Capote | Semiconductor flip-chip package and method for the fabrication thereof |
| US6166433A (en) * | 1998-03-26 | 2000-12-26 | Fujitsu Limited | Resin molded semiconductor device and method of manufacturing semiconductor package |
| US6933610B2 (en) * | 2002-02-20 | 2005-08-23 | Silicon Pipe, Inc. | Method of bonding a semiconductor die without an ESD circuit and a separate ESD circuit to an external lead, and a semiconductor device made thereby |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2655768B2 (en) | 1997-09-24 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |