JPH0541083A - Semiconductor storing device - Google Patents

Abstract

PURPOSE:To rapidly write without enlarging the size of a transistor constituting a write amplifier to be unfavorable to high integration on a semiconductor storing device provided with plural memory blocks. CONSTITUTION:This device is provided with a read memory block selecting gate part 26 and a write memory block selecting gate part 27, a data is read in accordance with a following route: memory cell bit line sense amplifier sub data bus sub data bus latch main data bus 8 main data bus latch 9 and the data is written in accordance with a following route: write amplifier 10 sub data bus bit line memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a plurality of memory blocks formed by dividing a memory cell array.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device of this type,
There is proposed a device whose main part is shown in FIG. The semiconductor memory device is a DRAM, in FIG, ₁ 1 to 1 ₄
The memory block, 21 _{to 24} memory blocks ₁ 1 to 1 ₄ of the memory cell array portion, respectively, 3 ₁ to 3 ₄ sense amplifier portion of the memory blocks ₁ 1 to 1 _4, respectively, 41 _to each of the memory ₄ column of blocks ₁ 1 to 1 ₄ (column) is selected gate portion.

[0003] 5 ₁ to 5 ₄ are sub data buses provided for each memory block ₁ 1 to 1 _4, respectively, ₆₁ through ₄ drives the sub-data bus 5 ₁ to 5 _4, respectively, the sub-data bus 5 ₁ to 5 sub data bus latch for latching the data read in _4, 7 is a memory block selection gate section for selecting a memory block to input and output data.

Reference numeral 8 is a main data bus commonly provided for the sub data buses 5 _{1 to} 5 ₄ , and 9 is main data for driving the main data bus 8 and latching the data read by the main data bus 8. Bus latch, 10 is a write amplifier used for writing data, DO is output data,
DI is input data.

[0005] FIG. 6 is a sense amplifier portion 3 ₁ of the memory block 1 ₁ is a circuit diagram showing in more detail a portion of the column select gate portion 4 ₁ and the sub-data bus 5 _1, the other memory blocks 1 ₂ - 1 ₄ sense amplifier 3 _{2-3 4,} column selection gate 4 _{2-4 4} and the sub-data bus 5 _{2-5 4} are similarly constructed.

[0006] Incidentally, in FIG. 6, BL ₁ to BL ₁₆ bars bit lines, 11 ₁ to 11 ₁₆ sense amplifiers included in the sense amplifier unit 3 _1, 12 ₁ to 12 ₃₂ column selecting gate 4 ₁
NMOS, and 13 _{1 to} 13 ₄ are sub-data buses
It is a latch for each bit that constitutes the latch 6 ₁ .

Further, FIG. 7 shows a sub data bus latch 6
_{1-6 4,} the memory block selection gate section 7, the main data bus 8 is a circuit diagram showing in more detail a portion of the main data bus latches 9 and the write amplifier 10, 14 ₁ to 1
4 ₄ latches for each bit that constitutes the sub-data bus latch 6 _2, 15 ₁ to 15 ₄ are sub data bus latch 6 ₃
And 16 _{1 to} 16 ₄ are latches for each bit constituting the sub data bus latch 6 ₄ .

Further, 17 _{1 to} 17 ₃₂ are nMOSs constituting the memory block selection gate section 7, 18 ₁ to 18 ₄ are latches for respective bits constituting the main data bus latch 9, and 19 _{1 to} 19 ₄ are write. It is an amplifier for each bit that constitutes the amplifier 10.

In the memory block selection gate section 7, the nMOSs 17 _{1 to} 17 ₈ are ON and the nMOS 17 is turned on.
_{When 9 to} 17 ₃₂ are turned off, the sub data bus 5 ₁ and the main data bus 8 are connected and the memory block 1 ₁ is selected.

Further, nMOSs 17 _{9 to} 17 ₁₆ are ON, n
When the MOSs 17 _{1 to} 17 ₈ and 17 _{17 to} 17 _{3 2} are turned off, the sub data bus 5 ₂ and the main data bus 8 are connected and the memory block 1 ₂ is selected.

Further, the nMOSs _{17 17 to} 17 ₂₄ are ON, n
When _{MOS17 1 ~17 16, 17 25 ~17} 32 is OFF, the the sub-data bus 5 ₃ and the main data bus 8 is connected, the memory block 1 ₃ is selected.

Further, the nMOSs 17 _{25 to} 17 ₃₂ are ON, n
When MOS17 ₁ ~17 ₂₄ is OFF, the connected and the sub-data bus 5 ₄ and the main data bus 8, the memory block 1 ₄ is selected.

In such a conventional semiconductor memory device,
Sense amplifiers are connected to the bit lines, sub data bus latches 6 _{1 to} 6 ₄ are connected to the sub data buses 5 _{1 to} 5 ₄ , and data bus latch 9 is connected to the main data bus 8. , Data read from memory cell → bit line → sense amplifier → sub data bus → sub data bus
Since the process is performed in the route of latch → main data bus 8 → main data bus / latch 9, the driving load at the time of reading is not so large, and high-speed reading can be performed.

[0014]

However, the writing of data is performed by the write amplifier 10 → the main data bus 8 →
The write amplifier 10 must drive the main data bus 8, the sub data bus, and the bit line because the operation is performed in the path of the sub data bus → bit line → memory cell, and the drive load is large. In order to do so, it is necessary to make the size of the transistor that constitutes the write amplifier 10 very large, which hinders high integration.

In view of the above point, the present invention provides a semiconductor memory device capable of increasing the writing speed without increasing the size of the transistor constituting the write amplifier, which is disadvantageous for high integration. The purpose is to

[0016]

FIG. 1 illustrates the principle of the present invention.
It is a figure. 20 in the figure₁, 20₂... 20_nIs a memory card
A memory block formed by dividing the rule array, 21₁, 21₂
... 21_nIs the memory block 20₁, 20₂... 20_n
Sub data bus provided for each
Tabas 21₁, 21₂... 21_nDesired sub from
By selecting the data bus, the memory block 20
₁, 20₂... 20_nSelect the desired memory block from
Memory block selecting means for selecting, 24 is a sub-data bus
Space 21 ₁, 21₂... 21_nMemory provided in common
Sub data bus 2 via block selecting means 22
1₁, 21₂... 21_nOut of the selected sub-data
Main data bus to which the bus is connected, 25 is a memory block
Sub data bus 21 via the clock selection means 23.₁Two
1₂... 21_nSelected sub-data bus
Is a light amplifier connected to the output side of the
The semiconductor memory device has a memory
Reblock 20₁, 20₂... 20_nSelected out of
Memory block sub data bus, memory block selection
Selector 22 and main data bus 24
For writing data, write amplifier 25, memory
Lock selection means 23 and memory block 20₁, 20₂・
・ ・ 20 _nOf the selected memory block
It is done via a data bus.

[0017]

According to the present invention, data is written via the sub-data bus of the memory block selected from the write amplifier 25, the memory block selecting means 23 and the memory blocks 20 ₁ , 20 ₂ ... 20 _n. The write amplifier 25 does not need to drive the main data bus 24, and the drive load is reduced accordingly.
Therefore, the writing speed can be increased without increasing the size of the transistor forming the write amplifier 25, which is disadvantageous for high integration.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 2 to 4 by taking the case where the present invention is applied to a DRAM as an example. 2 to 4, parts corresponding to those in FIGS. 5 to 7 are designated by the same reference numerals, and duplicate description thereof will be omitted.

FIG. 2 is a circuit diagram showing an essential part of one embodiment of the present invention. The semiconductor memory device of this embodiment is different from the conventional semiconductor memory device shown in FIG. Instead of the read memory block selection signal R
A read memory block selection gate unit 26 controlled by MBS _{1 to} RMBS ₄ and a write memory block selection gate unit 27 controlled by write memory block selection signals WMBS _{1 to} WMBS ₄ are provided, and sub data buses 5 ₁ , 5 are provided. The connection between ₂ , 5 ₃ or 5 ₄ and the main data bus 8 is made via the read memory block selection gate section 26, and the write amplifier 10 and the sub data buses 5 ₁ , 5 ₂ , 5 _{3 are connected.}
Or connection between the 5 ₄ is that is configured to perform through the write memory block selection gate portion 27.

FIG. 3 is a circuit diagram showing the read memory block selection gate section 26 in more detail.
28 _{1 to} 28 ₃₂ are read memory block selection gate units 2
6 is an nMOS.

In the read memory block selection gate section 26, the read memory block selection signal RMB
S ₁ is at H level, read memory block selection signal RMB
When S _{2 to} RMBS ₄ are set to L level, nMOS 28 ₁ to
28 ₈ is ON, nMOS 28 _{9 to} 28 ₃₂ is OFF,
The sub data bus 5 ₁ and the main data bus 8 are connected, and the memory block 1 ₁ is selected as the memory block to be read.

Further, the read memory block selection signal RM
BS ₂ is at H level, read memory block selection signal RM
When BS ₁ , RMBS ₃ , and RMBS ₄ are set to L level, n
MOS 28 _{9 to} 28 ₁₆ are ON, nMOS 28 _{1 to} 28 ₈ ,
28 _{17 to} 28 ₃₂ are turned off, the sub data bus 5 ₂ and the main data bus 8 are connected, and the memory block 1 ₂ is selected as the memory block to be read.

Further, the read memory block selection signal RM
BS ₃ is at H level, read memory block selection signal RM
When BS ₁ , RMBS ₂ , and RMBS ₄ are set to L level, n
MOS 28 _{17 to} 28 ₂₄ are ON, nMOS 28 ₁ to 2
8 ₁₆ and 28 _{25 to} 28 ₃₂ are turned off, the sub data bus 5 ₃ and the main data bus 8 are connected, and the memory block 1 ₃ is selected as the memory block to be read.

Further, a read memory block selection signal RM
BS ₄ is at H level, read memory block selection signal RM
When BS _{1 to} RMBS ₃ are set to L level, nMOS 28 ₂₅
To 28 ₃₂ ON, nMOS ₁ to 28 ₂₄ is turned OFF, is connected to the sub-data bus 5 ₄ and the main data bus 8, the memory block 1 ₄ is selected as the memory block to be read.

FIG. 4 is a diagram showing in detail the portion of the write memory block selection gate section 27, which is designated 29 ₁ to 2 _1.
9 ₈ , 30 ₁ to 30 ₈ , 31 _{1 to} 31 ₈ and 32 _{1 to} 32 ₈ are nMOs forming the write memory block selection gate section 27.
It is S. Incidentally, 33 _to 333 _{1 6} memory block 1 _{and second} sense amplifiers, 34 _{1-34 16} memory blocks 1 ₃ of the sense amplifier, 35 _{1-35 16} is a sense amplifier of the memory block 1 _4.

In the write memory block selection gate unit 27, the write memory block selection signal WMB
S ₁ is at H level, write memory block selection signal WMB
When S _{2 to} WMBS ₄ are set to L level, nMOS 29 ₁ to
29 ₈ is ON, nMOS 30 ₁ to 30 ₈ , 31 _{1 to} 31 ₈ ,
32 _{1 to} 32 ₈ are turned off, the write amplifier 10 and the sub data bus 5 ₁ are connected, and the memory block 1 ₁ is selected as the memory block to be written.

Further, a write memory block selection signal WM
BS ₂ at H level, write memory block selection signal WM
When BS ₁ , WMBS ₃ , and WMBS ₄ are set to L level, n
MOS 30 ₁ to 30 ₈ are ON, nMOS 29 _{1 to} 29 ₈ and 3
1 _{1-31 8,} 321 _to 323 ₈ is turned OFF, is connected to the write amplifier 10 and the sub-data bus 5 _2, the memory block 1 ₂ is selected as the memory block to be written in the subject.

Further, the write memory block selection signal WM
BS ₃ is at H level, write memory block selection signal WM
When BS ₁ , WMBS ₂ and WMBS ₄ are set to L level, n
MOS31 _{1 to} 31 ₈ is ON, nMOS 29 _{1 to} 29 ₈ and 3
0 ₁ - 30 _8, 321 _to 323 ₈ is turned OFF, is connected to the write amplifier 10 and the sub-data bus 5 _3, the memory block 1 ₃ is selected as the memory block to be written in the subject.

Further, the write memory block selection signal WM
BS ₄ is at H level, write memory block selection signal WM
When BS _{1 to} WMBS ₃ are set to L level, nMOS 32 ₁
To 32 ₈ are ON, nMOS 29 _{1 to} 29 ₈ and 30 _{1 to} 3
0 ₈ , 31 _{1 to} 31 ₈ are turned off, and the write amplifier 10
And the sub data bus 5 ₄ are connected, and the memory block 1 ₄ is selected as the memory block to be written.

In the semiconductor memory device of this embodiment, data reading is performed in the same manner as in the conventional semiconductor memory device shown in FIG. 5, memory cell → bit line → sense amplifier → sub data bus → sub data bus. -Latch-> main data bus 8-> main data bus-latch 9 is performed.

However, unlike the case of the conventional semiconductor memory device shown in FIG. 5, writing of data is performed in the route of write amplifier 10 → sub data bus → bit line → memory cell, and the write amplifier 10 is the main data. It is not necessary to drive the bus 8, and the driving load is reduced accordingly.

Therefore, according to the present embodiment, the writing speed can be increased without increasing the size of the transistor constituting the write amplifier 10 which is disadvantageous for high integration.

[0033]

According to the present invention, data is written through the write amplifier and the sub data bus of the selected memory block, and the write amplifier does not need to drive the main data bus. Since the driving load can be reduced, the writing speed can be increased without increasing the size of the transistor forming the write amplifier, which is disadvantageous for high integration.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 3 is a diagram showing in detail a read memory block selection gate unit that constitutes an embodiment of the present invention.

FIG. 4 is a diagram showing in detail a write memory block selection gate unit that constitutes an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a conventional semiconductor memory device.

FIG. 6 is a circuit diagram showing a part of a conventional semiconductor memory device in more detail.

FIG. 7 is a circuit diagram showing a part of a conventional semiconductor memory device in more detail.

[Explanation of symbols]

20 _{1 to} 20 _n memory block 21 _{1 to} 21 _n sub data bus 22, 23 memory block selecting means 24 main data bus 25 write amplifier DO output data DI input data

Claims (1)

[Claims] [Claim 1] and obtained by dividing the memory cell array a plurality of memory blocks (20 _1, 20 ₂ ... 20 _n), the plurality of memory blocks (20 _1, 20 ₂ ... 20
a plurality of sub-data buses (21 ₁ , 2) provided for each _n )
1 ₂ ... 21 _n ) and a plurality of sub data buses (21 ₁ , 21 ₂ ... 21)
By selecting a desired sub data bus from among _n ), the plurality of memory blocks (20 ₁ , 20 ₂ ... 2)
0 _n ), first and second memory block selecting means (22, 23) for selecting a desired memory block, and the plurality of sub data buses (21 ₁ , 21 ₂ ... 2)
1 _n ), selected sub-data among the plurality of sub-data buses (21 ₁ , 21 ₂ ... 21 _n ) via the first memory block selection means (22). Via a main data bus (24) to which a bus is connected and the second memory block selecting means (23),
The plurality of sub data buses (21 ₁ , 21 ₂ ... 2)
1 _n ), a selected sub-data bus has a write amplifier (25) connected to its output side, and data reading is performed by the plurality of memory blocks (2
0 ₁ , 20 ₂ ... 20 _n ) through the sub data bus of the selected memory block, the first memory block selecting means (22) and the main data bus (24), Is written to the sub memory of the selected memory block of the write amplifier (25), the second memory block selection means (23) and the plurality of memory blocks (20 ₁ , 20 ₂ ... 20 _n ). A semiconductor memory device characterized by being performed via a data bus.