JPH0537358A - Programmable logic circuit - Google Patents

Abstract

PURPOSE:To surely transfer an abnormality signal by forming a second logic circuit for inputting an output of a first logic circuit and inverting and outputting it, and sending out an output of a first logic circuit and an output of a second logic circuit to a logic circuit of the next stage. CONSTITUTION:In a first logic circuit 3, signals of input terminals IN1-IN3 are inputted to a logical gate 1-1 and to a second logic circuit 4, a signal obtained by inverting an output of the circuit 3 by an inverter, and a signal of the terminal IN1 are inputted. In this case, the terminal IN1 becomes an H level and to the IN2 and the IN3, a signal of is inputted simultaneously, respectively. In that case, under the condition that an abnormality signal is outputted, when the gates 1-1, 1-2 are set as AND gates, an output of the gate 1-1 and an output of the gate 1-2 become '1' and '0', respectively at the time of the condition for outputting the abnormality signal. In this case, an output of the next logic circuit 5 becomes '1', and at the timing of an inspection timing signal TT, the abnormality signal is sent out of an output terminal Q of an FF 6.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a programmable logic circuit that is programmable and capable of detecting abnormal conditions. A plurality of logic gates and a wiring connection section in which a plurality of wirings are arranged in a matrix are formed on one chip as a semiconductor integrated circuit, and the wirings of the wiring connection section are connected according to program data, whereby the logic gate is formed. Programmable logic circuits (PAL circuits) are known that connect together to form the desired logic circuit. Various electronic circuits can be configured by using a plurality of such programmable logic circuits. Further, it is desired that the normality of each part can be easily confirmed as the degree of integration is improved.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example.
˜41-4 is a 4-input AND gate, 42 is a wiring connection part, 43-1 to 43-4 are output buffers, IN1 to IN
Reference numeral 3 indicates an input terminal, OUT1 to OUT4 indicate output terminals, I indicates an inverter, and (1) and (2) indicate that the same symbols are connected.

The connection wiring portion 42 includes wirings L11 to L15,
L21 to L25, L31 to L35, L41 to L45 and wirings A to H, J, and K are arranged in a matrix, and the wiring A is connected to an output terminal of an inverter I whose input terminal is grounded. , The wiring B is directly grounded, the wiring C,
E and G are respectively connected to the input terminals IN1 to IN3 via two inverters I, and the wirings D, F and H are respectively connected to the input terminals IN1 to IN3 via one inverter I. Also, the wirings L11, L21, L31, L4
1 is an output buffer 43-
It is connected to the control terminals 1-43-4. Wiring L1
2 to L15, L22 to L25, L32 to L35, L42
To L45 are four-input AND gates 41-1 to 41-1, respectively.
The input terminal 41-4 is connected via a buffer gate indicated by a triangle.

In FIG. 4, between wirings A and L15, between wirings B and L11, between wirings C and L12, between wirings E and L13,
The case where the lines G and L14 are connected by program data is shown. Since "1" is added to the control terminal of the output buffer 43-1 from the inverter I, the output of the AND gate 41-1 is output to the output terminal OUT1. Can be sent to the next stage logic circuit. Another output buffer 43-
Since "0" is added from the inverter I to the control terminals of 2 to 43-4, the output buffers 43-2 to 43-4 are in the high impedance output state. Therefore, the input terminal IN
When "1" is added to each of 1 to IN3, the output of the AND gate 41-1 becomes "1", and the output terminal OUT
From 1 to the logic circuit of the next stage.

Various electronic circuits can be constructed by providing a combination of programmable logic circuits as described above. Further, by using a logic gate or a memory other than the AND gates 41-1 to 41-4, it is connected to the wiring connection portion 42.
It is also possible to adopt a configuration in which the desired logical processing is performed by connecting with each other.

FIG. 5 is an explanatory view of a test of a conventional example, showing a main part when the programmable logic circuits 51 and 52 are connected in cascade. The programmable logic circuit 51 is similar to the configuration shown in FIG. Although it includes AND gates 41-1 to 41-n, a wiring connection portion, and output buffers 43-1 to 43-n, the wiring connection portion is not shown. The programmable logic circuit 52 also includes a flip-flop 53, and a check timing signal is applied to the clock terminal C.
The output of the AND gate 41-1 is applied to the data terminal D via the output buffer 43-1. For example, if all three inputs of the AND gate 41-1 are "1" and an abnormality occurs, the output of the AND gate 41-1 is at the rising time of the inspection timing signal. When it is "1", the output terminal Q of the flip-flop 53 becomes "1". Therefore, it is possible to notify the maintenance person or the like of this "1" signal as an abnormal signal. The abnormal signal may be further input to the next programmable logic circuit and output from the last programmable logic circuit. In that case, it becomes possible to transfer the abnormal signal in consideration of various conditions, and the respective signals are latched by the inspection timing signal and transferred to the next stage.

[0007]

In the above-mentioned conventional example, the output is fixed at a high level ("1") due to, for example, an abnormality in the element of the AND gate 41-1 or an abnormality in the connection wiring portion. Or the output buffer 43-
When the output is fixed to the high level (“1”) due to the abnormality of 1, the data terminal D of the flip-flop 53
Is input to the output terminal Q, the output terminal Q becomes "1" according to the inspection timing signal, and an abnormal signal is output. That is, the abnormal signal is output when the output condition of the abnormal signal is not satisfied. On the contrary, the AND gate 41-1
Alternatively, when the output of the output buffer 43-1 is fixed at a low level (“0”), “0” is input to the data terminal D of the flip-flop 53 even if the output condition of the abnormal signal is satisfied, so that an error occurs. No signal will be output. That is, there is a drawback that the abnormality of the programmable logic circuit 51 cannot be transmitted to the programmable logic circuit 52 of the next stage. An object of the present invention is to ensure that an abnormal state can be transmitted.

[0008]

A programmable logic circuit according to the present invention will be described with reference to FIG. 1. Logic gates 1-1 to 1-n for a plurality of logical sums and logical products and a plurality of wirings. In a programmable logic circuit that connects the logic gates via the wiring connection unit 2 according to the program data, and the wiring connection unit 2 is arranged in a matrix. The formed first logic circuit 3 and the empty logic gates among the plurality of logic gates 1-1 to 1-n are connected by the wiring connection section 2, and the output of the first logic circuit 3 is input and inverted. The second logic circuit 4 for outputting is formed, and the output of the first logic circuit 3 and the output of the second logic circuit 4 are sent to the logic circuit of the next stage.
That is, the output terminal OU of the programmable logic circuit PAL1.
The configuration is such that inputs are made from T1 and OUT2 to the logic circuit 5 of the programmable logic circuit PAL2. In addition, 6 is a flip-flop, TT is a check timing signal, OUT3 to OU
Tn is an output terminal, and IN1 to IN3 are input terminals.

[0009]

The black circles in the wiring connecting portion 2 indicate the state in which the wirings are connected by the program data. Therefore, in the first logic circuit 3, the logic gate 1-1 is connected to the input terminal IN1.
The signal from IN3 is input. The second logic circuit 4 has a configuration in which the signal obtained by inverting the output of the first logic circuit 3 by the inverter and the signal at the input terminal IN1 are input. In this case, if the input terminal IN1 is set to a high level (“1”) and an abnormal signal is output when signals of “1” are simultaneously input to the input terminals IN2 and IN3, the logic gate 1-1, When 1-2 is a logical product gate, the output of the logical gate 1-1 is "1" and the logical gate 1-
The output of 2 becomes "0". In this case, the output of the logic circuit 5 at the next stage is set to "1", and the abnormal signal of "1" is transmitted from the output terminal Q of the flip-flop 6 at the timing of the inspection timing signal TT.

When the output of the output buffer (not shown) of the first logic circuit 3 is in an abnormal state of being fixed at a high level,
Even if the output of the logic gate 1-1 is "0", the output terminal OUT
1 becomes "1", and since the output obtained by inverting the output of the logic gate 1-1 is output from the logic gate 1-2, the output terminal OUT2 also becomes "1". In this case, since it can be known that the programmable logic circuit PAL1 is abnormal, the output of the logic circuit 5 is set to "1" and an abnormal signal is output. Therefore, the logic circuit 5 of the next stage is the programmable logic circuit P.
When the output terminal OUT1 of AL1 is "0", the output terminal OUT
Only when 2 is “1”, the logical configuration is such that the abnormal signal is not output, and in other cases, the logical configuration is such that the abnormal signal is output.

[0011]

EXAMPLE FIG. 2 is an explanatory view of an example of the present invention.
-1 to 11-4 are AND gates as logic gates, 1
2 is a plurality of wirings L11 to L15, L21 to L25, L3
1-L35, L41-L45 and wirings A-H, J, K are arranged in a matrix in a wiring connection portion, 13-1 to 13-
4 is an output buffer, 14-1 to 14-4, 15-1 to 1
5-4, 16, 17-1, 17-2, 18-1, 18-
2, 19-1 and 19-2 are inverters (I), 20-
1, 20-3 are first and second logic circuits, IN1 to IN3
Are input terminals, and OUT1 to OUT4 are output terminals.

Similar to the conventional example shown in FIG. 4, the connection wiring portion 12 has wirings L11 to L15, L21 to L25, L.
31 to L35, L41 to L45 and wirings A to H, J, and K are arranged in a matrix, the wiring A is connected to the output terminal of the inverter 16 whose input terminal is grounded, and the wiring B is It is grounded. The wirings C, E, and G are connected to the input terminals IN1 to IN3 by two inverters 17 respectively.
-1, 17-2 to 19-1 and 19-2, and the wirings D, F, and H are connected to the input terminals IN1 to IN, respectively.
3 through one inverter 17-1 to 19-1. Also, the wirings L11, L21, L31, L41
Are connected to the control terminals of the output buffers 13-1 to 13-4 via the inverters 14-1 to 14-4, respectively.
Wirings L12 to L15, L22 to L25, L32 to L3
5, L42 to L45 are respectively connected to the input terminals of four-input AND gates 41-1 to 41-4 via buffer gates indicated by triangles.

The wiring connection section 12 shows a case where points indicated by diamonds are connected by program data. Therefore,
The AND gate 11-1 outputs a logical product of the signal obtained by inverting the signal at the input terminal IN1 and the signals at the input terminals IN2 and IN3, and the inverter 14-1 is connected to the control terminal of the output buffer 13-1. Since "1" is added to the output terminal OUT of the AND gate 11-1,
It is sent from 1.

The logical product gate 11-2 has an input terminal IN.
The connection configuration outputs the logical product of the signals 1 to IN3,
Further, the inverter 14-is connected to the control terminal of the output buffer 13-2.
Since "1" is added from 2, the AND gate 13-2
Is output from the output terminal OUT2. If the first logic circuit 20-1 including the AND gate 11-2 is included, the second logic circuit 20-2 includes the AND gate 11-2.
-3 is vacant, the AND gate 11-3 is used to configure, and in the wiring connection portion 12, the wirings A, L33, L34, and L35 are connected as shown by a diamond, and The wirings B and L31 are connected, and the wirings K and L32 are also connected.
Are connected to each other, the output signal of the AND gate 11-2 of the first logic circuit 20-1 is inverted by the inverter 15-2, and the second logic circuit 20-2 is passed through the wirings K and L32.
Is input to the AND gate 11-3. The other input of the AND gate 11-3 is the wiring L3 connected to the wiring A.
3 to L35, a signal obtained by inverting the output signal of the AND gate 11-2 is output from the AND gate 11-3. The inverter 1 is connected to the control terminal of the output buffer 13-3.
Since "1" is added from 4-3, the AND gate 11
The output signal of -3 is transmitted from the output terminal OUT3. That is, the output signals of the output terminals OUT2 and OUT3 of the first and second logic circuits 20-1 and 20-2 are complementary when the respective parts are normal.

The AND gate 11-4 is connected to the wirings B and L4.
Since 5 are connected, one of the 4 inputs is always "0" and its output is "0" regardless of the other inputs.
Becomes Further, since "0" is added from the inverter 14-4 to the control terminal of the output buffer 13-4, the output buffer 13-4 is in the high impedance output state. That is,
This logic circuit is in an unused state.

In the logic circuit of the next stage, output terminals OUT1,
When the output signals from OUT2 and OUT3 are added and the first and second logic circuits 20-1 and 20-2 are normal, for example, an abnormal signal of "1" is output from the output terminal OUT2. Then, a signal of "0" is output from the output terminal OUT3. Thereby, the logic circuit in the next stage can be determined as a significant abnormal signal. Output terminal OUT
When "0" signal is output from 2, output terminal OUT
If, for example, non-complementary "0" is output from 3, it can be determined that the output buffer 13-2 of the first logic circuit 20-1 is abnormal.

FIG. 3 is an explanatory diagram of the logic circuit of the next stage. In FIGS. 3A and 3B, the case where the programmable logic circuits PAL1 and PAL2 are connected is shown. Output terminals OUT2 and OUT3 of PAL1
Corresponds to the output terminals OUT2 and OUT3 of the first and second logic circuits 20-1 and 20-2 of FIG. 21 is a logic circuit, 22 is a flip-flop, 23 is an inverter, 2
4 is a NAND circuit, 25 is an abnormal signal output terminal, 31 is a logic circuit, 32 is a flip-flop, 33 is an inverted output exclusive OR circuit, 34 is an OR circuit, 35 is an abnormal signal output terminal, and TT is an inspection timing signal. Is.

In FIG. 3A, the output terminals OUT2 and OUT3 of the preceding programmable logic circuit PAL1.
Is applied to the logic circuit 21 of the programmable logic circuit PAL2 at the next stage, the output signal of the logic circuit 21 is applied to the data terminal D of the flip-flop 22, and the test timing signal TT is applied to the clock terminal C of the flip-flop 22. Therefore, the logic circuit 21 outputs the output terminal O
When UT2 = “0” and OUT3 = “1”, the output signal is set to “0”, and under other conditions, the output signal is set to “1”.
It is what Therefore, the programmable logic circuit P
When the abnormal signal is not output from AL1, the flip-flop 22 is not set even by the inspection timing signal TT, so that the abnormal signal is not output from the output terminal 25.

When a "0" signal is applied to the logic circuit 21 from the output terminal OUT2 and a "0" signal is applied to the logic circuit 21 from the output terminal OUT3, the output signal of the logic circuit 21 is "1". "It becomes. That is, since the signals are not complementary signals, the flip-flop 22 is set by the inspection timing signal TT, and the abnormal signal of “1” is output from the output terminal 25. In this case, the "0" fixed fault of the output buffer 13-2 of the first logic circuit 20-1 of the programmable logic circuit PAL1, or the AND gate 11-3 or the output buffer 13 of the second logic circuit 20-2. It can be determined that the fixed fault is "0" of -3.

When the abnormal signal of "1" is output from the output terminal OUT2 of the programmable logic circuit PAL1, the output signal of the logic circuit 21 is always "1". It is set by the signal TT, and the abnormal signal of "1" is output from the output terminal 25. Therefore, the programmable logic circuit PAL
When the AND signal 11-2 of the first logic circuit 20-1 of No. 1 outputs the abnormal signal of “1”, the output buffer 1
Even when the abnormal signal of "1" cannot be output due to the fixed fault of "0" of 3-2, the output signal of the second logic circuit 20-2 becomes "0", and the logic circuit 21 of the programmable logic circuit PAL2 becomes Since it can be determined that the logic circuit in the preceding stage has an abnormality, the abnormality signal of "1" is output to the output terminal 25.
Can be output from.

Further, in FIG. 3B, the logic circuit 31 of the programmable logic circuit PAL2 is supplied from the inverted output exclusive OR circuit 33 which inputs the signals of the output terminals OUT2 and OUT3 of the programmable logic circuit PAL1. Composed,
When these signals are not complementary, a signal of "1" is output and input to the OR circuit 34. Since the signal of the output terminal OUT2 is input to the data terminal D of the flip-flop 32, the output terminal OUT2 = from the output terminal 35.
The signal of "0" is output only when "0" and OUT3 = "1", and the abnormal signal of "1" is output under other conditions. That is, as in the case of (A), the abnormal signal is not output from the output terminal 35 of the programmable logic circuit PAL2 only when the programmable logic circuit PAL1 is normal and no abnormal signal is output.
In the case of other abnormal signal output conditions, the output terminal 35
Will output an abnormal signal of "1".

Further, by combining the logic circuits 21 and 31 and the flip-flops 22 and 32, it is possible to determine whether or not there is an abnormality in the output signal of the programmable logic circuit PAL1 at the preceding stage. Equivalent to.
A logical configuration other than those shown in FIGS. 3A and 3B is also possible. For example, in FIG. 3B, instead of the inverting output exclusive OR circuit 33 of the logic circuit 31, an AND circuit is used. Circuit and NOR circuit are used, and an output terminal OU is provided by an AND circuit.
When T2, OUT3 = "1" is abnormal, the signal "1" is output, and the NOR circuit outputs the output terminals OUT2, OUT3 =
It is also possible to adopt a configuration in which a signal of "1" is output in the case of an abnormality of "0".

[0023]

As described above, according to the present invention, among the plurality of logic gates 1-1 to 1-n and the first logic circuit 3 formed by connecting the logic gates by the wiring connection portion 2. Empty logic gates are connected by the wiring connection unit 2, the output of the first logic circuit 3 is input, and the second logic circuit 4 that inverts and outputs the output is formed, and the first and second logic circuits are formed. With the configuration in which the complementary output signals 3 and 4 are sent to the logic circuit of the next stage, it becomes possible to reliably transfer the abnormal signal even when a plurality of programmable logic circuits are cascaded. In addition, even when there is an abnormality in the logic gate or the output buffer forming the first logic circuit 3, the abnormality signal can be sent out in the logic circuit in the next stage. Therefore, the reliability of the programmable logic circuit can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of an example of the present invention.

FIG. 3 is an explanatory diagram of a next-stage logic circuit.

FIG. 4 is an explanatory diagram of a conventional example.

FIG. 5 is an explanatory diagram of a test of a conventional example.

[Explanation of symbols]

 1-1 to 1-n logic gate 2 wiring connection part 3 first logic circuit 4 second logic circuit 5 logic circuit 6 flip-flop IN1 to IN3 input terminal OUT1 to OUTn output terminal PAL1, PAL2 programmable logic circuit

Claims (1)

Claims: 1. A plurality of logic gates (1-1 to 1-n).
And a wiring connection section (2) in which a plurality of wirings are arranged in a matrix, and which connects the logic gates via the wiring connection section (2) according to program data. A first logic circuit (3) formed by connecting the logic gates by the wiring connection section (2) and an empty logic gate among the plurality of logic gates (1-1 to 1-n) A second logic circuit (4) which is connected by a wiring connection part (2) and which receives the output of the first logic circuit (3) and inverts and outputs it, and forms the first logic circuit (3). And the output of the second logic circuit (4) are sent to the logic circuit of the next stage.