WO1990013043A1

WO1990013043A1 - Method for automatic isolation of functional blocks within integrated circuits

Info

Publication number: WO1990013043A1
Application number: PCT/US1990/002007
Authority: WO
Inventors: Martin Jeffrey Bell; Muhammad Arif Samad
Original assignee: Vlsi Technology, Inc.
Priority date: 1989-04-18
Filing date: 1990-04-18
Publication date: 1990-11-01

Abstract

A system for automatically generating configurations for isolation circuits that can be designed into ASIC chips such that the isolation circuits are transparent during normal operation of the host chip but allow the embedded functional blocks to be readily isolated and accessed for testing via the host chip's pads.

Description

METHOD FOR AUTOMATIC ISOLATION OF FUNCTIONAL BLOCKS WITHIN INTEGRATED CIRCUITS

BACKGROUND

Field of the Invention:

The present invention generally relates to the testing of very large-scale integrated circuits and, more particularly, to the testing of such circuits of the type known as application specific integrated circuits (ASICs) .

State of the Art:

In the semiconductor industry, it is commonplace to manufacture integrated circuits or "chips" which each comprise hundreds of thousands, if not millions, of individual circuit components such as transistors. Although testing of such integrated circuits can be a formidable task, it is usually economical to devise routine testing programs when the integrated circuits have a standardized design and are produced in large volumes.

In recent years, technology has developed to economically provide integrated circuits of the type known as application-specific integrated circuits (ASICs). In essence, ASIC chips are custom-designed circuits of the LSI (large scale integration) or VLSI (very large scale integration) class. ASIC chips often include one or more functional blocks which, individually, may be classified as an LSI or VLSI circuit. For instance, the functional blocks within an ASIC chip may comprise one or more random access memories (RAMs) , read-only memories (ROMs) , state machines, or programmable logic array (PLAs) .

ASIC chips are normally characterized by relatively low production volumes. Thus, while ASIC chips and the functional blocks therein require testing to the same degree as standard-design integrated circuit chips, the low production volumes of ASIC chips usually imply that the testing techniques for standard-design chips cannot be used economically for

ASIC chips. Moreover, the testing of functional blocks within ASIC chips can be quite complex when the ports of a block cannot be directly accessed from the pads of an ASIC chip. Such difficulties occur, for example, when a functional block is a component of a larger functional block which, itself, is one of many component circuits within a host ASIC chip.

Various methods have been proposed for testing functional blocks that are embedded within ASIC chips. Examples of such methods are discussed in the article "Logic Verification and Production Testing of Non-structured Embedded VLSI Blocks," Breitenwisher, T.G., Proceedings of the 1987 IEEE Custom Integrated Circuits Conference, pp.62-65. In practice, the implementation of test procedures for ASIC chips is at least partly manual because individual attention must be paid to isolating the functional blocks and to providing conductors within the chips to allow the functional blocks to be tested via signals which are input to the chip pads.

According to conventional design practice, multiplexers often are embedded within ASIC chips for facilitating the testing of functional blocks via selected input/output pads on the chips. Typically, the proper placement and connections for such multiplexers requires the expenditure of substantial time by an experienced engineer. To test an isolated functional block within an ASIC chip, it is also known to apply test mode vectors to the chip pads. Conceptually, a chip pad and the logic value on it can be thought of as an ordered pair. Therefore, a test mode vector can be defined according to a set of such ordered pairs, where the width of the vector equals the number of ordered pairs that it contains. One method for generating test mode vectors is described in an article by M. Arif Samad and T. Butzerin entitled "A Methodology for the Test of Embedded Compiled Cells," Proceedings of the 1988 IEEE Custom Integrated Circuits Conference, pp.16.7.1- 16.7.3.

SUMMARY OF THE INVENTION In view of the preceding, it can be appreciated that there exists a need for improved systems for testing functional blocks embedded within integrated circuits such as ASIC chips. The present invention satisfies this need by providing a technique for automatically generating configurations for circuits, referred to herein as isolation circuits, that can be designed into ASIC chips such that the isolation circuits are transparent during normal operation of a host chip, but allow embedded functional blocks to be readily isolated and accessed for testing via the host chip's pads. BRIEF DESCRIPTION OF THE DRAWINGS The present invention can be further understood by reference to the following description and attached drawings which illustrate the preferred embodiment. It should be noted that like reference numbers indicate like elements in the various figures. In the drawings:

FIGURE 1 is a schematic diagram of a control circuit for use in a system according to the present invention;

FIGURE 2 is a simplified schematic diagram of one particular embodiment of the control circuit of FIGURE 1;

FIGURE 3 is a block diagram of a multiplexer circuit for providing a single test signal to a functional block in a host chip;

FIGURE 4 is a block diagram of a multiplexer circuit for multiplexing multiple test signals with a system signal in a host chip; FIGURE 5 is a block diagram of a multiplexer circuit for connecting a unidirectional input port of an isolated block to an input pad in a host chip;

FIGURE 6 is a block diagram of a multiplexer circuit for connecting an input port of an isolated functional block to a bidirectional pad of a host chip;

FIGURE 7 is a block diagram of a multiplexer circuit for connecting an output port of an isolated functional block to an output or bidirectional pad of a host chip; FIGURE 8 is a block diagram of a multiplexer circuit for connecting a bidirectional port of an isolated functional block to a bidirectional pad of a host chip; FIGURE 9A is a block diagram showing various functional blocks with a host chip;

FIGURE 9B is a block diagram showing the functional blocks of FIGURE 9A commonly connected to a bidirectional port of the host chip;

FIGURE 10A is a block diagram showing a unidirectional input pad connected to a functional block;

FIGURE 10B is a block diagram showing the functional block of FIGURE 10A connected to a bidirectional pad;

FIGURE 11A is a block diagram showing a unidirectional output pad connected to a functional block; and FIGURE 11B is a block diagram showing the functional block of FIGURE 11A connected to a bidirectional pad.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIGURE 1 shows a control circuit 10 which is to be embedded a host ASIC chip of the LSI or VLSI class for use in isolating and testing functional blocks in the chip. The functional blocks, as mentioned previously, may comprise one or more random access memories (RAMs) , read-only memories (ROMs) , state machines, or programmable logic array (PLAs) .

Generally speaking, control circuit 10 operates to provide binary logic values for use in controlling selected multiplexers which have been embedded in the host chip. As will be described below, the multiplexers are used to provide paths between the pads of the host chip and the ports of the functional blocks within the chip. In its illustrated embodiment, control circuit 10 is comprised of binary logic elements for controlling multiplexers that isolate as many as seven functional blocks within a host chip. In practice, any test circuitry embedded in an ASIC chip should be unnoticeable, or "transparent", during normal operation of the chip. In that regard, a path between a pad and a port of functional block within the host chip can be transparent only if the path passes through combinational logic. Also, a functional block can be satisfactorily isolated within a host chip only if all of its ports are connected to chip pads by transparent paths.

In the embodiment illustrated in FIGURE 1, control circuit 10 includes a decoder 13, an array of instance counters 17A, 17B and 17C, a counter enable device 19, and a counter reset device 21 (i.e., a NAND gate) . In the preferred embodiment, counter enable device 19 is a D-type flip-flop or "latch". Further in control circuit 10, a clock pad 23 is connected to the clock inputs of counters 17A-17C and latch 19. It should be understood that a conventional binary logic clock is connected to clock pad 23. The respective output lines from counters 17A, 17B and 17C are labelled Cnt[0], Cnt[l] and Cnt[2] in the drawing. Those "count" lines are connected for driving decoder 13 and are available for connection to multiplexers in the isolation circuits that will be described below. When decoder 13 has three binary count lines, as shown in FIGURE 1, the count information can be uniquely represented on as many as eight output lines (i.e., 2³ = 8) . In the drawing, those eight output lines are labelled N[0] through N[7]. As will be described below, the signals on lines N[l] through N[7] operate to select the functional block, or "instance", which is to be isolated within the host chip. Because of their function, lines N[l] through N[7] are sometimes referred to herein instance select lines. Preferably, all of the outputs on those lines are active low. It can be noted that the required size of decoder 13 reflects the number of functional blocks requiring isolation within the host chip.

Still further, control circuit 10 in FIGURE 1 includes three test mode vector receiving lines TM[1], TM[2] and TM[3]. Those three lines are all connected to an AND gate 25 whose output is latched by latch 19. In turn, the output of latch is connected to 19 enable the counter 17A. Generally, as many lines as needed can be used to receive test mode vectors.

Control circuit 10 in FIGURE 10 also includes reset circuitry operated from reset mode pads RM[1], RM[2] and RM[3] that are commonly connected to an AND gate 29. The output of AND gate 29 is applied, via an inverter 32, to the reset inputs of latches 19 and 27 and to AND gate 33. Also, the output of AND gate 29 is provided to NAND gate 21. It will be noted that instance select lines N[l] through N[7] also are connected to AND gate 21. In turn, the output of AND gate 21 is connected to the reset inputs of counters 17A through 17C.

The operation of the above-described elements of control circuit 10 of FIGURE 1 will now be described.

When the host chip is not in a test mode, control circuit 10 deactivates all the transparent paths within the chip, leaving it free to behave exactly as if the testing logic were not present. However, when the host chip is in the a test mode, control circuit 10 operates the embedded multiplexers to isolate selected ones of the functional blocks for testing. For example, in the illustrated embodiment, the output line N[l] from control circuit 10 is used to isolate a first functional block (i.e., instance), the output line N[2] is used to isolate a second functional block, and so forth for up to eight functional blocks.

Further in operation of control circuit 10 of FIGURE 1, counter 17A is enabled by a test mode vector applied to lines TM[1]-TM[3]. In turn, counter 17A enables counters 17B and 17C. The test mode vector is, in practice, chosen so that it does not appear during normal operation of the host chip. Whenever counter 17A is enabled, the instance select lines N£l]- N[7] are all disabled via outputs from latch 19 and logic circuitry such as that comprised of latch 27 NOR gate 31, AND gate 33, and parallel OR gates 28A-28G. The purpose of disabling lines N[0]-N[7] during such times is to prevent spurious transitions by the isolation multiplexers. It may be noted that OR gates 28A-28G inactivate the instance enable lines N[l] through N[7], respectively, until one cycle after counter 17A stops counting. It may also be noted that decoder 13 is connected such that it becomes inactive on the leading edge of a clock signal on the same cycle that the counter enable becomes active, and becomes active on the trailing edge of a clock signal on the cycle following the cycle that counter 17A-17C becomes inactive. Further in operation of control circuit 10 of FIGURE 1, counter 17A is reset by a reset mode vector applied to lines RM[1]-RM[3] which feed into NAND gate 21. Normally, the reset mode vector is chosen to be a signal that always occurs when the host chip is powered up or reset for normal operation. It should be noted that an input from AND gate 29 is necessary for NAND gate 21 to produce an active high reset signal and, therefore, counters 17A-17B do not reset until after the host chip is in its normal operating mode. Accordingly, counter 17A is reset whenever the host chip is powevered up and is enabled and clocked on the leading edge of the clock pulse. Also, a reset signal form AND gate 29 resets latches 19 and 27, and disables decoder 13 via AND gate 33 and OR gates 28A- 28G.

Operation of control circuit 10 of FIGURE 1 can now be summarized. That is, control circuit 10 provides logic value signals to isolate a functional block B_N (where "N" is the identifier of a selected functional block embedded within the host chip) when binary signals are applied to the appropriate pads of the host chip to execute the following sequence of steps: 1. Disable counter 17A.

2. Reset counter 17A.

3. Start the clock.

4. Enable counter 17A.

5. Wait N clock cycles. 6. Disable counter 17A.

7. Wait an additional cycle for the instance enable to become stable. FIGURE 2 shows a simplified control circuit for use when only a single functional block is to be isolated within a host chip. In this embodiment, the control cirucit comprises a two-input multiplexer 41 and a pair of AND gates 42 and 44. The input and output signals from the control circuit have the same functions as in the control circuit of FIGURE 1.

As mentioned above, the transparent paths between functional block ports and chip pads during the test mode are provided by multiplexers. The multiplexer circuits will now be described. As will become apparent in the following, certain of the multiplexers can have as many as N input ports. Those multi-input multiplexers will each receive " " control lines, where L — log₂(N) . The binary logic values on the control lines to any given multiplexer determine which of the inputs appear on the output line from the multiplexer.

FIGURE 3 shows a circuit for substituting a single test signal for a "system signal" when only a single functional block B₁ is to be isolated within a host chip. In FIGURE 3, a multiplexer 51 is interposed between a selected chip pad P_χ and circuitry C_χ that ordinarily provides system signals to the chip pad. More particularly, the output of multiplexer 51 is connected to chip pad P_χ, the first of the two inputs of multiplexer 51 is connected to circuitry Cx, the second of the two inputs is connected to the isolated block B.,, and the select input of the multiplexer is connected to receive the signal on instance select line N[l] . For purposes of discussion, the line carrying the output test signal from block B₁ is labelled TS[1] . In operation of the circuit of FIGURE 3, the select signal on line N[l] is ordinarily kept high (i.e., at logic level "1") but is driven low when functional block B₁ is to be isolated for testing. Thus, ordinarily, signals pass unimpeded from circuitry C_χ to pad P_χ. However, when the signal on line N[l] goes low (i.e., to logic level "0"), the signals from circuitry C_x are blocked from reaching chip pad P_χ and, instead, the signals on line TS[1] from functional block B₁ are directed to the chip pad. It should be noted that the delay introduced into the system signal path is only the time taken by the signal to propagate through multiplexer 51.

FIGURE 4 shows an example of a circuit that can be employed when multiple functional blocks B-, B_k, B_L and B_m are to be tested within a host chip, with each block providing a single test signal. In the illustrated example, the functional blocks are connected to a multi-input multiplexer 53 via respective test signal lines TS[j], TS[k], TS[1] and

TS[m]. Multiplexer 53 has two select lines Cnt[I] and Cnt[J]. Further in the circuit, the output of multiplexer 53 is connected to the second input of multiplexer 51. It should be noted that multiplexer 51 is connected as previously shown except that its select input is determined, via AND gate 52, by instance select lines N[j], N[k] , N[l] and N[m]. It should also be observed that the delay on the system path from circuitry C_x equals only the delay through multiplexer 51 and is independent of the number of test signal lines being multiplexed.

In operation of the circuit of FIGURE 4, the signals on all four of the select lines N[j], N[k] , N[l] and N[m] for multiplexer 51 are high except when one of the functional blocks B_j through B_m is to be tested. When one of the signals on select lines N[j], N[k], N[l] or N[m] goes low, the signals from multiplexer 53 are directed to pad P_χ in place of the system signals from circuitry C_χ. Then, depending upon the state of the count lines Cnt[I] and Cnt[J], the output of multiplexer 53 will correspond to the signal on one of the test signal lines TS[j], TS[k], TS[1] or TS[m]. Since the count lines Cnt[I] and Cnt[J] each have one of two binary states (i.e., either high or low) , any one of the four test signal lines can be uniquely selected.

In practice, the signals on the control lines Cnt[I] and Cnt[J] are synchronized with the signals on select lines N[j], N[k], N[l] and N[m] . In case of a circuit such as shown in FIGURE 4, synchronization can be accomplished with the following algorithm:

1. Convert the identifying numbers assigned to all functional blocks to binary digits. Let N be the number of binary digits in the identifying number for each functional block, and M be the number of functional blocks. 2. Put the binary numbers in tabular form such that the corresponding bits in each number are aligned in columns 0 through N-l.

3. Reject any columns that contain all binary ones or all zeros.

4. Reject any column that is a duplicate or binary inverse of a previously unrejected column. 5. Starting from bit zero (i.e., the least significant bit) , select ceiling of log₂ (M) unrejected columns. In applying the preceeding algorithm to the multiplexer circuit of FIGURE 4, the column number of the selected column determines the output line (e.g., Cnt[l]) to be connected to the select port of multiplexer 53. Then, for a given functional block, the multiplexer input "J" is assigned by examining the binary bits in the row corresponding to that block for the selected columns and converting those bits to the decimal number J. That is, the test signal for the selected functional block is connected to the Jth input of multiplexer 53. As an example of the preceding algorithm, assume that functional blocks having identifying Nos. 2, 69 and 158 are to be multiplexed with a system signal in a circuit similar to that of FIGURE 4. In that case, the algorithm can be expressed as shown in Table 1 below:

TABLE 1

Block MUX No. No. Funct. Block S[l] S[0] Input

7 6 5 4 3 2 1 0 — 2 0

N[2] . . . 0 0 0 0 0 0 1 0 — 0 0 — 10

N[69]. . . 0 1 0 0 0 1 0 1 — 1 1 — 13 N[158] . . 1 0 0 1 1 1 1 0 — 1 0 — 12

X X X X N S X S

X = reject column, S = accept column, and N = column not needed. As shown in Table 1, the numbers of the three functional blocks N[2], N[69] and N[158] are each represented by an eight bit sequence of binary numbers, with the members of the sequence arranged in columns 0 through 7. After rejecting certain of the columns according to the preceding algorithm, columns 0, 2 and 3 are left. With three functional blocks being isolated, ceiling of log₂(3) = 2 columns. Columns 0 and 2 can be chosen and, hence, select inputs 10 (i.e., SO) and II (i.e., SI) for multiplexer 53 will be connected to count lines Cnt[0] and Cnt[2]. Then, the test signal port for each of the functional blocks 2, 69 and 158 would be connected to multiplexer input ports 10,13 and 12, respectively. In practice, five basic types of connections can be used for providing transparent path between the port of a functional block and a pad of a host chip: 1) input pad to unidirectional input port; 2) input port to bidirectional pad; 3) output port to unidirectional output pad; 4) output port to bidirectional pad; and 5) bidirectional port to bidirectional pad. Circuitry to provide each of those connections will now be described.

FIGURE 5 shows a circuit to provide a transparent path between a unidirectional input port of a functional block B_N and an input pad P-. In the circuit shown, a 2-to-l multiplexer 56 is interposed between the unidirectional pad and the port. One input of multiplexer 56 is connected to pad P. via a level shifter 55 and the other input is connected to the circuit C_χ which ordinarily provides system signals to the input port of functional block B_N. The select input of multiplexer 56 is connected to line N[N] where "N" is the number which has been assigned to identify the functional block B_N.

In operation of the circuit of FIGURE 5, signals from circuitry C_χ ordinarily are directed to the input port of functional block B_N. However, when functional block B_N is to be isolated for testing, the binary state of line N[N] changes and, therefore, multiplexer 56 directs signals (i.e., test vector signals) from pad P- to the functional block. It may be observed that the signal on input pad P, is undisturbed electrically except for the additional capacitance of multiplexer 56.

FIGURE 6 shows a circuit to provide a transparent path between an input port of a functional block B_N and a bidirectional pad P_k of a host chip. It should be noted that bidirectional pad P_k includes buffers 55 and 57, and a pad driver 58 of conventional design. The connections in the circuit of FIGURE 6 are similar to the ones in FIGURE 5 except that circuitry is provided to disable pad driver 58 when pad P_k is needed for sending test signals to functional block B_N.

In the circuit of FIGURE 6, disablement of pad driver 58 is accomplished by a multiplexer 59 which multiplexes the enable line (OEB) of pad driver 58 -with VSS if the enable signal is active high or VDD if the enable signal is active low. The select signal for multiplexer 59 is connected to select line N[N] where, again, "N" is the number that identifies the functional block, B_N, which is to be isolated for testing.

The operation of the circuit of FIGURE 6 is the same as the operation of the circuit of FIGURE 5 except for the disablement circuitry for pad driver 58. Thus, in ordinary operation of the host chip, signals are directed from circuitry C_χ to the input port of functional block B_N. Also in the non-test mode of operation, signals are directed from circuitry C to pad P_k depending upon the state of pad driver 58 as determined by circuitry C_z. In the test mode, however, signals from circuitry C_z are blocked from passing through multiplexer 59 by the high input on select line N[N] . In turn, the VDD signal disables pad driver 58 and restrict bidirectional pad P_k to operating as a unidirectional input pad. When pad P_k operates as an input pad, the test signal from pad P_k to functional block B_N is controlled by multiplexer 56 as described in connection with FIGURE 5. FIGURE 7 shows a multiplexing circuit for connecting on output port of functional block B_N to bidirectional pad P_k. In the circuit, a multiplexer 61 is provided for multiplexing the system signal to pad driver 58 from circuitry C_H and the output signal from functional block B_N. Also, multiplexer 59 is provided for multiplexing the enable line for pad driver 58 in the same manner as shown in FIGURE 6. It should be noted that select line N[N] is connected to the select inputs of both multiplexers 59 and 61.

In the test mode of operation of the circuit of FIGURE 7, a low logic signal on line N[N] causes multiplexer 59 to block signals from circuitry C_z from reaching the enable input of pad driver 58. Instead, the pad driver is enabled by the VSS signal, thereby causing bidirectional pad P_k to operate as unidirectional output pad. (When pad P_k operates as an output pad, system signals cannot be directed from the pad to circuitry C_v.) Also during the test mode, multiplexer 61 prevents signals from circuitry C_w from reaching pad P_k; instead, because of the low logic signal on line N[N] , the output signals from functionl block B_N are directed to pad P_k.

Further with regard to FIGURE 7, it should be noted that multiplexer 59 would be unnecessary if pad P_k were an output pad rather than a bidirectional pad. In that case, pad driver 58 would be absent and the Z output of multiplexer 61 would be connected directly to pad P_k.

The circuit of FIGURE 7 can be generalized to the case where multiple functional blocks are present, each of which has an ouput port for connection to a single bidirectional pad of the host chip. In that case, a circuit such as the one shown in FIGURE 4 is used to multiplex the output signals from the functional blocks. Also in that case, the instance select lines would be- connected to an AND gate which, in turn, would be connected to the select inputs of multiplexers 59 and 61. Thus, pad driver 58 would be enabled concurrently with a test signal output from any one of the functional blocks that are under test

FIGURE 8 shows circuitry for providing a transparent path between a bidirectional port of a functional block B_N and a bidirectional pad P_k. It should be noted that block B_N includes a control port that indicates whether its bidirectional port is in the input or output mode. It should also be noted that two paths must be created to pad P_k from the bidirectional port of block B_N (i.e., one path for input signals to the block and one for output signals) . In the example shown, multiplexer 61 is provided for multiplexing the system signal from circuitry C_w with the output signal from the bidirectional port of block B_N. Also, multiplexer 59 is interposed between circuitry C_z and the enable (OEB) input of pad driver 58. More particularly, multiplexer 59 is connected for multiplexing the enable signal to pad driver 58 with the signal from the control port of functional block B_N. It should be noted that instance select line N[N] is connected to the select inputs of both multiplexers 59 and 61.

As also shown in FIGURE 8, a bidirectional control unit 73 is interposed in the input path from pad P_k to block B_N. In the illustrated embodiment, control unit 73 comprises a multiplexer 76, two AND gates 77 and 79, and an^"inverter 81. The two AND gates 77 and 79 are connected in series via inverter 81; the second input to AND gate 79 is from the Z output of multiplexer 76. The output of AND gate 79 is connected to a three-state buffer 83. The 10 input to multiplexer 76 is from the control port of block B_N. The select inputs of multiplexer 76 receive count lines Cnt[I] and Cnt[J], In operation of the circuit of FIGURE 8, control unit 73 disables the path between the input level shifter 55 and the bidirectional port of functional block B_N if the bidirectional port is in the output mode.

Also, the circuit of FIGURE 8 can be used when multiple functional blocks each have a bidirectional port that drives the same signal and when all of those ports are connected to a single bidirectional pad P_k for testing. In that case, the input and select ports of multiplexer 76 are assigned according to the algorithm that was described in connection with FIGURE 4. Further in that case, AND gate 77 would receive instance select lines corresponding to each of the functional blocks that share the same bidirectional signal and that are being connected to the same pad. Still further in the case of multiple functional blocks, the inputs of multiplexer 76 are connected to the control ports of those other functional blocks.

Also for employing the circuitry of FIGURE 8 for the case where bidirectional ports from multiple functional blocks are to be connected to a single bidirectional pad, a control unit (e.g., unit 73) is added for each group of functional block ports that share the same bidirectional signal and that are mapped to the same bidirectional pad of the host chip. And, as mentioned above, the inputs to each multiplexer in each control circuit would include lines from the control ports of all the functional block bidirectional ports that share the same signal and that are to be connected to the bidirectional pad under consideration.

It can now be understood that the above- discussed circuits for connection functional block ports to bidirectional pads can be combined. Accordingly, each bidirectional pad of a host chip can have some combination of input, output and bidirectional ports connected to it. An example of such a combination will be provided in conjunction with FIGURES 9A and 9B. FIGURE 9A should be understood as showing functional blocks B₁ through B₆ within a host chip having a bidirectional pad P_k. FIGURE 9B shows a multiplexer circuit which connects functional blocks B₁-B₆ to pad P_k for sequential testing. It will be noted that the circuit of FIGURE 9B is a combination of the various isolation circuits discussed above, including control units 73.

To determine which pad of a host chip should be used to provide an isolation path for testing any one functional block, the following priority method can be employed:

1. For a bidirectional connector on the functional block, choose a pad that has another instance connector connected to the same bidirectional signal mapped to it. (That is, try to map all connectors connected to the same bidirectional signal to the same pad.) 2. Choose a pad of the same type as an instance connector which already has a signal path added to it.

3. Choose a pad of the same type as the instance connector which does not already have a signal path added to it.

4. Choose a pad of any type which already has a signal path added it. (Such a pad will be changed to a bidirectional pad.)

5. Choose a pad of any type and, then, change the pad to a bidirectional pad if necessary. Thus, in practice, it is preferred to use chip pads that already have isolation multiplexers added to them. The reason for this is that, once a pad has been disturbed with a multiplexer unit, no additional path delay incurred by adding more test circuit signals to the pad if the above-described isolation circuits are used. In accordance with the preceding priority method, situations may arise where a host chip one or more unidirectional input or output pads which must be replaced with bidirectional pads. In practice, the automatic test circuit generation system includes a file with a list of unidirectional pad macro names and a corresponding list of their bidirectional equivalents to provide bidirectional equivalents for the unidirectional pad. Convenient steps for replacing a unidirectional pad with a bidirectional pad are as follows:

1. Disconnect all signal lines from the unidirectional pad which is to be replaced. The disconnected lines can include ones for the pad signal, an input signal or an output signal, and an optional output enable signal.

2. Delete the pad.

3. Add an equivalent bidirectional pad. 4. Reconnect all disconnected signals.

5. For input pads, add a three-state pad driver whose output enable is active low. Connect the output signal to VSS and connect the output enable to VDD to permanently disable it. (The replacement pad, unless modified further, will behave exactly like the original input pad.)

6. For output pads, replace the pad driver with a three-state pad driver with an output enable which is active low. Also, connect the output enable port of the pad driver to V_ss to permanently enable it. The method for repacing an input pad P. with a bidirectional pad P_k is illustrated by FIGURES 10A and 10B. FIGURE 10A shows the connections between pad P_j and block B_N before the pad is replaced with a bidirectional pad. FIGURE 10B shows the configuration of the circuit after input pad P_j has been replaced by bidirectional pad P_k.

Similarly, FIGURES 11A and 11B illustrate the method for replacing an output pad P₀ with a bidirectional pad P_k. FIGURE 11A shows the connections between pad P₀ and block B_N before the pad is replaced with a bidirectional pad. FIGURE 11B shows the configuration of the circuit after output pad P₀ has been replaced by a bidirectional pad P_k. The foregoing has described the principles, preferred embodiments and modes of operation of the present invention. However, the present invention should not be construed as being limited to the particular embodiments disclosed, and the embodiments described herein are to be regarded as illustrative rather than restrictive. Variations and changes may be made in the illustrated embodiments without departing from the spirit of the present invention as defined by the following claims.

Claims

CLAIMS :

1. An automatic system for generating isolation circuits for sequentially testing a plurality of functional blocks within an integrated circuit chip, which isolation circuits that are substantially transparent during normal operation of the chip, comprising the steps of: a) assigning identifying numbers to the functional blocks selected for testing; b) selecting the pads of the chip to which each of the selected functional block ports is to be connected for testing; c) for each selected pad, embedding a 2:1 multiplexer in the chip for multiplexing system signals in the chip with a signal associated with testing the functional blocks connected to the pad; d) then, for each selected pad and each set of two or more functional blocks that are to be connected to the pad for testing, embedding a multi- input multiplexer in the chip with the output of the multi-input multiplexer connected as an input of the 2:1 multiplexer, and connecting the inputs of the multi-input multiplexer connected to one port of each of the functional blocks of the set; e) controlling the select port of the first multiplexer with a signal which uniquely identifies the functional block selected for testing during the test sequence; and f) simultaneously controlling the select port of the multi-input multiplexer with a signal which uniquely identifies the functional block selected for testing.