JPH0537354A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0537354A JPH0537354A JP3190485A JP19048591A JPH0537354A JP H0537354 A JPH0537354 A JP H0537354A JP 3190485 A JP3190485 A JP 3190485A JP 19048591 A JP19048591 A JP 19048591A JP H0537354 A JPH0537354 A JP H0537354A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- current
- logic
- control signal
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特にIIL型の論理回路を含んだ半導体集積回路に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit including an IIL type logic circuit.
【0002】[0002]
【従来の技術】従来、この種の半導体集積回路は、一例
として図3に示すように、外部回路からの入力信号DI
a〜DInをIIL(Integrated Inje
ction Logic)型の論理レベルに変換し、ま
た内部からのIIL型の論理レベルの信号を外部回路の
論理レベルに適合させて出力するインタフェース回路1
と、複数の単位ゲート21a〜21nを備えインタフェ
ース回路1からの入力信号に対し所定の論理処理を行い
インタフェース回路1へ出力するIIL型の論理回路2
と、ベースにバイアス電圧Vbを受けるトランジスタQ
3と抵抗R1とを備えこの論理回路2の各単位回路21
a〜21nへ定電流を供給する定電流源回路3cとを有
する構成となっていた。2. Description of the Related Art Conventionally, a semiconductor integrated circuit of this type has an input signal DI from an external circuit as shown in FIG.
a to DIn are IIL (Integrated Inje)
interface circuit 1 for converting to a logic level of an action logic type and for outputting an IIL type logic level signal from the inside in conformity with a logic level of an external circuit.
And an IIL type logic circuit 2 including a plurality of unit gates 21a to 21n and performing a predetermined logic process on an input signal from the interface circuit 1 and outputting it to the interface circuit 1.
And a transistor Q that receives a bias voltage Vb at its base
3, each unit circuit 21 of this logic circuit 2 is provided with 3 and a resistor R1.
It has a configuration including a constant current source circuit 3c for supplying a constant current to a to 21n.
【0003】定電流源回路3cのトランジスタQ3のベ
ースには常にバイアス電圧Vbが印加されているので、
論理回路2には常時一定の電流が供給されている。この
電流は、各単位ゲート21a〜21nの特性や要求され
る動作速度をもとに決定され、通常、単位ゲート当り数
10μA程となるように設定されている。Since the bias voltage Vb is always applied to the base of the transistor Q3 of the constant current source circuit 3c,
A constant current is always supplied to the logic circuit 2. This current is determined based on the characteristics of each of the unit gates 21a to 21n and the required operation speed, and is normally set to about several 10 μA per unit gate.
【0004】[0004]
【発明が解決しようとする課題】この従来の半導体集積
回路では、常に論理回路2に対して一定の電流を供給し
ているので、論理回路2が論理処理動作をしない場合に
も、この電流分の電力を消費するため、電池を電源とし
て使用するような低消費電力を要求される用途において
は使用する事が困難であるという問題点があった。In this conventional semiconductor integrated circuit, a constant current is always supplied to the logic circuit 2. Therefore, even if the logic circuit 2 does not perform the logic processing operation, this current component is not supplied. However, there is a problem in that it is difficult to use in applications requiring low power consumption such as using a battery as a power source.
【0005】本発明の目的は、消費電力を低減し、電池
を電源として使用するような場合にも使用することがで
きる半導体集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit which consumes less power and can be used even when a battery is used as a power source.
【0006】[0006]
【課題を解決するための手段】本発明の半導体集積回路
は、電流入力端に電流が供給されたとき活性化し入力信
号に対し所定の論理処理を行い出力するIIL型の論理
回路と、制御信号によりオン状態,オフ状態となるトラ
ンジスタを備えこのトランジスタがオン状態のとき前記
論理回路へ電流を供給する電流源回路と、前記制御信号
を前記電流源回路へ供給する制御信号供給手段とを有し
ている。SUMMARY OF THE INVENTION A semiconductor integrated circuit according to the present invention includes an IIL type logic circuit which is activated when a current is supplied to a current input terminal and performs a predetermined logic process on an input signal and outputs the same. A current source circuit that supplies a current to the logic circuit when the transistor is on, and a control signal supply unit that supplies the control signal to the current source circuit. ing.
【0007】[0007]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【0008】図1は本発明の第1の実施例を示す回路図
である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【0009】この実施例は、外部回路からの入力信号D
Ia〜DInをIIL型の論理レベルに変換し、また内
部からのIIL型の論理レベルの信号を外部回路の論理
レベルに適合させて出力するインタフェース回路1と、
複数の単位ゲート21a〜21nを備え電流入力端II
Nに電流が供給されたとき活性化しインタフェース回路
1からの入力信号に対し所定の論理処理を行いインタフ
ェース回路1へ出力するIIL型の論理回路2と、ベー
スに制御信号CNTを入力してオン,オフするトランジ
スタQ3及び抵抗R1とを備え、トランジスタQ3がオ
ン状態のとき論理回路2へ電流を供給する低電流源回路
3と、制御信号CNTを電流源回路3へ供給する制御信
号供給手段の端子Tcとを有する構成となっている。In this embodiment, an input signal D from an external circuit is used.
An interface circuit 1 for converting Ia to DIn to an IIL type logic level, and for outputting an IIL type logic level signal from the inside in conformity with the logic level of an external circuit,
A current input terminal II including a plurality of unit gates 21a to 21n
An IIL type logic circuit 2 which is activated when a current is supplied to N and performs a predetermined logic process on an input signal from the interface circuit 1 and outputs it to the interface circuit 1, and a control signal CNT is input to the base to turn it on, A low current source circuit 3 that includes a transistor Q3 that turns off and a resistor R1 and that supplies a current to the logic circuit 2 when the transistor Q3 is in an on state, and a terminal of a control signal supply unit that supplies a control signal CNT to the current source circuit 3. It has a structure including Tc.
【0010】制御信号CNTは、論理回路2が論理処理
を行わない場合には電源電圧Vccレベルとなり、トラ
ンジスタQ3をオフ状態とする。従ってこの状態では論
理回路2に電流が流れないので、従来例のように常時一
定の電流が流れている場合に比べ、消費電流を低減する
ことができる。Control signal CNT attains power supply voltage Vcc level when logic circuit 2 does not perform logic processing, and turns off transistor Q3. Therefore, in this state, since no current flows through the logic circuit 2, it is possible to reduce current consumption as compared with the case where a constant current constantly flows as in the conventional example.
【0011】図2は本発明の第2の実施例を示す回路図
である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
【0012】この実施例は、2つの論理回路2a,db
が設けられ、これら論理回路2a,2bに対応してそれ
ぞれ定電流源回路3a,3bが設けられ、これら定電流
源回路3a,3bのトランジスタQ3のオン,オフを制
御信号CNTa,CNTbにより制御するようにしたも
のである。In this embodiment, two logic circuits 2a and db are provided.
Are provided, and constant current source circuits 3a and 3b are provided corresponding to these logic circuits 2a and 2b, respectively, and the ON / OFF of the transistor Q3 of these constant current source circuits 3a and 3b is controlled by control signals CNTa and CNTb. It was done like this.
【0013】制御信号CNTa,CNTbは、インタフ
ェース回路1aにより、入力信号DIの内容に応じてそ
のレベルが決定されるようになっている。すなわち、入
力信号DIの内容が論理回路2a,2bにより処理する
必要がないものであれば制御信号CNTa,CNTbは
電源電圧Vccレベルとなって定電流源回路3a,3b
のトランジスタQ3をオフにし、論理回路2a(又は2
b)による論理処理が必要であれば制御信号CNTa
(又はCNTb)を低レベルにして定電流源回路3a
(又は3b)のトランジスタQ3をオンにし、論理回路
2a(又は2b)に電流を供給する。The levels of the control signals CNTa and CNTb are determined by the interface circuit 1a according to the contents of the input signal DI. That is, if the content of the input signal DI does not need to be processed by the logic circuits 2a and 2b, the control signals CNTa and CNTb become the power supply voltage Vcc level and the constant current source circuits 3a and 3b.
Of the logic circuit 2a (or 2
If logical processing according to b) is required, the control signal CNTa
(Or CNTb) to a low level to make the constant current source circuit 3a
The transistor Q3 (or 3b) is turned on to supply a current to the logic circuit 2a (or 2b).
【0014】このようにして、入力信号DIの内容に応
じて、必要な論理回路のみを活性化し、他は非活性状態
として電流を流さないようにしているので、消費電流を
必要最小限に抑えることができる。In this way, only the necessary logic circuits are activated according to the contents of the input signal DI, and the other logic circuits are inactivated so that no current flows. Therefore, the current consumption is suppressed to the minimum necessary. be able to.
【0015】[0015]
【発明の効果】以上説明したように本発明は、定電流源
回路から論理回路へ供給する電流を、制御信号によって
制御する制御信号供給手段を設けた構成とすることによ
り、論理回路で論理処理を行うときのみ電流を供給し論
理処理を行わないときは電流の供給を停止するので、無
駄な電流の消費がなくなり消費電流の低減をはかること
ができ、従って電池を電源として使用する場合でもこの
半導体集積回路を使用することができる効果がある。As described above, according to the present invention, by providing the control signal supply means for controlling the current supplied from the constant current source circuit to the logic circuit by the control signal, the logic processing is performed in the logic circuit. Current is supplied only when performing a logic operation, and current supply is stopped when no logic processing is performed, so that useless current consumption is eliminated and consumption current can be reduced. Therefore, even when a battery is used as a power source, this There is an effect that a semiconductor integrated circuit can be used.
【図1】本発明の第1の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【図2】本発明の第2の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
【図3】従来の半導体集積回路の一例を示す回路図であ
る。FIG. 3 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.
1,1a インタフェース回路 2,2a,2b 論理回路 3,3a〜3c 定電流源回路 21a〜21n 単位ゲート Q1〜Q3 トランジスタ R1 抵抗 1,1a interface circuit 2, 2a, 2b logic circuit 3, 3a to 3c constant current source circuit 21a-21n unit gate Q1 to Q3 transistors R1 resistance
Claims (2)
化し入力信号に対し所定の論理処理を行い出力するII
L型の論理回路と、制御信号によりオン状態,オフ状態
となるトランジスタを備えこのトラジスタがオン状態の
とき前記論理回路へ電流を供給する電流源回路と、前記
制御信号を前記電流源回路へ供給する制御信号供給手段
とを有することを特徴とする半導体集積回路。1. A device which is activated when a current is supplied to a current input terminal and performs a predetermined logical processing on an input signal and outputs the signal II
A current source circuit that includes an L-type logic circuit and a transistor that is turned on and off by a control signal and supplies a current to the logic circuit when the transistor is on, and the control signal is supplied to the current source circuit. And a control signal supply means for controlling the semiconductor integrated circuit.
成り、電流源回路が前記第1及び第2の論理回路へそれ
ぞれ対応して電流を供給,制御する第1及び第2の電流
源回路から成り、制御信号供給手段を、入力信号の内容
に応じて前記第1及び第2の電流源回路のトランジスタ
のオン,オフを制御する第1及び第2の制御信号を発生
する回路とした請求項1記載の半導体集積回路。2. The first and second currents, wherein the logic circuit comprises first and second logic circuits, and the current source circuit supplies and controls currents corresponding to the first and second logic circuits, respectively. And a control signal supply means for generating the first and second control signals for controlling ON / OFF of the transistors of the first and second current source circuits according to the contents of the input signal. The semiconductor integrated circuit according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3190485A JPH0537354A (en) | 1991-07-31 | 1991-07-31 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3190485A JPH0537354A (en) | 1991-07-31 | 1991-07-31 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0537354A true JPH0537354A (en) | 1993-02-12 |
Family
ID=16258884
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3190485A Pending JPH0537354A (en) | 1991-07-31 | 1991-07-31 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0537354A (en) |
-
1991
- 1991-07-31 JP JP3190485A patent/JPH0537354A/en active Pending
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20000905 |