JPH0537339A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a noise which follows a simultaneous operation of plural pieces of output circuits, and to relax a restriction of the number of simultaneous operations of the output circuits. CONSTITUTION:In a first and a second output circuits formed on the same semiconductor substrates, an input threshold voltage of an inverter I3 of a first output circuit is set to about 1.5V, and an input threshold voltage of an inverter I5 of a second output circuit is set to about 3V. When a first and a second output circuits are operated simultaneously, a timing of the simultaneous operation is subjected to fine adjustment due to a difference of the input threshold voltages, and it can be prevented that a variation of a power source current or a ground current is concentrated timewise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device for simultaneously operating a plurality of output circuits, and more particularly to a semiconductor integrated circuit device provided with noise countermeasures.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, the main source of noise is an output circuit section that interfaces with the outside. In particular, noise generated by the simultaneous operation of a plurality of output circuits is generated by another output circuit or an input circuit. Cause malfunction. Therefore, a semiconductor integrated circuit device in which noise in the output circuit section is reduced has been proposed.

FIG. 3 shows a conventional Controlled Slew Rate Output Buffer, Pro
ceedings of the IEEE 1988 Custom Integrated Circui
is a circuit diagram showing (tsConference). The input end of the inverter I ₂ is connected to the input terminal 1. The inverter I ₁ is composed of a P-type MOS transistor P ₁ and an N-type MOS transistor N ₁ which are connected in series between the power source V _DD and the ground GND, and the input end of the inverter I ₁ is the inverter I _2.
Is connected to the output terminal and the output terminal is connected to the output terminal 2. One input end of the NAND gate is the input terminal 1
, And the other input end is connected to the output terminal 2. The P-type MOS transistor P ₂ is connected between the power supply V _DD and the output terminal 2 and receives the output signal of the NAND gate as a gate input. One input terminal of the NOR gate is the input terminal 1
, And the other input end is connected to the output terminal 2. The N-type MOS transistor N ₂ is connected between the ground GND and the output terminal 2 and receives the output signal of the NOR gate as a gate input.

Next, the operation of the above control slew rate output buffer will be described. First, when a high level is applied to the input terminal 1, the output signal of the inverter I ₂ becomes low level, and the output signal of the inverter I ₁ , that is, the output signal at the output terminal 2 becomes high level. In this case, the output signal of the NOR gate is Low
Since it is fixed to the level, N-type MOS transistor N ₂
Turns off. The NAND gate has an output terminal 2
This state is determined by the output potential of
Since the output signal of the gate becomes low level, the P-type MO
The S transistor P ₂ is turned on. By thus providing a time difference between the operations of the P-type MOS transistors P ₁ and P ₂ , it is possible to reduce the noise of the power supply potential.

Next, when the Low level is applied to the input terminal 1, the output signal of the inverter I ₂ becomes High level, and the output signal of the inverter I ₁ , that is, the output signal at the output terminal 2 becomes Low level. In this case, NAN
Since the output signal of the D gate is fixed at the high level, the P-type MOS transistor P ₂ is turned off. The state of the NOR gate is determined by the output potential of the output terminal 2, and the output signal of this NOR gate is HIg.
Since it becomes the h level, the N-type MOS transistor N ₂ is turned on. By thus providing a time difference between the operations of the N-type MOS transistors N ₁ and N ₂ , it is possible to reduce the noise of the ground potential.

The parasitic inductance component is L,
The time change of the current per output circuit is dI / dt,
When the number of simultaneous operations of the output circuit is n, the noise ΔV of the power supply potential or the ground potential is expressed by the following mathematical formula 1.

[0007]

[Equation 1] △ V∝n ・ L ・ dI / dt

[0008]

However, in the conventional semiconductor integrated circuit device, speeding up of the circuit means reduction of the dt component, and improvement of transistor performance due to miniaturization etc. means increase of the dI component. Therefore, the dI / dt component tends to increase more in a single output circuit. On the other hand, the parasitic inductance component L is being reduced due to the improvement of the layout of the power supply wiring and the improvement of the package, but this reduction is insufficient. Therefore, as is clear from the above formula 1, there is a problem that the number n of simultaneous operations of the output circuit is limited.

Therefore, noise of the power supply potential or the ground potential can be reduced by adding a delay circuit to the semiconductor integrated circuit device and finely adjusting the timing of simultaneous operation of the output circuits. In this case, the delay circuit is used. This is not preferable because the element area is increased. Further, it is possible to stabilize the potential by increasing the number of power supply terminals and ground terminals, but this is not preferable because the number of pins of the semiconductor integrated circuit device increases.

Recently, since the system composed of semiconductor integrated circuit devices has become large in scale of 8, 16, 32 and 64 bits, it is strongly demanded to relax the limitation on the number of simultaneous operation of output circuits. However, it is difficult to deal with the above-mentioned control slew rate output buffer.

The present invention has been made in view of the above problems, and it is possible to reduce noise associated with the simultaneous operation of a plurality of output circuits, and relax the limitation on the number of simultaneous operation of the output circuits. An object of the present invention is to provide a semiconductor integrated circuit device that can be used.

[0012]

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which a plurality of output circuits formed on the same semiconductor substrate are simultaneously operated. The input threshold voltages are different from each other.

[0013]

In the present invention, by making the input threshold voltages of the plurality of output circuits different from each other and finely adjusting the timing of the simultaneous operation, the power supply current or the simultaneous operation of the plurality of output circuits can be improved. A time difference can be provided for the change in the ground current. Therefore, it is possible to reduce the noise of the power supply potential or the ground potential due to the simultaneous operation of the plurality of output circuits.

According to the present invention, since the input threshold voltage of the output circuit is changed, it is possible to relax the limitation on the number of simultaneous operations of the output circuit without adding a delay circuit or the like to the semiconductor integrated circuit device.

[0015]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. This semiconductor integrated circuit device has first and second output circuits on the same semiconductor substrate, the first output circuit is composed of inverters I ₃ and I ₄ , and the second output circuit is the inverter I 3. ₅ and I ₆ .

First, the first output circuit will be described.
The inverter I ₃ is a P-type MOS transistor P ₃ and an N-type MOS transistor connected in series between the power source V _DD and the ground GND.
Is composed of transistors N _3, the common gate of the MOS transistor P _3, N ₃ is the input terminal (input potential V ₁₎
It is connected to the. Inverter I ₄ has power supply V _DD and ground G
It is composed of a P-type MOS transistor P ₄ and an N-type MOS transistor N ₄ connected in series with ND, and the common gate of the MOS transistors P ₄ and N ₄ is MO.
It is connected to the common drain of the S transistors P ₃ and N ₃ . The common drain of the MOS transistors P ₄ and N ₄ is connected to the output terminal (output potential V ₂ ).

Next, the second output circuit will be described.
The inverter I ₅ is a P-type MOS transistor P ₅ and an N-type MOS transistor connected in series between the power supply V _DD and the ground GND.
It is composed of a transistor N ₅ , and the common gate of the MOS transistors P ₅ and N ₅ is an input terminal (input potential V ₃ ).
It is connected to the. Inverter I ₆ has power supply V _DD and ground G
It is composed of a P-type MOS transistor P ₆ and an N-type MOS transistor N ₆ connected in series with ND, and the common gate of the MOS transistors P ₆ and N ₆ is MO.
It is connected to the common drain of the S transistors P ₅ and N ₅ . The common drain of the MOS transistors P ₆ and N ₆ is connected to the output terminal (output potential V ₄ ).

The gate width of the N-type MOS transistor N ₃ is about twice the gate width of the P-type MOS transistor P ₃ , and the input threshold voltage of the inverter I ₃ is about 1.5V. On the other hand, the gate width of the P-type MOS transistor P ₅ is about twice the gate width of the N-type MOS transistor N ₅ , and the input threshold voltage of the inverter I ₅ is about 3V. Further, the inverters I ₄ and I ₆ have the same input threshold voltage.

FIG. 2 is a waveform diagram showing the relationship between the input potentials and output potentials of the first and second output circuits in the semiconductor integrated circuit device according to this embodiment and time. In FIG. 2, Va indicates the potential at the interconnection point a of the inverters I ₃ and I ₄ , and Vb indicates the potential at the interconnection point b of the inverters I ₅ and I ₆ .

As shown in FIG. 2, when the input potentials V ₁ and V ₂ are simultaneously applied to the first and second output circuits, respectively, the input threshold voltages of the inverters I ₃ and I ₅ are different from each other. , Output potential V ₄ is time Δt with respect to output potential V ₂ .
Change only with a delay. As a result, there is a time difference in the change of the power supply current, so that the noise of the power supply potential due to the simultaneous operation of the two output circuits can be reduced.

Further, for example, TTL is formed on the same semiconductor substrate.
When the input (threshold voltage; about 1.3V) is provided,
In FIG. 1, noise of the ground potential becomes a problem when the input potential changes from the high level to the low level. In this case, the second output circuit having a high input threshold voltage is used on the side where the TTL input signal reaches early, and the first output circuit having a low input threshold voltage is used on the side where the TTL input signal reaches late. By using it, the time Δt is increased. Although this time Δt depends on the fall time of the input potential, it can be secured for about 1 n seconds. As a result, there is a time difference in the change of the ground current, so that the noise of the ground potential due to the simultaneous operation of the two output circuits can be reduced.

According to the present embodiment, the input threshold voltages of the two output circuits are mutually changed to finely adjust the timing of the simultaneous operation, thereby reducing the noise accompanying the simultaneous operation of the two output circuits. You can As a result, the limitation on the number of simultaneous operations of the output circuit can be relaxed.

The present invention can also be applied to the control slew rate output buffer shown in FIG. FIG. 3 is a circuit diagram showing an extracted NOR gate in FIG. That is, the P-type MOS transistors P ₇ and P ₈ are connected in series between the power source V _DD and the output end of the NOR gate. The N-type MOS transistors N ₇ and N ₈ are connected in parallel between the output end of the NOR gate and the ground GND. The MOS transistors P ₈ and N ₈ receive the potential of the input terminal 1, and the MOS transistors P ₇ and N ₇ output the output terminal 2.
Input the potential of.

In this case, by changing the input threshold voltage of the N-type MOS transistor N ₇ which gate-inputs the potential of the output terminal 2 for each output circuit operating simultaneously, it is possible to provide a time difference in the change of the ground current. , The noise of the ground potential due to the simultaneous operation of the output circuits can be reduced.
The time difference of changes in the ground current changes depending on the size of the output load, but normally it can be secured for several n seconds, and the changes in the ground current are dispersed within this time difference.

[0026]

As described above, according to the present invention, the input threshold voltages of a plurality of output circuits operated simultaneously on the same semiconductor substrate are made different from each other, and the timing of the simultaneous operation is finely adjusted. Therefore, it is possible to reduce the noise due to the simultaneous operation of the plurality of output circuits. As a result, the limitation on the number of simultaneous operations of the output circuit can be relaxed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the relationship between the input potential of the output circuit and the output potential and time in the semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a NOR gate to which the present invention is applied.

FIG. 4 is a circuit diagram showing a conventional control slew rate output buffer.

[Explanation of symbols]

I _{1 to} I ₆ ; Inverters P _{1 to} P ₈ ; P-type MOS transistors N _{1 to} N ₈ ; N-type MOS transistors

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H03K 19/0948

Claims (1)

1. A semiconductor integrated circuit device for simultaneously operating a plurality of output circuits formed on the same semiconductor substrate, wherein the plurality of output circuits have different input threshold voltages from each other. And a semiconductor integrated circuit device.