JPH0536850A - Thin film circuit - Google Patents
Thin film circuitInfo
- Publication number
- JPH0536850A JPH0536850A JP21295991A JP21295991A JPH0536850A JP H0536850 A JPH0536850 A JP H0536850A JP 21295991 A JP21295991 A JP 21295991A JP 21295991 A JP21295991 A JP 21295991A JP H0536850 A JPH0536850 A JP H0536850A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- thin film
- insulating
- metal thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、大面積半導体装置等に
広く使用される薄膜回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film circuit widely used for large area semiconductor devices and the like.
【０００２】[0002]
【従来の技術】大面積半導体装置等には、絶縁性基板の
上に、金属薄膜や薄い絶縁膜を積層して形成した薄膜回
路が使用される。このような薄膜回路においては、金属
薄膜を他の部分から絶縁するのに、高い絶縁性をもって
他の層から隔てなければならない部分（以下「高絶縁
部」という）と、それほど高い絶縁性をもって隔てなく
ともよい部分（以下「低絶縁部」という）とがある。そ
して、高絶縁部は、低絶縁部と同様に施す共通絶縁膜に
追加して追加絶縁膜を積層した構造とすることが行われ
ている。2. Description of the Related Art A thin film circuit formed by laminating a metal thin film or a thin insulating film on an insulating substrate is used for a large area semiconductor device or the like. In such a thin film circuit, in order to insulate the metal thin film from other parts, it is necessary to separate the part that has to be separated from other layers with high insulation property (hereinafter referred to as “high insulation part”) with such high insulation property. There is a part that may be omitted (hereinafter referred to as "low insulation part"). Then, the high insulating portion is formed to have a structure in which an additional insulating film is stacked in addition to the common insulating film formed in the same manner as the low insulating portion.
【０００３】図３は、従来の薄膜回路の高絶縁部と低絶
縁部の境界付近の断面を示す図である。図３において、
１は絶縁性基板、２は共通絶縁膜としての第１絶縁膜、
３は第２金属薄膜、４は第１金属薄膜、５は追加絶縁膜
としての第２絶縁膜、５−１はパターンエッヂ、Ａは低
絶縁部、Ｂは高絶縁部である。絶縁性基板１としては、
例えばガラス基板が用いられ、第１金属薄膜４として
は、例えばクロム膜が用いられ、第２金属薄膜３として
は、例えばアルミニウム膜が用いられる。また、第１絶
縁膜２，第２絶縁膜５としては、例えばポリイミド膜が
用いられる。FIG. 3 is a diagram showing a cross section near a boundary between a high insulation portion and a low insulation portion of a conventional thin film circuit. In FIG.
1 is an insulating substrate, 2 is a first insulating film as a common insulating film,
3 is a second metal thin film, 4 is a first metal thin film, 5 is a second insulating film as an additional insulating film, 5-1 is a pattern edge, A is a low insulating portion, and B is a high insulating portion. As the insulating substrate 1,
For example, a glass substrate is used, a chromium film is used as the first metal thin film 4, and an aluminum film is used as the second metal thin film 3, for example. Moreover, as the first insulating film 2 and the second insulating film 5, for example, a polyimide film is used.
【０００４】絶縁性基板１の上に第１金属薄膜４を成膜
し、これをパターニングして第１の回路配線を形成す
る。次に、その上に第１絶縁膜２を成膜し、更に第２絶
縁膜５を成膜する。そして、その上層に形成する予定の
他の第２金属薄膜３の配線分布状況からみて、高絶縁性
を必要とする部分についてだけは第２絶縁膜５が残るよ
う、第２絶縁膜５をパターニングする。パターンエッヂ
５−１は、そのパターニングの際に出来た端縁である。A first metal thin film 4 is formed on the insulating substrate 1 and patterned to form a first circuit wiring. Next, the first insulating film 2 is formed thereon, and the second insulating film 5 is further formed thereon. Then, the second insulating film 5 is patterned so that the second insulating film 5 remains only in a portion requiring high insulating property in view of the wiring distribution of the other second metal thin film 3 to be formed on the upper layer. To do. The pattern edge 5-1 is an edge formed during the patterning.
【０００５】このようにして形成した絶縁層の表面に、
第２金属薄膜３を成膜し、パターンニングして第２の回
路配線を形成する。すると、第２金属薄膜３の部分の
内、第１金属薄膜４の上方に位置する部分は、第１絶縁
膜２と第２絶縁膜５の２重の絶縁膜に隔てられることに
なり、第１金属薄膜４の上方に位置しない部分に比べて
高絶縁性を有することとなる。On the surface of the insulating layer thus formed,
The second metal thin film 3 is formed and patterned to form the second circuit wiring. Then, the portion of the second metal thin film 3 located above the first metal thin film 4 is separated by the double insulating film of the first insulating film 2 and the second insulating film 5. The metal thin film 4 has a higher insulating property than the part not located above the metal thin film 4.
【０００６】[0006]
【発明が解決しようとする課題】（問題点）しかしなが
ら、前記した従来の薄膜回路には、追加絶縁膜としての
第２絶縁膜５のパターンエッヂ５−１により、第２金属
薄膜３の配線が断たれることがあるという問題点があっ
た。(Problem) However, in the above-described conventional thin film circuit, the wiring of the second metal thin film 3 is formed by the pattern edge 5-1 of the second insulating film 5 as an additional insulating film. There was a problem that it was sometimes refused.
【０００７】（問題点の説明）第２絶縁膜５のパターン
エッヂ５−１は、図３に示すように、僅かに隆起する程
度であれば問題ないが、製造時のバラツキにより大きく
隆起することがある。図４は、従来の薄膜回路でパター
ンエッヂが大きい場合の断面を示す図であり、符号は図
３のものに対応している。パターンエッヂ５−１が大き
く隆起していれば、その上に第２金属薄膜３を成膜して
も、パターンエッヂ５−１の先端が第２金属薄膜３の上
に出たままとなることがある。そうすると、その部分で
第２金属薄膜３が突き破られる形となり、パターンニン
グの結果、その部分が配線部分として残された場合、そ
の配線は初めから断線しているものとなってしまう。こ
のような不良品が出来たのでは、製造の歩留りが悪くな
る。本発明は、以上のような問題点を解決することを課
題とするものである。(Explanation of Problems) As shown in FIG. 3, the pattern edge 5-1 of the second insulating film 5 has no problem as long as it slightly swells, but it greatly swells due to variations in manufacturing. There is. FIG. 4 is a diagram showing a cross section of a conventional thin film circuit having a large pattern edge, and reference numerals correspond to those of FIG. If the pattern edge 5-1 is largely raised, even if the second metal thin film 3 is formed on it, the tip of the pattern edge 5-1 will remain above the second metal thin film 3. There is. Then, the second metal thin film 3 is pierced at that portion, and if that portion is left as a wiring portion as a result of patterning, the wiring will be broken from the beginning. If such a defective product is produced, the manufacturing yield is deteriorated. An object of the present invention is to solve the above problems.
【０００８】[0008]
【課題を解決するための手段】前記課題を解決するた
め、本発明では、高絶縁部には低絶縁部と同様に施す共
通絶縁膜に追加して追加絶縁膜を積層する構造の薄膜回
路において、該追加絶縁膜の上に共通絶縁膜を成膜する
こととした。In order to solve the above-mentioned problems, the present invention provides a thin film circuit having a structure in which an additional insulating film is laminated on a common insulating film applied to the high insulating part in the same manner as the low insulating part. A common insulating film is formed on the additional insulating film.
【０００９】[0009]
【作 用】高絶縁部を、低絶縁部と同様に施す共通絶
縁膜に追加して、追加絶縁膜を積層する構造にしている
薄膜回路において、追加絶縁膜の上に共通絶縁膜を成膜
する。そうすれば、追加絶縁膜のパターニングの際に、
大きく隆起したパターンエッヂが生じていたとしても、
それは上に成膜した共通絶縁膜に埋もれるか、あるいは
埋もれなかったとしても、突出する高さは低められる。
そのため、その上に成膜する金属薄膜を突き破ることは
なくなる。[Operation] In the thin-film circuit in which the high insulation part is added to the common insulation film applied in the same way as the low insulation part and the additional insulation film is laminated, the common insulation film is formed on the additional insulation film. To do. Then, when patterning the additional insulating film,
Even if there is a large raised pattern edge,
It is buried in the common insulating film formed above, or even if it is not buried, the protruding height is lowered.
Therefore, it does not break through the metal thin film formed thereon.
【００１０】[0010]
【実施例】以下、本発明の実施例を図面に基づいて詳細
に説明する。図１は、本発明の薄膜回路の高絶縁部と低
絶縁部の境界付近の断面を示す図である。符号は、図３
のものに対応している。本発明では、高絶縁部Ｂを形成
するために絶縁膜を２重に施す場合に、絶縁の程度に差
をつけるために形成する追加絶縁膜の方を最初に形成
し、その上に低絶縁部Ａにおいても同様に施す共通絶縁
膜を形成する。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram showing a cross section near a boundary between a high insulating portion and a low insulating portion of a thin film circuit of the present invention. The reference numeral is FIG.
It corresponds to that of. In the present invention, when the insulating film is doubly applied to form the high insulating portion B, the additional insulating film formed to make the degree of insulation different is formed first, and the low insulating film is formed thereon. A common insulating film is similarly formed in the part A as well.
【００１１】絶縁性基板１の上に第１金属薄膜４を成膜
して第１の回路配線を形成した後、絶縁膜を形成するに
際し、低絶縁部Ａより絶縁の程度を大にするために高絶
縁部Ｂのみに形成する追加絶縁膜としての第１絶縁膜２
を、まず成膜する。そして、高絶縁部Ｂとする部分にの
み残るよう、パターニングする。パターンエッヂ２−１
は、そのパターニング時に出来る端縁である。After forming the first metal thin film 4 on the insulating substrate 1 and forming the first circuit wiring, in order to make the degree of insulation larger than that of the low insulation portion A when forming the insulation film. First insulating film 2 as an additional insulating film formed only on the high insulating portion B
First, a film is formed. Then, patterning is performed so that only the portion to be the high insulating portion B remains. Pattern edge 2-1
Is an edge formed at the time of patterning.
【００１２】次に、低絶縁部Ａ，高絶縁部Ｂの両方に等
しく施す、共通絶縁膜としての第２絶縁膜５を成膜す
る。そして、その上に第２金属薄膜３を成膜して、パタ
ーニングし、第２の回路配線を形成する。このようにし
て薄膜回路を形成すると、第１絶縁膜２のパターニング
の際、たとえパターンエッヂ２−１が製造時のバラツキ
により大きく隆起したとしても、次に述べるように、第
２金属薄膜３の配線を切断することはない。Next, a second insulating film 5 is formed as a common insulating film, which is applied equally to both the low insulating portion A and the high insulating portion B. Then, a second metal thin film 3 is formed thereon and patterned to form a second circuit wiring. When the thin film circuit is formed in this manner, even when the pattern edge 2-1 is largely bulged due to variations in manufacturing during patterning of the first insulating film 2, as described below, It does not cut the wiring.
【００１３】図２は、本発明の薄膜回路でパターンエッ
ヂが大きい場合の断面を示す図であり、符号は図１のも
のに対応している。異なる点は、パターンエッヂ２−１
が、図１の場合に比べて大きく隆起している点である。FIG. 2 is a diagram showing a cross section of the thin film circuit of the present invention when the pattern edge is large, and the reference numerals correspond to those of FIG. The difference is that the pattern edge 2-1
However, it is a point that is largely raised as compared with the case of FIG.
【００１４】パターンエッヂ２−１が大きく隆起してい
ても、その上に直接成膜されるのは第２絶縁膜５であ
り、第２金属薄膜３ではない。従って、仮に大きく隆起
したパターンエッヂ２−１により膜が突き破られること
があったとしても、その膜は第２絶縁膜５であって第２
金属薄膜３ではない。第２絶縁膜５に託されている役割
は、第１絶縁膜２と同じく絶縁に寄与することであるか
ら、それが第１絶縁膜２によって一部突き破られたとし
ても、何ら支障は生じない。Even if the pattern edge 2-1 is largely raised, it is the second insulating film 5 and not the second metal thin film 3 that is directly formed thereon. Therefore, even if the film may be breached by the pattern edge 2-1 that is greatly raised, the film is the second insulating film 5 and the second insulating film 5.
It is not the metal thin film 3. Since the role of the second insulating film 5 is to contribute to the insulation like the first insulating film 2, even if the second insulating film 5 is partially broken by the first insulating film 2, no trouble occurs. Absent.
【００１５】パターンエッヂ２−１は、殆どの場合、第
２絶縁膜５の中に埋まってしまうが、仮に第２絶縁膜５
の表面から突出したとしても、その先端部の高さは僅か
となる。従って、第２絶縁膜５の上層に第２金属薄膜３
を成膜した時、第２金属薄膜３がパターンエッヂ２−１
の先端部により切断されるというようなことは、生じな
くなる。The pattern edge 2-1 is buried in the second insulating film 5 in most cases, but the second insulating film 5 is assumed.
Even if it protrudes from the surface of the, the height of its tip is small. Therefore, the second metal thin film 3 is formed on the second insulating film 5.
When the film is formed, the second metal thin film 3 forms the pattern edge 2-1.
It will no longer be cut by the tip of the.
【００１６】図５，図６は、高絶縁部Ｂと低絶縁部Ａと
が隣接している箇所の１例を示す図であり、図５は平面
図、図６は、図５のＸ−Ｘの部分の断面構造を示す図で
ある。これは、薄膜回路の中に形成する薄膜トランジス
タの部分である。これらの図において、符号は図１のも
のに対応し、６はチャネル層、７はチャネル層保護膜、
８はドレイン電極、９はソース電極、１０はゲート絶縁
膜である。5 and 6 are views showing an example of a portion where the high insulation portion B and the low insulation portion A are adjacent to each other. FIG. 5 is a plan view, and FIG. 6 is X- of FIG. It is a figure which shows the cross-section of the part of X. This is the part of the thin film transistor that is formed in the thin film circuit. In these figures, reference numerals correspond to those in FIG. 1, 6 is a channel layer, 7 is a channel layer protective film,
Reference numeral 8 is a drain electrode, 9 is a source electrode, and 10 is a gate insulating film.
【００１７】絶縁性基板１の上に第１金属薄膜４を成膜
してパターニングした後、ゲート絶縁膜１０を成膜し、
チャネル層６，チャネル層保護膜７を形成する。そし
て、第１金属薄膜４の上方に、追加絶縁膜としての第１
絶縁膜２を成膜，パターニングした後、共通絶縁膜とし
ての第２絶縁膜５を成膜する。この時、パターンエッヂ
２−１の先端部は、第２絶縁膜５に埋もれてしまうか、
突出したとしても、その高さはごく僅かである。After the first metal thin film 4 is formed on the insulating substrate 1 and patterned, the gate insulating film 10 is formed.
The channel layer 6 and the channel layer protective film 7 are formed. Then, the first metal thin film 4 is provided above the first metal thin film 4 with the first
After forming and patterning the insulating film 2, the second insulating film 5 as a common insulating film is formed. At this time, the tip of the pattern edge 2-1 may be buried in the second insulating film 5.
Even if it protrudes, its height is very small.
【００１８】第２絶縁膜５の上に第２金属薄膜３を成膜
し、パターニングするが、パターンエッヂ２−１は、第
２絶縁膜５に埋もれるか低い高さしか突出していないの
で、第２金属薄膜３が断線させられることはない。The second metal thin film 3 is formed on the second insulating film 5 and patterned, but since the pattern edge 2-1 is buried in the second insulating film 5 or protrudes only at a low height, 2 The metal thin film 3 is not broken.
【００１９】[0019]
【発明の効果】以上述べた如く、本発明によれば、低絶
縁部と高絶縁部との境界付近において、絶縁膜のパター
ンエッヂの上方に形成した金属薄膜の配線が、該パター
ンエッヂにより切断された状態の薄膜回路が出来てしま
うことを、防止することが出来る。そのため、製造歩留
りが良くなる。As described above, according to the present invention, the wiring of the metal thin film formed above the pattern edge of the insulating film near the boundary between the low insulating portion and the high insulating portion is cut by the pattern edge. It is possible to prevent the thin film circuit in the closed state from being formed. Therefore, the manufacturing yield is improved.
【図１】 本発明の薄膜回路の高絶縁部と低絶縁部の境
界付近の断面を示す図FIG. 1 is a diagram showing a cross section near a boundary between a high insulating portion and a low insulating portion of a thin film circuit of the present invention.
【図２】 本発明の薄膜回路でパターンエッヂが大きい
場合の断面を示す図FIG. 2 is a diagram showing a cross section of the thin film circuit of the present invention when the pattern edge is large.
【図３】 従来の薄膜回路の高絶縁部と低絶縁部の境界
付近の断面を示す図FIG. 3 is a diagram showing a cross section near a boundary between a high insulation portion and a low insulation portion of a conventional thin film circuit.
【図４】 従来の薄膜回路でパターンエッヂが大きい場
合の断面を示す図FIG. 4 is a diagram showing a cross section of a conventional thin film circuit when the pattern edge is large.
【図５】 高絶縁部と低絶縁部とが隣接している箇所の
１例を示す図FIG. 5 is a diagram showing an example of a portion where a high insulation portion and a low insulation portion are adjacent to each other.
【図６】 図５のＸ−Ｘの部分の断面構造を示す図6 is a diagram showing a cross-sectional structure of a portion XX in FIG.
１…絶縁性基板、２…第１絶縁膜、２−１…パターンエ
ッヂ、３…第２金属薄膜、４…第１金属薄膜、５…第２
絶縁膜、５−１…パターンエッヂ、６…チャネル層、７
…チャネル層保護膜、８…ドレイン電極、９…ソース電
極、１０…ゲート絶縁膜、Ａ…低絶縁部、Ｂ…高絶縁部1 ... Insulating substrate, 2 ... First insulating film, 2-1 ... Pattern edge, 3 ... Second metal thin film, 4 ... First metal thin film, 5 ... Second
Insulating film, 5-1 ... Pattern edge, 6 ... Channel layer, 7
... Channel layer protective film, 8 ... Drain electrode, 9 ... Source electrode, 10 ... Gate insulating film, A ... Low insulating part, B ... High insulating part
Claims (1)
絶縁膜に追加して追加絶縁膜を積層する構造の薄膜回路
において、該追加絶縁膜の上に共通絶縁膜を成膜したこ
とを特徴とする薄膜回路。Claim: What is claimed is: 1. In a thin film circuit having a structure in which a high-insulation portion is formed in the same manner as a low-insulation portion, and an additional insulating film is laminated on a common insulating film, which is common on the additional insulating film. A thin film circuit characterized in that an insulating film is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21295991A JP3158516B2 (en) | 1991-07-30 | 1991-07-30 | Thin film circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21295991A JP3158516B2 (en) | 1991-07-30 | 1991-07-30 | Thin film circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0536850A true JPH0536850A (en) | 1993-02-12 |
| JP3158516B2 JP3158516B2 (en) | 2001-04-23 |
Family
ID=16631130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21295991A Expired - Fee Related JP3158516B2 (en) | 1991-07-30 | 1991-07-30 | Thin film circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3158516B2 (en) |
-
1991
- 1991-07-30 JP JP21295991A patent/JP3158516B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3158516B2 (en) | 2001-04-23 |
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