JPH0536717A - Semiconductor device - Google Patents

Abstract

PURPOSE:To elevate the resistance to hot carrier in all circuit areas while materializing large scale integration and high-speed operation. CONSTITUTION:An impurity layer as the storage node of the memory cell of a SRAM and an impurity layer for the contact of a bit line are constituted of N<-> layers 15 outer than gate electrodes and N<-> layer 64 farther outer than them, and the impurity layer in the peripheral circuit area is constituted of the N<-> layer 15 under the gate electrode and the N<+> layer outer than it. Therefore, resistance to hot carrier is elevated both in the memory cell area and in the peripheral circuit area while materializing large scale integration in the memory cell area and the high speed operation in the peripheral circuit area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS transistor.

[0002]

2. Description of the Prior Art FIG. 4 shows an LDD structure N-channel MOS.
Shows a transistor. In this MOS transistor, SiO ₂ which is a gate insulating film is formed on the surface of the Si substrate 11.
A film 12 is formed, and a gate electrode is formed of a polycrystalline Si film 13 doped with impurities. Polycrystalline Si
On the side surface of the film 13, a side wall made of a SiO ₂ film 14 is formed.

By the way, in order to suppress the deterioration of the device due to hot carriers even when the gate length is less than submicron,
As shown in FIG. 4, the impurities obliquely ion-implanted into the Si substrate 11 N under the gate electrode ^- to form a layer 15, the N ^- the layer 15 and the N ⁺ layer 16 which also extends under the side wall It is considered to configure the source / drain with (for example, Japanese Patent Laid-Open No. 1-212471).

[0004]

However, in the MOS transistor shown in FIG. 4, the N ⁻ layer 15 is the SiO ₂ film 1.
The short-channel effect is stronger than that of the conventional LDD-structured MOS transistor formed below the gate, and the shortening of the gate length is limited. Therefore, it is difficult to achieve high integration in the semiconductor device having the MOS transistor shown in FIG.

On the other hand, as shown in FIG.
When the buried contact holes 23 and 24 of the polycrystalline Si films 21 and 22 for 1 are formed, the polycrystalline Si films 21 and
When patterning 22 the buried contact hole 2
As shown in FIG.
As shown in (b), the dug portion 25 is formed on the Si substrate 11.

As a result, when impurities are ion-implanted into the Si substrate 11 from an oblique direction as described above, FIG. 5B and FIG.
As is clear from the comparison with (c), in the buried contact holes 23, 24, the lateral diffusion length of the impurities forming the N ⁺ layers 26, 27 becomes substantially long. Therefore, when the buried contact hole 23, 24 to each other as shown in FIGS. 5 (a) is adjacent via the SiO ₂ film 31 for element isolation, punch through margin of the SiO ₂ film 31 is lowered, The narrowing of the width of the SiO ₂ film 31 is limited. Therefore, this also makes it difficult to achieve high integration.

Further, as is apparent from FIG. 5D, when the impurities 32 are ion-implanted into the Si substrate 11 from an oblique direction, the impurity concentration at the bottom of the dug portion 25 becomes low, and the N ⁺ layers 26 and 27 are formed. High sheet resistance. Therefore, it is difficult to increase the speed of the semiconductor device having the MOS transistor shown in FIG.

[0008]

In a semiconductor device according to the present invention, a first impurity layer 15 having a relatively low impurity concentration and a first impurity layer 15 connected to the first impurity layer 15 and having a relatively medium impurity concentration. Source and drain are formed of the second impurity layer 64 and the first and second impurity layers 15 and 64.
The first impurity layer 15 on the side opposite to the boundary between them.
The edge of the gate electrode is located near the edge of the gate electrode 13
Source transistor and the first impurity layer 15 and a third impurity layer 16 connected to the first impurity layer 15 and having a relatively high impurity concentration, thereby forming a source / drain. The impurity layer 15 is the gate electrode 1
3 below and at the end of the gate electrode 13 on the edge side, and the boundary between the first and third impurity layers 15 and 16 is located near the edge of the gate electrode 13. 2 MOS transistors.

[0009]

The first MOS in the semiconductor device according to the present invention
In the transistor, since the first impurity layer 15 forming the source / drain is outside the gate electrode, the short channel effect is weak. Therefore, the gate length can be shortened and high integration can be achieved. In addition, the second impurity layer 64
Since the impurity concentration of 1 is not high, the hot carrier resistance is high even though the first impurity layer 15 is outside the gate electrode 13.

On the other hand, in the second MOS transistor, since the impurity concentration of the third impurity layer 16 forming the source / drain is high, the sheet resistance is low and the speed can be increased. Further, since the first impurity layer 15 is below the gate electrode 13, the hot carrier resistance is high despite the high impurity concentration of the third impurity layer 16.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a resistance load type SRAM will be described below with reference to FIGS.

As shown in FIGS. 2 and 3, a resistance load type SRAM
The memory cell flip-flop 33 is composed of driving N-channel MOS transistors 34 and 35 and load resistance elements 36 and 37. The flip-flop 33 and the transfer N-channel MOS transistors 41 and 4 are provided.
A memory cell is composed of 2 and.

N-channel MOS transistors 34 and 35
The ground wire 43 is connected to the source of
A power line 44 is connected to the reference numerals 6 and 37. The word line 45 serves as the gate electrode of the N-channel MOS transistors 41 and 42, and the true complementary bit lines 46 and 47 are connected to one source / drain of each of the N-channel MOS transistors 41 and 42. ing.

Further, in this memory cell, impurity layers 51 to 53 as storage nodes, impurity layers 54 and 55 for contacting bit lines 46 and 47, and ground line 4 are provided.
Impurity layers 56 and 57 for contacting the semiconductor layer 3 are provided. Further, as shown by hatching in FIG. 2, three embedded contact holes 61 to 63 are provided.

By the way, while high integration is required in the memory cell area, high integration is not so required in the peripheral circuit area. On the other hand, the impurity layers 51 to 51 of the memory cell
In 55, the sheet resistance does not have to be so low, whereas in the impurity layer (not shown) in the peripheral circuit region, it is generally necessary to reduce the sheet resistance in order to increase the speed.
Further, also in the impurity layers 56 and 57 of the memory cell, it is necessary to reduce the sheet resistance in order to suppress the rise in the minimum operating voltage.

Therefore, in this embodiment, each of the impurity layers 51 to 55 of the memory cell is N ^{− as} shown in FIG.
It is composed of a layer 15 and an N layer 64. The N ^- layer 15 is
A polycrystalline Si film 1 is formed on the SiO ₂ film 12 which is a gate insulating film.
3 is processed into a gate electrode pattern, and then is formed by an ion implantation method with an inclination angle of about 0 to 7 ° with respect to the normal line of the surface of the Si substrate 11 using the polycrystalline Si film 13 as a mask. Is.

The N layer 64 is formed by forming a side wall of the SiO ₂ film 14 on the side surface of the polycrystalline Si film 13 and then forming these Si films.
Using the O ₂ film 14 and the polycrystalline Si film 13 as a mask, P
Hos ^{+ is applied} to the Si substrate 11 at 5 × 10 ¹³ to 1 × 10 ¹⁴ cm.
It is formed by ion implantation at a relatively low dose of about ^-2 .

On the other hand, each of the impurity layers in the peripheral circuit region which does not have a buried contact is composed of an N ⁻ layer 15 and an N ⁺ layer 16, as shown in FIG. 1B. There is. The N ⁻ layer 15 is formed by an ion implantation method with a tilt angle of about 45 ° with respect to the normal line of the surface of the Si substrate 11 using the polycrystalline Si film 13 as a mask. The N ⁺ layer 16 is formed by ion-implanting As ⁺ into the Si substrate 11 at a high dose of about 3 × 10 ¹⁵ cm ^{−2 using the} polycrystalline Si film 13 as a mask.

Further, as shown in FIG. 1C, each of the impurity layers in the impurity layers 56 and 57 of the memory cell and the portion of the peripheral circuit region having the buried contact has an N ⁻ layer 15 formed therein. And the N ⁺ layer 16. N ^-
The layer 15 is formed by using the polycrystalline Si film 13 or the like as a mask by an ion implantation method with an inclination angle of about 0 to 7 ° with respect to the normal line of the surface of the Si substrate 11. N ⁺ layer 16
Is used as a mask for the As ⁺ with the polycrystalline Si film 13 as a mask.
It is formed by ion-implanting the substrate 11 at a high dose amount of about 3 × 10 ¹⁵ cm ⁻² .

In this embodiment as described above, the impurity layers 51 to 51
The N ⁻ layer 15 of 55 is, as shown in FIG.
Since it is outside the polycrystalline Si film 13 which is the gate electrode,
The short channel effect is weak. Therefore, it is possible to miniaturize the gate length and the width of the element isolation region to achieve high integration of the memory cell region. Further, since the impurity concentration of the N layer 64 is not as high as that of the N ⁺ layer 16, the hot carrier resistance is high even though the N ⁻ layer 15 is outside the gate electrode.

Further, the impurity concentration of the N ⁺ layer 16 in the portion of the peripheral circuit region which does not have the buried contact is high. Therefore, the sheet resistance of the N ⁺ layer 16 is low,
It meets the demand for higher speed in the peripheral circuit area. On the other hand, in the peripheral circuit region, high integration is not required so much, and the gate length can be lengthened. Therefore, as shown in FIG. 1B, the N ⁻ layer 15 is under the gate electrode. For this reason,
Despite the high impurity concentration of the N ⁺ layer 16, the hot carrier resistance is high.

Since the N ⁻ layer 15 of the impurity layers 56 and 57 is outside the gate electrode as shown in FIG. 1C, the short channel effect is weak. Therefore, it is possible to miniaturize the gate length and the width of the element isolation region to achieve high integration of the memory cell region. Moreover, since the impurity concentration of the N ⁺ layer 16 is high, the sheet resistance of the N ⁺ layer 16 is low, and the rise of the minimum operating voltage is suppressed.

The N ⁻ layer 15 in the portion having the buried contact in the peripheral circuit region is formed by the ion implantation method with an inclination angle of about 0 to 7 ° with respect to the normal line to the surface of the Si substrate 11. It was done. Therefore, since the impurity concentration at the bottom of the dug portion 25 (FIG. 5D) is high and the sheet resistance is low, the requirement for speeding up the peripheral circuit region is satisfied.

[0024]

In the semiconductor device according to the present invention, the first MOS transistor is used in the circuit area requiring high integration and the second MOS transistor is used in the circuit area requiring high speed. It is possible to improve the hot carrier resistance in all circuit areas while achieving high integration and high speed.

[Brief description of drawings]

FIG. 1 is a side sectional view of each part of an embodiment of the present invention.

FIG. 2 is a plan view of a memory cell of a resistance load type SRAM to which the present invention can be applied.

FIG. 3 is an equivalent circuit diagram of a memory cell of a resistance load type SRAM.

FIG. 4 is a side sectional view of a conventional example of the present invention.

FIG. 5 shows a problem in one conventional example, (a) is a plan view, (b), (c) and (d) are bb of (a) respectively.
It is a side sectional view which follows a line, a cc line, and a dd line.

[Explanation of symbols]

13 Polycrystalline Si film 15 N ⁻ layer 16 N ⁺ layer 64 N layer

Claims (1)

Claim: What is claimed is: 1. A source is formed from a first impurity layer having a relatively low impurity concentration and a second impurity layer connected to the first impurity layer and having a relatively medium impurity concentration. A first MOS transistor having a drain, and the edge of the first impurity layer on the side opposite to the boundary between the first and second impurity layers is located near the edge of the gate electrode And a source / drain composed of the first impurity layer and a third impurity layer connected to the first impurity layer and having a relatively high impurity concentration, and the first impurity layer is the gate electrode. A second MO which is formed below and at the end of the gate electrode on the side of the edge thereof, and in which the boundary between the first and third impurity layers is located near the edge of the gate electrode.
A semiconductor device having an S transistor.