JPH0536714A - Bipolar transistor and semiconductor device using it - Google Patents

Abstract

PURPOSE:To manufacture a bipolar transistor where the capacitance between a substrate and a collector is reduced, and provide a semiconductor device capable of high speed operation and excellent in radiation resistance free from the soft error by alpha rays or the like. CONSTITUTION:Single crystal layers constituting, at least, active regions, of bipolar transistors 2 and 3 are the nonporous single crystal layers 4 and 5 on a silicon substrate, which has an oxide film being gotten by removing by a process including, at least, wet chemical etching, the silicon substrate being made porous after sticking the surface of the nonporous single crystal layer on the silicon substrate made porous or the surface of the oxidized nonporous single crystal layer to the oxide film 18 of the silicon substrate 1 having an oxide film 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a semiconductor device using the same, and more particularly to a bipolar transistor having a bipolar transistor formed on an insulating substrate and a semiconductor device using the same.

[0002]

2. Description of the Related Art The formation of a single crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and is unattainable in a bulk Si substrate for producing an ordinary Si integrated circuit. Much research has been done because the device utilizing the SOI technology has an advantage. In other words, by using SOI technology,
． Dielectric isolation is easy and high integration is possible. Excellent radiation resistance ,. Stray capacitance is reduced and speedup is possible. The well process can be omitted. Latch-up can be prevented. Advantages such as a fully depleted field effect transistor can be obtained by thinning the film.

In order to realize the many advantages in device characteristics as described above, a method for forming an SOI structure has been researched for several decades. This content is, for example, Special Issue: "Single-crystal silicon on n
on-single-crystal insulators "; edited by GWCulle
n, Journal of Crystal Growth, volume 63, no3, pp 4
29-590 (1983).

Further, SOS (silicon on sapphire) formed by heteroepitaxially forming Si on a single crystal sapphire substrate by a CVD method (chemical vapor deposition method) has been known for a long time and is the most mature. Although it was successful as an SOI technology, a large amount of crystal defects due to the lattice mismatch between the Si layer and the underlying sapphire substrate interface, mixing of aluminum from the sapphire substrate into the Si layer, and above all, the high cost of the substrate The delay in increasing the area prevents the spread of its application. In recent years, attempts have been made to realize an SOI structure without using a sapphire substrate. This attempt is roughly divided into the following two. (1) After the surface of the Si single crystal substrate is oxidized, a window is opened and Si is
The substrate is partially exposed and laterally epitaxially grown using the portion as a seed to form a Si single crystal layer on SiO ₂ (in this case, Si layer is deposited on SiO ₂ ). (2) Using the Si single crystal substrate itself as the active layer,
SiO ₂ is formed thereunder (this method does not involve deposition of a Si layer).

Various semiconductor devices and integrated circuits made of them have been formed on a silicon layer on an insulator formed by these methods.

[0006]

As means for realizing the above (1), a single crystal layer Si is directly formed by a CVD method.
Lateral epitaxial growth, amorphous Si deposition, and solid phase lateral epitaxial growth by heat treatment, electron beam on the amorphous or polycrystalline Si layer,
A method of converging and irradiating an energy beam such as a laser beam to grow a single crystal layer on SiO ₂ by melting and recrystallization, and a method of scanning a melting region in a band shape with a rod heater (Zone melting recrystallization) are known. ing. Each of these methods has advantages and disadvantages,
There are still many problems in its controllability, productivity, uniformity, and quality, and none has been industrially put to practical use. For example, the CVD method requires sacrificial oxidation to achieve a flat thin film, and the solid phase growth method has poor crystallinity. Further, the beam annealing method has problems in processing time by convergent beam scanning, controllability such as beam overlapping and focus adjustment. Of these, the Zone Melting Recrystallization method is the most mature, and relatively large-scale integrated circuits have been prototyped, but crystal defects such as sub-grain boundaries still occur.
Majority remains and has not led to the creation of minority carrier devices.

In the method (2) above, in which the Si substrate is not used as seeds for epitaxial growth, there are the following three types of methods.

[0008] An oxide film is formed on a Si single crystal substrate in which V-shaped grooves are anisotropically etched on the surface, a polycrystalline Si layer is deposited on the oxide film to be as thick as the Si substrate, and then polished from the back surface of the Si substrate. Is a method for forming a Si single crystal region surrounded by V-grooves and dielectrically isolated on a thick polycrystalline Si layer. In this method, the crystallinity is good, but the step of depositing polycrystalline Si to a thickness of several hundreds of microns, and
This requires a step of polishing the single crystal Si substrate from the back surface to leave only the separated Si active layer, which is problematic in terms of controllability and productivity.

[0009]. SIMOX: Seperati
This is a method of forming a SiO ₂ layer by ion implantation of oxygen in a Si single crystal substrate called “on by ion implanted oxygen”, which is the most mature method at present because it has good compatibility with the Si process. However, in order to form the SiO ₂ layer, oxygen ions are added at 10 ¹⁸ ions / cm ^2.
It is necessary to implant the above, the implantation time is long, the productivity cannot be said to be high, and the wafer cost is high. Further, many crystal defects remain, and from an industrial point of view, the quality is not sufficient to produce a minority carrier device.

[0010]. This is a method of forming an SOI structure by dielectric isolation by oxidation of porous Si. This method is
Ion implantation of N-type Si layer on the surface of type Si single crystal substrate (Imai et al., J. Crystal Growth, vol 63, 547 (1983)),
Alternatively, it is formed into an island shape by epitaxial growth and patterning, and only the P-type Si substrate is made porous by an anodization method in a HF solution so as to surround the Si island from the surface, and then the N-type Si island is increased by accelerated oxidation. It is a method of dielectric separation. In this method, the separated Si region is determined before the device process, and there is a problem in that the degree of freedom in device design may be limited. Therefore, as a semiconductor integrated circuit of various SOIs described above, It has not yet reached its full potential.

[0011]

In the bipolar transistor of the present invention, the single crystal layer constituting at least the active region of the bipolar transistor has a surface of a non-porous single crystal layer on a porous silicon substrate, or Obtained by attaching the oxidized surface of the non-porous single crystal layer to the oxide film of a silicon substrate having an oxide film on the surface, and then removing the porous silicon substrate by a step including at least wet chemical etching. And a non-porous single crystal layer on the silicon substrate having the oxide film on the surface.

A semiconductor device of the present invention is characterized by using the bipolar transistor.

Here, the silicon substrate having an oxide film on its surface includes those having electronic circuit elements such as transistors and metal wiring formed thereon.

[0014]

[Operation] Although the density of porous silicon is less than half that of single crystal Si, the single crystallinity is maintained, and it is possible to grow a single crystal Si layer epitaxially on top of the porous layer. It is possible. Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half. As a result, the surface area is dramatically increased as compared with the volume, so that the chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

The present invention utilizes such properties of porous silicon to form a single crystal semiconductor layer on a silicon substrate having an oxide film on its surface, and uses this single crystal semiconductor layer to produce a bipolar transistor. To do. That is, the present invention forms a non-porous single crystal layer with excellent crystallinity on a porous silicon substrate, the surface of the non-porous single crystal layer or the oxidized surface of the non-porous single crystal layer A step of bonding the silicon substrate having an oxide film on its surface to the oxide film and then etching the porous silicon substrate having an etching rate increased as compared with a normal single crystal layer, including at least wet chemical etching. A single crystal semiconductor layer is formed on an insulator base (a silicon base having an oxide film on its surface) by removing the single crystal semiconductor layer, and a bipolar transistor and a semiconductor device using the bipolar transistor are manufactured using the single crystal semiconductor layer. is there.

According to the present invention, a Si single crystal layer having an extremely low number of defects is formed on a silicon substrate having an oxide film on its surface, which is economical, is even and flat over a large area, has extremely excellent crystallinity. Since it is formed and an element is created on this Si single crystal layer, a bipolar transistor with a reduced capacitance between the substrate and collector can be manufactured, high-speed operation is possible, and radiation resistance characteristics without soft error due to α-rays etc. It is possible to provide an excellent semiconductor device.

[0017]

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention. In the figure, the substrate 1 is a silicon substrate having SiO ₂ (18 in FIG. 1) formed on the surface thereof by selectively removing porous Si as described later.

An NPN type bipolar transistor 2 and a PNP type bipolar transistor 3 are formed on the base 1, and a desired semiconductor device is manufactured by appropriately combining the elements of both. Although the bipolar transistor in FIG. 1 is a planar type, the bipolar transistor of the present invention may have a non-planar shape such as a lateral type.

The steps of producing the transistors 2 and 3 will be described below with reference to FIGS. 2, 3 and 4 from the step of producing a single crystal semiconductor layer on an insulating substrate.

2A to 2C and 3A to 3C.
(D) is a process drawing for explaining the method for manufacturing a semiconductor substrate according to the present invention, and is shown as a schematic cross-sectional view in each process. 4A and 4B show N shown in FIG.
FIG. 7 is a schematic cross-sectional view showing a manufacturing process of a PN type bipolar transistor 2 and a PNP type bipolar transistor 3.
As shown in FIG. 2A, first, a Si single crystal substrate is prepared and made porous to form a porous Si single crystal substrate 21. The Si substrate is made porous by an anodizing method using an HF solution. This porous Si layer is a single crystal Si
Compared with the density of 2.33 g / cm ³ , the density was changed to 1.20 by changing the HF solution concentration to 50 to 20%.
It can be changed in the range of 1 to 0.6 g / cm ³ . This porous layer is easily formed on the P-type Si substrate for the following reason. According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in this porous Si layer.

Porous Si is described by Uhlir et al.
It was discovered in the research process of electropolishing of semiconductors in 2010 (A.
Uhlir, Bell Syst.Tech.J., vol 35, p.333 (1956)). Also, Unagami et al. Studied the dissolution reaction of Si in anodization and reported that the anodic reaction of Si in HF solution requires holes, and the reaction is as follows (T .
Unagami: J. Electrochem. Soc., Vol.127, p.476 (198
0)).

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4 -λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ^- SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the numbers of holes required for dissolving one silicon atom, respectively, and porous silicon is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type silicon having holes is likely to be made porous. The selectivity in this porosification has been demonstrated by Nagano et al. And Imai (Nagano, Nakajima, Anno, Ohnaka, Kajiwara; IEICE technical report, vol 79, SSD 79-9549 (1979), (K. Imai; Solid-Sta
te Electronics vol 24,159 (1981)). In this way, the P-type silicon in which holes are present is easily made porous, and the P-type silicon can be selectively made porous.

On the other hand, it is reported that high-concentration N-type silicon is also made porous (RP Holmstrom, IJYChi Appl. Phys. Le.
tt.Vol.42,386 (1983)), it is important to select a substrate that can realize porosity regardless of P type and N type.

Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
The chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

By various growth methods, epitaxial growth is performed on the surface of the porous substrate to form a thin film single crystal layer 22.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Nevertheless, single crystallinity is maintained, and it is also possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, 1000 ° C
In the above, rearrangement of the internal holes occurs and the characteristics of the enhanced etching are impaired. Therefore, for the epitaxial growth of the Si layer, the molecular beam epitaxial growth method, plasma C
Low temperature growth such as VD method, thermal CVD method, photo CVD method, bias sputtering method, liquid phase growth method and the like is preferable.

As shown in FIG. 2B, the insulating layer 2 is formed on the surface.
After preparing the substrate 23 having No. 6 and oxidizing the surface of the single crystal Si layer on the porous Si substrate, the insulating substrate 23 is attached to the oxide layer 24. The oxide layer plays an important role in making a device. That is, the interface level generated by the underlying interface of the Si active layer is lower at the oxide film interface according to the present invention than at the direct bonding interface, and the characteristics of the electronic device are significantly improved. Figure 2
As shown in (b), Si _{3 is used} as an etching prevention film.
An N ₄ layer 25 is deposited to cover the entire two bonded substrates to remove the Si ₃ N ₄ layer on the surface of the porous silicon substrate. Apiezon wax may be used as another etching prevention film instead of the Si ₃ N ₄ layer. After this, the entire porous Si substrate 21 is removed by means such as etching to form the thinned single crystal silicon layer 22 on the insulating substrate 23 and form it.

FIG. 2C shows a semiconductor substrate obtained by the present invention. That is, by removing the Si ₃ N ₄ layer 25 as the etching prevention film in FIG. 2B, the single crystal Si layer 22 having the crystallinity equivalent to that of the silicon wafer is flattened on the insulating substrate 23. Moreover, the layer is uniformly thinned and formed in a large area over the entire wafer. The semiconductor substrate thus obtained can be suitably used from the viewpoint of producing an electronic element which is insulated and separated.

Next, the single crystal thin layer thus prepared on the surface of the insulating substrate is separated by the partial oxidation method or island-shaped etching as shown in FIG. Next, the N-type impurity ions are formed on the single crystal silicon island (4 in FIG. 1) where the NPN transistor (2 in FIG. 1) is to be formed, and the single crystal silicon island (3 in FIG. 1) is to be formed in the PNP transistor (3). P-type impurity ions are independently implanted into 5) of FIG. 1 to form collector regions.

Next, as shown in FIG. 4A, an oxide film 8 is formed on the surface by dry oxidation or wet oxidation by pyrogenicity. Subsequently, the oxide film is partially removed by using photolithography or the like, and an impurity different from that in the collector region is diffused into a part of the collector region 15 by using an ion implantation method, a thermal diffusion method, or the like, to form a base region. Form 7. Next, with a photoresist, ions are implanted into the emitter region 9 and the collector contact region 10 using the formed mask pattern, and impurities are doped at a high concentration so as to be of the same type as the collector region.

Next, as shown in FIG. 4B, the interlayer insulating layer 11 is deposited by using the CVD method, the bias sputtering method or the like. Further, after forming contact holes by photolithography and etching, the electrodes 12, 13, 14 of the base region 7, the emitter region 9, and the collector contact region 10 are made of Al, Al-Si, W, M.
The bipolar transistor of the present invention can be obtained by forming it from o, W silicide, Ti, Ti silicide or the like. An integrated circuit is manufactured by connecting each element to each other by a thin film metal wiring or the like. The type of integrated circuit is not particularly limited.

Hereinafter, another method for manufacturing a semiconductor substrate according to the present invention will be described in detail with reference to the drawings.

FIGS. 3A to 3D are process drawings for explaining another method of manufacturing a semiconductor substrate according to the present invention, each of which is shown as a schematic sectional view in each process.

First, as shown in FIG. 3A, a low impurity concentration layer 32 is formed on a high concentration silicon single crystal substrate 31 by epitaxial growth by various thin film growth methods.
Alternatively, the surface of the P-type Si single crystal substrate 31 is ion-implanted with protons to form the N-type single crystal layer 32.

Next, as shown in FIG. 3B, P-type Si
The single crystal substrate 31 is transformed from the back surface into a porous Si substrate 33 by an anodization method using an HF solution. This porous Si layer has a density of 1.1 to 0.6 g / cm ³ by changing the density of the single crystal Si from 2.33 g / cm ³ to an HF solution concentration of 50 to 20%. It can be changed into a range. This porous layer is formed on the P-type substrate as described above.

As shown in FIG. 3C, the insulating layer 3 is formed on the surface.
An insulating substrate 34 having No. 6 is prepared, and the insulating substrate is attached to the surface of the single crystal Si layer on the porous Si substrate. As shown in FIG. 3C, the porous Si substrate 33 is removed by etching to form a thinned single crystal silicon layer on the insulating substrate.

FIG. 3D shows a semiconductor substrate obtained by the present invention. That is, by removing the Si ₃ N ₄ layer 35 as the etching prevention film in FIG. 3C, the single crystal Si layer 32 having the crystallinity equivalent to that of the silicon wafer is flattened on the insulating substrate 34. Moreover, the layer is uniformly thinned and formed in a large area over the entire wafer.

The semiconductor substrate thus obtained can be preferably used from the viewpoint of producing an electronic element which is insulated and separated.

The above is a method of forming an N-type layer before making it porous, and then selectively making only the P-type substrate porous by anodizing.

A selective etching method for electroless wet etching only porous Si will be described below.

As an etching solution which does not have an etching effect on crystalline Si and can selectively etch only porous Si, hydrofluoric acid, buffered hydrofluoric acid, hydrofluoric acid containing hydrogen peroxide solution or buffered fluorine is used. A mixed solution of an acid, a mixed solution of hydrofluoric acid or a buffered hydrofluoric acid with an alcohol, and a mixed solution of hydrofluoric acid with a hydrogen peroxide solution and an alcohol or a buffered hydrofluoric acid are preferably used. 5 to 12 show porous S
It is a characteristic view which shows the etching time dependence of the thickness of the porous Si and single crystal Si which were etched when i and single crystal Si were infiltrated in said various etching liquids. The etching liquids are 49% hydrofluoric acid in FIG. 5, FIG. 6 is a mixed liquid of 49% hydrofluoric acid and hydrogen peroxide water (1: 5), and FIG. 7 is a mixed liquid of 49% hydrofluoric acid and alcohol ( 10: 1), 49% in Figure 8
Mixture of hydrofluoric acid, alcohol, and hydrogen peroxide (10:
6:50) and FIG. 9 shows buffered hydrofluoric acid, FIG.
0 is a mixed solution of buffered hydrofluoric acid and hydrogen peroxide solution (1:
5), FIG. 11 shows a mixed solution (10: 1) of buffered hydrofluoric acid and alcohol, and FIG. 12 shows a mixed solution (10: 6: 50) of buffered hydrofluoric acid, alcohol and hydrogen peroxide solution. It should be noted that the one to which alcohol was added was infiltrated without stirring, and the one to which alcohol was not added was infiltrated with stirring.

Porous Si is formed by anodizing single crystal Si, and the conditions are as follows. The starting material of porous Si formed by anodization is not limited to single crystal Si, and Si having other crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 2.4 ( Time) Thickness of porous Si: 300 (μm) Porosity: 56 (%) The porous Si prepared under the above conditions was infiltrated into the above various etching solutions at room temperature.

When the reduction in the thickness of the porous Si was measured for the one infiltrated in 49% hydrofluoric acid (white circle in FIG. 5) with stirring, the porous Si was rapidly etched,
90 μm in about 40 minutes, and 20 minutes after 80 minutes
Even 5 μm had a high degree of surface property and was uniformly etched.

The decrease in the thickness of the porous Si was measured for the one infiltrated in a mixed solution (1: 5) of 49% hydrofluoric acid and hydrogen peroxide solution (white circle in FIG. 6) with stirring. , Porous Si is rapidly etched, 112 μm in about 40 minutes, and 256 μm in 80 minutes.
It had a high degree of surface properties and was uniformly etched.

Mixed liquid of 49% hydrofluoric acid and alcohol (1
0: 1) (white circle in FIG. 7) infiltrated without stirring, the reduction in the thickness of the porous Si was measured, and the porous Si was rapidly etched to 85 μm in about 40 minutes. , 195 μm after 80 minutes
Also had a high degree of surface properties and was uniformly etched.

The thickness of the porous Si, which was infiltrated into a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (white circles in FIG. 8) without stirring. The porous Si was rapidly etched, and was 107 μm in about 40 minutes, and even 244 μm after 80 minutes had a high degree of surface property and was uniformly etched.

The reduction in the thickness of the porous Si was measured for the one that was stirred and soaked in buffered hydrofluoric acid (white circle in FIG. 9), and the porous Si was rapidly etched.
70 μm in about 0 minutes, then 11 after 120 minutes
Even 8 μm had a high degree of surface property and was uniformly etched.

When the mixed solution (1: 5) of buffered hydrofluoric acid and hydrogen peroxide solution (white circle in FIG. 10) was soaked and stirred, the decrease in the thickness of the porous Si was measured. The quality Si is rapidly etched, and it is 88 μm in about 40 minutes and 147 μm in 120 minutes.
It had a high degree of surface properties and was uniformly etched.

The decrease in the thickness of the porous Si was measured for the one that was infiltrated in the mixed solution (10: 1) of buffered hydrofluoric acid and alcohol (white circle in FIG. 11) without stirring. Porous Si is rapidly etched, 4
67 μm in about 0 minutes, and 11 after 120 minutes
Even 2 μm had a high degree of surface property and was uniformly etched.

The thickness of the porous Si of a buffered hydrofluoric acid / alcohol / hydrogen peroxide mixture solution (10: 6: 50) (white circles in FIG. 12) infiltrated without stirring. The porous Si was rapidly etched, and it was found that it was 83 μm in about 40 minutes.
After 0 minutes, it had a high surface property of 140 μm and was uniformly etched.

The solution concentration of the hydrogen peroxide solution is 30% here, but it is set at a concentration that does not impair the effect of adding the hydrogen peroxide solution described below and is practically acceptable in the manufacturing process. It As buffered hydrofluoric acid, ammonium fluoride (NH ₄ F) 36.2%, hydrogen fluoride (HF)
A 4.46% aqueous solution is used.

The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid, and hydrogen peroxide solution.
By adding hydrogen peroxide solution, the oxidation of silicon can be accelerated and the reaction rate can be increased as compared with that without addition. By further changing the ratio of hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. Further, by adding alcohol, the bubbles of the reaction product gas due to etching can be instantly removed from the etching surface without stirring, and the porous Si can be uniformly and efficiently etched.

The solution concentration and temperature conditions are set within a range in which the effect of hydrofluoric acid, buffered hydrofluoric acid, the above hydrogen peroxide solution or the above alcohol is exhibited, and the etching rate is practically acceptable in the manufacturing process and the like.

In the present application, the case of the above-mentioned solution concentration and room temperature is taken up as an example, but the present invention is not limited to such conditions.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95%, more preferably 1 to 85%, further preferably 1 to 70% with respect to the etching solution. The NH ₄ F concentration in the acid is set within the range of preferably 1 to 95%, more preferably 5 to 90%, and further preferably 5 to 80% with respect to the etching solution.

The HF concentration is set within the range of preferably 1 to 95%, more preferably 5 to 90%, and further preferably 5 to 80% with respect to the etching solution.

The H ₂ O ₂ concentration is
It is preferably 1 to 95%, more preferably 5 to 90%, still more preferably 10 to 80%, and is set within a range in which the above hydrogen peroxide solution effect is exhibited.

The alcohol concentration is set to preferably 80% or less, more preferably 60% or less, still more preferably 40% or less with respect to the etching solution, and within the range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, further preferably 5 to 60 ° C.

As the alcohol used in the present invention, in addition to ethyl alcohol, it is possible to use isopropyl alcohol or the like which has no practical problem in the manufacturing process such as the manufacturing process and can be expected to have the above-mentioned alcohol addition effect.

Further, 500 μm thick non-porous Si was infiltrated into the above various etching solutions at room temperature. Later,
The reduction in thickness of the non-porous Si was measured. Non-porous Si
Was etched less than 100 Å even after 120 minutes.

Porous Si and non-porous Si after etching
The sample was washed with water, and its surface was microanalyzed with secondary ions. No impurities were detected.

[0066]

EXAMPLES The present invention will be described below with reference to specific examples. In the examples described below, the case where a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10: 6: 50) is used as an etching solution will be taken as an example. It goes without saying that the etching solution can be used in the same manner. (Example 1) A P-type (10
0) A single crystal Si substrate was anodized in a HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Thickness of porous Si: 200 (μm) Porosity: 56 (%) MBE (Molecular Beam Epitaxy) on the P-type (100) porous Si substrate
The Si epitaxial layer was grown at a low temperature of 0.5 micron by the axy method. The deposition conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ^-9 Torr Growth rate: 0.1 nm / sec Next, an oxide layer of 1000 Å was formed on the surface of this epitaxial layer, and the oxidized surface was covered with 5
The other Si substrate on which an oxide layer having a thickness of 000 angstroms has been formed is superposed, and the temperature is adjusted to 800 ° C. in an oxygen atmosphere at 800 ° C.
By heating for 5 hours, both Si substrates were firmly bonded.

Then, the bonded substrates were mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
Selective etching at 6:50) without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution is very low, even after 65 minutes.
It is approximately angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and single crystal Si having a thickness of 0.5 μm is formed on SiO _2.
A layer could be formed.

As a result of the cross-section observation by the transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

An NPN bipolar transistor was produced on the above single crystal silicon thin film. As a result, the capacitance between the collector and substrate was reduced to 3.4 fF, which is almost one fourth of that in the case where a similar element was formed on the single crystal substrate. In addition, a RAM (Random A) having the transistor as a main constituent element
ccess memory), its electrical characteristics were evaluated, and when compared with the device on the single crystal substrate, the gate delay time was about 13
%, And power consumption was reduced by about 10%. Since a known integrated circuit manufacturing technique is used for the method of manufacturing each transistor, description thereof will be omitted, and only the method of forming a substantial single crystal semiconductor layer will be described. The same applies to the following examples. (Example 2) P-type (10
0) A single crystal Si substrate was anodized in a HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Thickness of porous Si: 200 (μm) Porosity: 56 (%) A Si epitaxial layer was grown at a low temperature of 0.5 μm on the P-type (100) porous Si substrate by a plasma CVD method. The deposition conditions are as follows. Gas: SiH ₄ High frequency power: 100 W Temperature: 800 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 2.5 nm / sec Next, an oxide layer of 1000 Å is formed on the surface of this epitaxial layer, and the oxide surface is formed. , On the surface 5
The other Si substrate on which an oxide layer having a thickness of 000 angstroms has been formed is overlaid, and the temperature is set to 800 ° C. in an oxygen atmosphere at 0.
By heating for 5 hours, both Si substrates were firmly bonded.

Thereafter, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10:
Selective etching at 6:50) without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution is very low, even after 65 minutes.
It is approximately angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and single crystal Si having a thickness of 0.5 μm is formed on SiO _2.
A layer could be formed.

Bipolar transistors were formed on the single crystal silicon thin film and were connected to each other to prepare an integrated circuit thereof. A well-known integrated circuit manufacturing technique is used for manufacturing each transistor. (Example 3) A P-type (10
0) A single crystal Si substrate was anodized in a HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Porous Si thickness: 200 (μm) Porosity: 56 (%) A Si epitaxial layer was grown at a low temperature of 0.5 μm on the P-type (100) porous Si substrate by a bias sputtering method. The deposition conditions are as follows.

[0081] RF frequency: 100 MHz _Z frequency power: 600W Temperature: 300 ° C. Ar gas pressure: 8 × 10 ^-3 Torr Growth time: 60 minutes Target direct current bias: -200 V substrate direct current bias: + 5V Next, the surface of the epitaxial layer A 1000 angstrom oxide layer is formed on the
The other Si substrate on which an oxide layer having a thickness of 000 angstroms has been formed is superposed, and the temperature is adjusted to 800 ° C. in an oxygen atmosphere at 800 ° C.
By heating for 5 hours, both Si substrates were firmly bonded.

Then, the bonded substrates were mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
Selective etching at 6:50) without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution is very low, even after 65 minutes.
It is approximately angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and single crystal Si having a thickness of 0.5 μm is formed on SiO _2.
A layer could be formed.

Bipolar transistors were formed on the single crystal silicon thin film and were connected to each other to prepare an integrated circuit. A well-known integrated circuit manufacturing technique is used for manufacturing each transistor. (Example 4) N-type (10
0) A single crystal Si substrate was anodized in a HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Thickness of porous Si: 200 (μm) Porosity: 56 (%) A Si epitaxial layer was grown at a low temperature of 5 microns on the N-type (100) porous Si substrate by a liquid phase growth method. The growth conditions are as follows.

Solvent: Sn Growth temperature: 900 ° C. Growth atmosphere: H ₂ Growth time: 50 minutes Next, an oxide layer of 1000 angstrom was formed on the surface of this epitaxial layer, and 5 was formed on the oxidized surface.
The other Si substrate on which an oxide layer having a thickness of 000 angstroms has been formed is superposed, and the temperature is adjusted to 800 ° C. in an oxygen atmosphere at 800 ° C.
By heating for 5 hours, both Si substrates were firmly bonded.

Then, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10:
Selective etching at 6:50) without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
It is approximately angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm was removed, and a single crystal Si layer having a thickness of 5 μm could be formed on SiO ₂ .

Bipolar transistors were formed on the single crystal silicon thin film and were connected to each other to prepare an integrated circuit. A well-known integrated circuit manufacturing technique is used for manufacturing each transistor. (Example 5) A P-type (10
0) A single crystal Si substrate was anodized in a HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Thickness of porous Si: 200 (μm) Porosity: 56 (%) A Si epitaxial layer was grown at a low temperature of 1.0 micron on the P-type (100) porous Si substrate by a low pressure CVD method. The deposition conditions are as follows. Source gas: SiH ₄ Carrier gas: H ₂ Temperature: 850 ° C. Pressure: 1 × 10 ^-2 Torr Growth rate: 3.3 nm / sec Next, an oxide layer of 1000 Å is formed on the surface of this epitaxial layer, and its oxidation is performed. On the surface, 5 on the surface
The other Si substrate on which an oxide layer having a thickness of 000 angstroms has been formed is superposed, and the temperature is adjusted to 800 ° C. in an oxygen atmosphere at 800 ° C.
By heating for 5 hours, both Si substrates were firmly bonded.

Thereafter, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10:
Selective etching at 6:50) without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is approximately angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and single crystal Si having a thickness of 1.0 μm on SiO ₂ is removed.
A layer could be formed. When SiH ₂ Cl ₂ was used as the source gas, it was necessary to raise the growth temperature by several tens of degrees, but the enhanced etching characteristic peculiar to the porous substrate was maintained.

Bipolar transistors were formed on the single crystal silicon thin film and were connected to each other to prepare an integrated circuit. A well-known integrated circuit manufacturing technique is used for manufacturing each transistor. (Example 6) A P-type (10
0) A Si epitaxial layer was grown on the Si substrate by the CVD method to a thickness of 1 micron. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min. This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosity at this time is 8.4 μm / mi.
n. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer did not change.

Next, 10 is formed on the surface of this epitaxial layer.
A 00 angstrom oxide layer was formed, and the other Si substrate with a 5000 angstrom oxide layer formed on the surface was superposed on the oxidized surface, and the layer was placed in an oxygen atmosphere for 8 hours.
By heating at 00 ° C. for 0.5 hours, both Si substrates were firmly bonded.

Then, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
Selective etching at 6:50) without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution is extremely low, even after 65 minutes.
It is approximately angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
A single crystal Si layer having a thickness of 1.0 μm could be formed on SiO ₂ .

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

Bipolar transistors were formed on the single crystal silicon thin film and were connected to each other to prepare an integrated circuit. A well-known integrated circuit manufacturing technique is used for manufacturing each transistor. (Example 7) P-type (10
0) An Si epitaxial layer was grown on a Si substrate by atmospheric pressure CVD to a thickness of 5 μm. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 l / min. Temperature: 1080 ° C. Pressure: 760 Torr Time: 1 min. The Si substrate was anodized in an HF solution.

The anodization conditions were as follows.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1 Time: 1.6 ( Time) Thickness of porous Si: 200 (μm) Porosity: 56 (%) As described above, in this anodization, P-type (100) Si was used.
Only the substrate was made porous and there was no change in the Si epitaxial layer.

Next, 10 is formed on the surface of this epitaxial layer.
A 00 angstrom oxide layer was formed, and the other Si substrate with a 5000 angstrom oxide layer formed on the surface was superposed on the oxidized surface, and the layer was placed in an oxygen atmosphere for 8 hours.
By heating at 00 ° C. for 0.5 hours, both Si substrates were firmly bonded.

Then, the bonded substrates were mixed with a mixed solution of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide (10:
Selective etching at 6:50) without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was very low, even after 65 minutes.
It is approximately angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
A single crystal Si layer having a thickness of 5 μm could be formed on SiO ₂ .

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained.

Bipolar transistors were formed on the single crystal silicon thin film and were connected to each other to prepare an integrated circuit. A well-known integrated circuit manufacturing technique is used for manufacturing each transistor. (Embodiment 8) P type (10
0) N ions are formed on the surface of the Si substrate by ion implantation of protons.
A type Si layer was formed to 1 micron. H ⁺ injection amount is 5 × 1
It was 0 ¹⁵ (ions / cm ² ). 50% of this board
Anodization was performed in the HF solution. The current density at this time was 100 mA / cm ² . The porosification rate at this time was 8.4 μm / min. And the total thickness of the P-type (100) Si substrate with a thickness of 200 microns is 24
Porosified in minutes. As described above, in this anodization, only the P-type (100) Si substrate is made porous and the N-type S is formed.
There was no change in the i layer.

Next, the surface of this N-type single crystal layer was subjected to 1000
An angstrom oxide layer is formed, and on the oxidized surface,
The other Si substrate with a 5000 angstrom oxide layer formed on the surface was overlaid and placed in an oxygen atmosphere at 800
By heating at 0.5 ° C. for 0.5 hour, both Si substrates were firmly bonded.

Then, the bonded substrates are mixed with a mixed solution of 49% hydrofluoric acid, alcohol, and 30% hydrogen peroxide (10:
Selective etching at 6:50) without stirring.
After 65 minutes, only the single crystal Si layer remained without being etched, and the porous Si substrate was selectively etched and completely removed by using the single crystal Si as an etch stop material.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is approximately angstroms or less, and the selectivity with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several tens of angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 μm is removed, and single crystal Si having a thickness of 1.0 μm on SiO ₂ is removed.
A layer could be formed.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained. (Example 9) P-type (10
0) The single crystal Si substrate was anodized in a 50% HF solution. The current density at this time is 10 mA / cm ²
Met. A porous layer having a thickness of 20 μm was formed on the surface in 10 minutes. On the P-type (100) porous Si substrate, a Si epitaxial layer was grown at a low temperature of 0.5 μm by a low pressure CVD method. The deposition conditions are as follows.

Gas: SiH ₂ Cl ₂ (0.6 1 / min.), H ₂ (100 1 / min) Temperature: 850 ° C. Pressure: 50 Torr Growth rate: 0.1 μm / min Next, the surface of this epitaxial layer Was thermally oxidized to 50 nm. A silicon substrate having a 0.8-micron oxide layer on its surface is superposed on the thermal oxide film, and then 900
Both substrates were firmly bonded by heating at 1.5 ° C. for 1.5 hours.

Then, from the back surface of the silicon substrate, 490
It was removed by micron polishing to expose the porous layer.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 15 minutes, only the single crystal Si layer remains without being etched,
Porous S using single crystal Si as an etch stop material
The i layer was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low and was 40 even after 15 minutes.
It is about a little less than Angstrom, and the selection ratio with respect to the etching rate of the porous layer reaches 10 5 or more, and the etching amount in the non-porous layer (several Angstroms) is a practically negligible reduction in film thickness. After removing the Si ₃ N ₄ layer, 0.5 μm on a silicon substrate having an insulating layer on the surface.
It was possible to form a single crystal Si layer having a thickness of.

Further, the same effect can be obtained by coating with apiezon wax or electron wax instead of the Si ₃ N ₄ layer, and only the porous Si layer can be completely removed.

Bipolar transistors were formed on the single crystal silicon thin film and connected to each other to prepare an integrated circuit. A well-known integrated circuit manufacturing technique is used for manufacturing each transistor. (Example 10) A P-type (1
00) A Si epitaxial layer was grown to 1 micron on the Si substrate by the CVD method. The deposition conditions are as follows.

Reaction gas flow rate: SiH ₂ Cl ₂ 1000 SCCM H ₂ 230 1 / min. Temperature: 1080 ° C. Pressure: 80 Torr Time: 2 min This substrate was anodized in a 50% HF solution. The current density at this time was 100 mA / cm ² . The rate of porosity at this time is 8.4 μm / mi.
n. And a P-type (10
0) The entire Si substrate became porous in 24 minutes. As described above, in this anodization, only the P-type (100) Si substrate was made porous, and the Si epitaxial layer remained unchanged.

Next, a 0.
A silicon substrate having an oxide layer of 8 μm on its surface was overlaid and heated at 900 ° C. for 1.5 hours in an oxygen atmosphere to firmly bond the two substrates.

Si ₃ N ₄ is deposited to a thickness of 0.1 μm by the plasma CVD method to cover the two bonded substrates, and only the nitride film on the porous substrate is removed by reactive ion etching.

Then, the bonded substrates are mixed with 49% hydrofluoric acid, alcohol and hydrogen peroxide solution (10: 6: 5).
In 0), selective etching is performed without stirring. After 65 minutes, only the single crystal Si layer remains unetched,
Porous S using single crystal Si as an etch stop material
The i substrate was selectively etched and completely removed.

The etching rate of the non-porous Si single crystal with respect to the etching solution was extremely low, even after 65 minutes.
It is about a little less than Angstrom, and the selection ratio to the etching rate of the porous layer reaches more than ten to the fifth power, and the etching amount in the non-porous layer (several tens of Angstroms) is a practically negligible reduction in film thickness. That is, the porous Si substrate having a thickness of 200 microns is removed,
After removing the Si ₃ N ₄ layer, 1 μm on the insulating substrate
It was possible to form a single crystal Si layer having a thickness of.

As a result of cross-sectional observation with a transmission electron microscope, S
No new crystal defect was introduced into the i layer, and it was confirmed that good crystallinity was maintained. An integrated circuit was manufactured by manufacturing bipolar transistors in the single crystal silicon thin film and connecting them to each other. A well-known integrated circuit manufacturing technique is used for manufacturing each transistor.

[0127]

As described in detail above, according to the bipolar transistor of the present invention and the semiconductor device using the bipolar transistor,
A high-performance bipolar transistor is manufactured by manufacturing an element on a high quality single crystal layer formed on an insulating substrate. Therefore, it is possible to provide an integrated circuit which has a small capacitance between the substrate and the collector and can be operated at high speed, and which can exhibit various advantages as an SOI without a soft error due to α rays at a low price.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a bipolar transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a substrate manufacturing process of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining a substrate manufacturing process of the present invention.

FIG. 4 is a schematic cross-sectional view for explaining a process of the present invention.

FIG. 5 shows etching characteristics of porous and non-porous Si.

FIG. 6 shows etching characteristics of porous and non-porous Si.

FIG. 7 shows etching characteristics of porous and non-porous Si.

FIG. 8 shows etching characteristics of porous and non-porous Si.

FIG. 9 shows etching characteristics of porous and non-porous Si.

FIG. 10 shows etching characteristics of porous and non-porous Si.

FIG. 11 shows etching characteristics of porous and non-porous Si.

FIG. 12 shows etching characteristics of porous and non-porous Si.

[Explanation of symbols]

1 substrate, 2 NPN type bipolar transistor, 3
PNP bipolar transistor, 4 island-shaped single crystal layer, 5 island-shaped single crystal layer, 6 SiO ₂ , 7 base region, 8 oxide film, 9 emitter region, 10 collector contact region, 11 interlayer insulating layer, 12 base electrode, 13 Emitter electrode, 14 collector electrode, 15 collector region, 18 SiO ₂ , 21 porous Si substrate, 22 non-porous Si single crystal layer, 23
Substrate, 24 Silicon Oxide Layer, 25 Etching Prevention Film, 26 Silicon Oxide Layer, 31 P-Type Si Single Crystal Substrate, 32 N-Type Si Single Crystal Layer, 33 Porous Si Substrate, 34 Substrate, 35 Etching Prevention Film, 36 Silicon Oxide layer.

Claims (4)

[Claims] 1. A single-crystal layer constituting at least an active region of a bipolar transistor is a surface of a non-porous single-crystal layer on a porous silicon substrate or an oxidized surface of the non-porous single-crystal layer, Silicon having an oxide film on the surface, which is obtained by bonding a silicon substrate having an oxide film on the surface to the oxide film and then removing the porous silicon substrate by a step including at least wet chemical etching. A bipolar transistor that is a non-porous single crystal layer on a substrate. 2. The bipolar transistor according to claim 1, which is an NPN type. 3. The bipolar transistor according to claim 1, which is a PNP type. 4. A semiconductor device comprising the bipolar transistor according to claim 2 or 3 as a constituent element.