JPH053668A - Exciting pulse generating method for pulse transformer - Google Patents

Abstract

PURPOSE:To substantially equalize the product of exciting voltage and time on the positive and negative sides of a pulse transformer by generating exciting pulses synchronously with the rising of input pulse and comparing the level of exciting pulse at the time of falling of input pulse with that at the time of generation. CONSTITUTION:Output of a pulse transformer 27 is rectified through a rectifying circuit 28 and amplified to produce a wide gate pulse which is then applied onto the gate of a thyristor 7a. When the pulse transformer 27 is excited according to the wide width gate pulse (a), excitation is stopped at time t4 and thereby the excitation is increased on the positive side for an exciting time T4 immediately before the time t4. When the excitation is not stopped at time t4 but sustained through utilization of charge/discharge characteristics of series circuit of a capacitor 32 and a resistor 31, the pulse transformer 27 is excited on the negative side for a time T5 corresponding to the time T4. Consequently, the difference of the product of exciting voltage and time can be substantially eliminated between the positive and negative sides of the pulse transformer 27 which is thereby prevented from saturation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating an excitation pulse of a pulse transformer, and more particularly, to an excitation pulse generation of a pulse transformer suitable for firing control of a thyristor of a thyristor converter controlled by a wide gate pulse. Regarding the method.

[0002]

2. Description of the Related Art A thyristor converter is applied to various fields. For example, a thyristor converter having a structure shown in FIG. 1 is known as a device for controlling the speed of an AC motor. As shown in FIG. 5, the AC power supplied from the AC power supply 1 is converted to DC by the forward converter 2,
This DC power is supplied to the inverse converter 4 via the smoothing reactor 3.
Is supplied to the reverse converter 4 and converted into AC power having a desired frequency and voltage by the reverse converter 4, thereby controlling the speed of the electric motor 5 connected to the output terminal of the reverse converter 4. Each of the forward converter 2 and the inverse converter 4 is formed using a thyristor, and has pulse amplifiers 14 and 16 respectively.
Is controlled by the firing signal formed by the gate phase control circuits 13 and 15 based on the signal corresponding to the target speed output from the speed control circuit 12 via the.

The inverse converter 4 of the example shown in FIG. 5 is of a three-phase bridge type, and each arm 6 to 11 has a thyristor element 1
Generally, a plurality of thyristors are connected in parallel in consideration of the limitation of the current capacity per unit and the damage of the elements. As a result, the desired current capacity is satisfied, and even if some of the thyristor elements are damaged, the operation can be continued without trouble, and the reliability is improved.

Therefore, in the ignition control circuit of the thyristor element, a wide gate pulse amplifier (hereinafter referred to as WGP amplifier) 1 directly connected to the gate of the thyristor element.
6 is provided for each thyristor element so as to cope with the disconnection operation. For example, as shown in FIG. 5, W is made to correspond to each of the thyristor elements 7a to 7n of the arm 7.
GP amplifiers 16a to 16n are provided. Similarly, a WGP amplifier is provided corresponding to each of the thyristor elements of the other arms 6 and 8 to 11, but they are omitted for simplification of the drawing.

The WGP amplifier provided for each thyristor as described above is formed in the same manner. As an example thereof, a WGP amplifier 16a is shown in FIG.

As shown in FIG. 6, the wide gate pulse shown in FIG. 7A is input from the gate phase control circuit 15 to one input end of the AND circuits 23P and 23N via the signal input end 20. There is. The oscillator 21 generates a pulse (b) having a duty of 50% as shown in FIG. 7B. The pulse (b) is directly applied to the other input terminal of the AND circuit 23P and the inverting circuit 22. The pulse (c) shown in FIG. 7C that has been inverted by is input to the other input terminals of the AND circuit 23N. These AN
The outputs of the D circuits 23P and 23N are amplified by the amplifier circuits 24P and 24P.
The amplifier circuit 2 is input to the base of the N transistor and the output of the AND circuits 23P and 23N is "1".
4P and 24N are turned on. The emitters of the amplifier circuits 24P and 24N are commonly connected, and a pulse transformer 27 is connected via a power supply 25 and a current limiting resistor 26.
Connected to the center tap of the primary winding of the. Both ends of the primary winding are connected to the collectors of the amplifier circuits 24P and 24N, respectively. The secondary winding of the pulse transformer 27 is connected between the gate and cathode of the thyristor 7a via a rectifier circuit 28 and a gate resistor 29.

Due to such a configuration, the wide gate pulse (a) to be inputted, the oscillator 21 and the inverting circuit 2 are inputted.
The amplifying circuits 24P and 24N are alternately turned on and off by the pulse (b) or (c) output from No. 2, and the output of the pulse transformer 27 becomes a signal having an amplified waveform as shown in FIG. 7 (f). Further, it is rectified by the rectifier circuit 28 and is applied to the gate of the thyristor 7a as a wide gate pulse having the waveform shown in FIG.

[0008]

However, according to the above-mentioned conventional method, the oscillation start of the oscillator 21 is not synchronized with the input wide gate pulse (a), and the wide gate pulse (a Since the pulse width of () is not necessarily an even multiple of the width of the pulse (b) generated by the oscillator 21, there is a drawback that the pulse transformer 27 may be saturated. That is, FIG.
Assuming that the wide gate pulse (a) ₁ having the width T ₁ is input at the timing shown in (a), the excitation state of the pulse transformer 27 is as shown in FIG.・ A difference occurs in the time product (the positive side is large in the case shown).

When the wide gate pulse (a) ₂ to be inputted next is inputted to the pulse transformer 27 in such an excited state at the timing t ₃ shown in FIG. 7A, that is, the positive side is changed. At the excitation timing, the pulse transformer 27 saturates and no output is produced at time t _{4 as} shown in FIG. 7F, and the pulse width applied to the gate of the thyristor 7a becomes T _2. .. If this pulse width T ₂ is less than the allowable minimum gate pulse width of the thyristor 7a, the current will flow when the spread of the gate signal in the element is not sufficient, and the thyristor 7a will be damaged. There is fear.

In addition, a wide gate pulse (a) that is input
It is considered that the pulse width T ₂ applied to the gate becomes "zero" depending on the timing of the above, or the pulse width T ₁ thereof. In this case, will be the gate pulse for the first time the thyristors 7a at time t ₅ is applied, as shown in FIG. 5, a plurality of thyristors 7a~7
n will be fired at different timings by the respective WGP amplifiers 16a to 16n.
As a result, an excessive load current may flow through the previously fired thyristor, which may damage the element.

[0011] In all of the above problems, the oscillation start of the oscillator of the excitation pulse for controlling the excitation of the pulse transformer is not synchronized with the input wide gate pulse, and the width of the input wide gate pulse is an integer of the excitation pulse cycle. Since they do not match twice, the voltage-time product of the positive side and the negative side in the excitation state of the pulse transformer (equivalent to the excitation energy)
Is caused by saturation of the pulse transformer at the rising edge of the wide gate pulse.

An object of the present invention is to provide a method for generating an excitation pulse of a pulse transformer, which can make the excitation voltage and time product of the positive side and the negative side of the pulse transformer for amplifying the gate pulse substantially equal.

[0013]

In order to achieve the above object, the present invention generates an excitation pulse of a pulse train having a constant width narrower than the width of an input pulse, and alternately excites a pulse transformer in synchronization with the excitation pulse. In the excitation pulse generation method of the pulse transformer for rectifying the output of the pulse transformer to generate a thyristor gate pulse having a width corresponding to the width of the input pulse, the excitation pulse is generated in synchronization with the rising edge of the input pulse. After that, when the input pulse falls, it is determined whether the high level or low level of the excitation pulse at the time of falling and the high / low level of the excitation pulse at the time of occurrence are different, and when the levels are different, the input pulse falls. When the judgment result is at the same level, the excitation pulse is stopped in synchronization with the rising or falling of the excitation pulse that appears next to Switching the excitation pulse during the force pulse fall Conversely level, and wherein the stopping after a pulse of inverse levels are generated width substantially the same time of the excitation pulse of the previous level switching the.

[0014]

With this configuration, according to the present invention, the excitation pulse having the high and low levels involved in the alternating excitation of the pulse transformer is synchronized with the input pulse, and
The time widths of the high level and the low level are made substantially the same, and the exciting voltage-time product of the positive side and the negative side of the pulse transformer can be made substantially the same. As a result, the pulse transformer is not excited with a biased polarity, and the saturation of the pulse transformer can be prevented.

[0015]

EXAMPLES The present invention will be described below based on examples.

FIG. 1 is a circuit configuration diagram of a gate pulse generator to which an embodiment of an exciting pulse generating method of a pulse transformer of the present invention is applied. In the figure, the alternate long and short dash line 30
The circuit surrounded by is the input synchronous oscillation circuit 30 that implements the excitation pulse generating method according to the features of the present invention, and the other components have the same configuration as the conventional example shown in FIG. Omit it. In the input synchronous oscillation circuit 30, the buffer 38 is formed so that the transistor 38a is turned on / off in synchronism with the input wide gate pulse, and the comparator 37 compares the two input signals A ₁ and B _1. , A ₁ ≧ B ₁ , the transistor 37a is turned on,
It is formed so as to be turned off when A ₁ <B ₁ . The input end of the signal A ₁ of the comparator 37 is the capacitor 32.
Is connected to the power supply + Vcc via a series circuit of resistors 31 and 33. On the other hand, the input end of the signal B ₁ is connected to the power supply + Vcc via the resistor 34, grounded via the resistor 35, and further connected to the output end of the comparator 37 via the resistor 36. The connection points of the resistors 31 and 33 are respectively connected to the output end of the comparator 37, the output end of the buffer 38 via the resistor 39, and the input ends of the signals A ₂ and A ₃ of the comparators 40P and 40N. There is. This comparator 40P, 40
Input terminals of the signals B ₂ and B ₃ of N are constant voltage sources V _B2 and V _B2 , respectively.
It is connected to V _B3 . This comparator 40P, 40
The output terminal of N is connected to the bases of the transistors of the amplifier circuits 24P and 24N.

That is, the input synchronous oscillation circuit 30 has a capacitor 32 whose one end is grounded, and a capacitor charging circuit in which the other end of the capacitor 32 is connected to the control power source + Vcc through a series circuit of a resistor 31 and a resistor 33. And a capacitor discharge circuit in which the connection point between the resistors 31 and 33 is grounded via a transistor 37a which is a first switch element, and a voltage dividing resistor 3 connected between the control power source + Vcc and ground.
A reference voltage generating circuit for generating the reference voltage B ₁ by the second resistors 35 of 4, 35 and a terminal voltage A _{1 of the} capacitor 32.
Having a reference voltage terminal to which the reference voltage B ₁ is input, and turning on the transistor 37a when the voltage A _{1 at the} comparison voltage terminal is high.
And a reference voltage lowering circuit in which the reference voltage terminal of the comparator 37 is connected to the anti-ground side terminal of the transistor 37a through the third resistor 36, and an input wide gate pulse is input to the rising edge of this pulse. It has a transistor 38a which is a second switch element which is turned off in synchronization and turned on in synchronization with the fall, and the transistor 38a is connected to the opposite side of the transistor 37a via a series circuit of the transistor 38a and a fourth resistor 39. And an oscillation control circuit having a ground-side terminal grounded.
The voltage at the anti-ground terminal of a is used as an excitation pulse, and this excitation pulse drives the amplifier circuits 24P, N constituting the excitation circuit of the pulse transformer 27 via the comparators 40P, N.

As will be clarified by the operation description given later, the resistors 35, 36 and 39 are set to values such that the terminal voltage A _{1 of the} capacitor 32 is lower than the reference voltage B ₁ when the transistor 38a is on. The resistance 35 is set to a value larger than that of the resistance 36.

The operation of the embodiment thus constructed will be described with reference to the time chart shown in FIG.

[0020] First, the wide gate pulse (a) shown in FIG. 2 (a), t ₁ operating status of the previous respective portions of "0", the buffer 38 is turned on, the comparator 3 in this state
Since the circuit constants are selected so that the relationship between the input signals A ₁ and B ₁ of 7 is A ₁ <B ₁ as shown in FIG. 2C, the input signals A of the comparators 40P and 40N are ₂ ,
As shown in FIG. 2B, A ₃ has a voltage V ₂ determined by the resistors 33 and 39. Next, when the wide gate pulse (a) rises to “1” at t ₁ , the buffer 38 is turned off, so that the input signals A ₂ and A ₃ change to the voltage V ₁ and at the same time, the input signal of the comparator 37. The voltage of B ₁ changes to V _5, and the voltage of the input signal A ₁ is gradually increased toward V ₅ as shown in FIG. 2C as the capacitor 32 is charged. When the signal A ₁ reaches the voltage V ₅ at t ₂ , the comparator 37 is turned on, so that the input signals A ₂ and A ₃ of the comparators 40P and 40N become “0”. At the same time, the voltage of the signal B ₁ changes from V ₅ to V
_While changing to ₄ , the voltage of signal A ₁ is reduced towards V ₄ by the discharge of capacitor 32. When the voltage of the signal A ₁ reaches V ₄ or less at t ₃ , the comparator 37 is turned off again and returns to the state of t ₁ , and the same operation is repeated.

When the wide gate pulse (a) becomes "0" at t ₄ , the buffer 38 is turned on and the input signals A ₂ and A ₃ of the comparators 40P and 40N temporarily become the above voltage V ₂ . The voltage of the input signal B ₁ of the comparator 37 becomes V ₃ . As a result, the relationship of A ₁ ≧ B ₁ is established, the comparator 37 is turned on, and the voltage of the input signal A ₁ is as the capacitor 32 is discharged, as shown between the times t _{4 and} t _{5 in} FIG. Lowered towards V ₄ . During this period, the input signals A ₂ , A _{3 of} the comparators 40P, 40N are
Becomes “0”, and the input signal B ₁ of the comparator 37 is V ₄
It has become. At t ₅ , when A ₁ reaches V ₄ or less, the comparator 37 is turned off and the comparator 4 is turned on again.
The input signals A ₂ and A ₃ of 0P and 40N are fixed to V _2, and the input signals A ₁ and B ₁ of the comparator 37 are V ₂ and V ₃ respectively.
And is returned to the initial state.

Due to such operation of the input synchronous oscillator 30, the outputs of the comparators 40P and 40N are synchronized with the oscillation of the comparator 37 and are alternately amplified by the amplifier circuits 24P and 24P.
4N is turned on, which causes the pulse transformer 27 to
As shown in FIG. 2 (f), the positive side and the negative side are alternately excited,
The output of the pulse transformer 27 is rectified by the rectifier circuit 28 as shown in FIG. 2 (g) and becomes an amplified wide gate pulse, which is applied to the gate of the thyristor 7a. If the excitation of the pulse transformer 27 is stopped at t ₄ in accordance with the width of the input wide gate pulse (a), the positive side excitation is performed for the excitation time T ₄ immediately before t ₄ shown in FIG. 2 (f). Although it becomes large, it is excited to the negative side for a time T ₅ corresponding to T ₄ by utilizing the charge / discharge characteristics of the series circuit of the capacitor 32 and the resistor 31 without stopping the excitation at t ₄ . .. As a result, the difference between the excitation voltage and the time product of the positive side and the negative side of the pulse transformer 27 can be almost eliminated, and the saturation of the pulse transformer 27 is prevented.

As is clear from FIGS. 2 (a) and 2 (g), the pulse width of the amplified wide gate pulse (g) is widened by T _5; however, in general, a thyristor Since it is not turned off in synchronization with the wide gate pulse (a), there is no problem. It goes without saying that the circuit constant should be selected so that this time T ₅ is sufficiently shorter than the turn-off time of the thyristor.

Although FIG. 2 shows the case where the positive side excitation pulse is output at the falling edge of the input wide gate pulse, the case where the negative side excitation pulse is output will be described here. That is, when the input wide gate pulse falls T ₄ hours before t ₄ in FIG. 2, the buffer 38 is turned on, but the potential at the point in FIG. 1B does not change because the comparator 37 is in the on state. Therefore, the comparator 3
7 input signal B ₁ is held at V ₄ while comparator 3
Similarly to that shown in FIG. 2C, the input signal A _{1 of} 7 gradually decreases according to the discharge characteristic of the capacitor 32, and when A ₁ ≧ B ₁ is satisfied at the same time as the normal excitation pulse width, the comparator 37 Is turned off. Since the voltage of the capacitor 32 is held at V ₂ by the buffer 38, the input signal of the comparator 37 has the relationship of A ₁ <B ₁ and the oscillation is stopped. As a result, the positive side and the negative side have the same number of excitation pulses, so that the excitation of the pulse transformer 27 is not biased to any polarity, and the saturation thereof can be prevented.

That is, in this embodiment, after the excitation pulse is generated in synchronism with the rising edge of the input wide gate pulse, when the input wide gate pulse falls, the high and low levels of the excitation pulse at the falling edge are set. The difference between the high and low levels of the excitation pulse at the time of occurrence is determined, and when the levels are different, the excitation pulse is stopped in synchronization with the rising or falling of the excitation pulse at the falling edge of the input wide gate pulse, and the determination result is obtained. Is at the same level, the excitation pulse of the positive side and the negative side is generated by stopping after generating the excitation pulse of the same width as the pulse width until the falling edge of the input wide gate pulse of the excitation pulse. The difference in time product is set to zero to prevent saturation of the pulse transformer.

FIG. 3 shows another embodiment of the present invention. Figure 3
1 is different from the embodiment shown in FIG. 1 in that the center tap of the primary winding of the pulse transformer 27 is connected to the capacitor 41.
Wide gate pulse (a) at the point grounded via
There when the "0", the comparator 40P, there the voltage of the input signal A _2, A ₃ of 40N in that setting is changed to the high V ₂ 'than V _2.

With this configuration, the initial pulse width of the input signal B ₁ of the comparator 37 is as shown in FIG. 4C, as shown in the time chart of the operation waveforms of the respective parts shown in FIG. It has a narrow width T ₆ . In accordance with this, the exciting voltage initially applied to the pulse transformer 27 is superposed on the voltage charged in the capacitor 41 when the wide gate pulse (a) is “0”, so that it is higher than the voltage V _{6 of the} power supply 25. It becomes a big V ₇ .

Generally, the gate pulse voltage of the thyristor requires a large voltage at the start of ignition, but a small voltage is sufficient thereafter. Therefore, if V ₇ is selected to be a predetermined voltage, the pulse voltage between t _{2 and} t ₅ can be relatively reduced, so that the voltage V _{6 of the} power supply 25 can be made small. is there.

[0029]

As described above, according to the present invention,
After the excitation pulse is generated in synchronization with the rising edge of the input wide gate pulse, when the input wide gate pulse falls, the high and low levels of the excitation pulse at the falling edge and the high and low levels of the excitation pulse at the occurrence Of the excitation pulse when the input wide gate pulse falls, the excitation pulse is stopped in synchronization with the rise or fall of the excitation pulse when the input wide gate pulse falls, and when the determination result is the same level, The input wide gate pulse is generated by generating an exciting pulse of the same level as the pulse width until the falling edge and then stopping.Therefore, the number of positive and negative pulses of the exciting pulse for exciting the pulse transformer and The width can be equal. As a result, the difference between the excitation voltage and the time product of the positive side and the negative side of the pulse transformer can be made zero, saturation of the pulse transformer can be prevented, and damage to the thyristor due to this can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a pulse amplifier to which an excitation pulse generating method for a pulse transformer according to an embodiment of the present invention is applied.

FIG. 2 is a time chart explaining the operation of the embodiment in FIG.

FIG. 3 is a circuit configuration diagram of another embodiment of a pulse amplifier to which the excitation pulse generating method of the pulse transformer of the present invention is applied.

FIG. 4 is a time chart explaining the operation of the embodiment in FIG.

FIG. 5 is an overall block diagram of an example of a thyristor conversion device to which the present invention is applied.

FIG. 6 is a circuit configuration diagram of a conventional pulse amplifier.

FIG. 7 is a time chart for explaining the operation of the conventional example.

[Explanation of symbols]

 24P, 24N amplification circuit 25 power supply 27 pulse transformer 30 input synchronous oscillation circuit 37 comparator 38 buffer 40P, 40N comparator 41 capacitor

Claims (1)

Claim: What is claimed is: 1. An excitation pulse having a constant pulse width narrower than that of an input pulse is generated, the pulse transformer is alternately excited in synchronization with the excitation pulse, and the output of the pulse transformer is rectified. In the excitation pulse generating method of the pulse transformer for generating a thyristor gate pulse having a width corresponding to the width of the input pulse, the excitation pulse is generated in synchronization with the rising edge of the input pulse, and then the falling edge of the input pulse is generated. Occasionally, the difference between the high and low levels of the excitation pulse at the time of the fall and the high and low levels of the excitation pulse at the time of occurrence are determined, and when the levels are different, the rise of the excitation pulse that appears after the fall of the input pulse appears. Alternatively, the excitation pulse is stopped in synchronization with the falling edge, and when the judgment result is at the same level, the excitation pulse is stopped when the input pulse falls. Switches the scan in the reverse level, the pulse transformers of the excitation pulse generator wherein the stopping after a pulse of inverse levels are generated width substantially the same time of the excitation pulse of the previous level switching the.