JPH0536501A - Laminated positive characteristic thermistor - Google Patents
Laminated positive characteristic thermistorInfo
- Publication number
- JPH0536501A JPH0536501A JP21260591A JP21260591A JPH0536501A JP H0536501 A JPH0536501 A JP H0536501A JP 21260591 A JP21260591 A JP 21260591A JP 21260591 A JP21260591 A JP 21260591A JP H0536501 A JPH0536501 A JP H0536501A
- Authority
- JP
- Japan
- Prior art keywords
- laminated
- sintered body
- temperature coefficient
- coefficient thermistor
- positive temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- Thermistors And Varistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電気抵抗値が温度によ
って変化する正の抵抗温度特性を有する積層型正特性サ
ーミスタに関し、特に該サーミスタをプリント基板上に
実装する際の半田喰われを防止して半田付け性を向上で
きるようにした構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated positive temperature coefficient thermistor having a positive resistance-temperature characteristic in which an electric resistance value changes with temperature, and particularly prevents solder leaching when the thermistor is mounted on a printed circuit board. The present invention relates to a structure capable of improving solderability.
【０００２】[0002]
【従来の技術】正の抵抗温度特性を有するチタン酸バリ
ウム系正特性サーミスタは、キュリー点以上で抵抗値が
急激に増加する特性を有しており、例えば電気回路の過
電流保護素子用として，あるいはテレビのブラウン管枠
の消磁用など、多くの分野で使用されている。また、近
年の表面実装に対応するために、例えば特公昭57-60802
号公報には積層型の正特性サーミスタが提案されてい
る。この積層型正特性サーミスタは、ＢａＴｉＯ3 を主
成分とするセラミックス層とＰｔ−Ｐｄペーストからな
る内部電極とを交互に積層して一体焼結するとともに、
該焼結体の左, 右端面にＡｇからなる外部電極を形成
し、該外部電極に上記各内部電極の一端面を交互に接続
して構成されている。2. Description of the Related Art A barium titanate-based positive temperature coefficient thermistor having a positive resistance temperature characteristic has a characteristic that the resistance value sharply increases above the Curie point. For example, as an overcurrent protection element for an electric circuit, It is also used in many fields, such as for degaussing TV picture frame. In addition, in order to correspond to the recent surface mounting, for example, Japanese Patent Publication No. 57-60802.
In the publication, a laminated positive temperature coefficient thermistor is proposed. In this laminated positive temperature coefficient thermistor, ceramic layers containing BaTiO 3 as a main component and internal electrodes made of Pt-Pd paste are alternately laminated and integrally sintered, and
External electrodes made of Ag are formed on the left and right end faces of the sintered body, and one end faces of the internal electrodes are alternately connected to the external electrodes.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上記積層型
正特性サーミスタにおいて表面実装に対応するには、通
常の正特性サーミスタとして優れているだけでなく、プ
リント基板上に実装する際の半田付け性が要求される。
即ち、上記従来の積層型正特性サーミスタの外部電極を
プリント基板の回路配線に半田付けする場合、この外部
電極はＡｇ製であることから、半田が電極膜を浸食する
いわゆる半田喰われが生じ易いという問題がある。この
半田付け性を改善するには、上記外部電極の表面にメッ
キ膜を形成することが有効であることが知られている。
しかしながら、上記従来の焼結体は半導体であることか
ら焼結体の全面にメッキ膜が付着し、このままでは外部
電極のみにメッキ膜を形成することはできないという問
題点がある。By the way, in order to cope with surface mounting in the above-mentioned laminated type positive temperature coefficient thermistor, not only is it excellent as a normal positive temperature coefficient thermistor, but also solderability at the time of mounting on a printed circuit board. Is required.
That is, when the external electrode of the conventional laminated positive temperature coefficient thermistor is soldered to the circuit wiring of the printed circuit board, since the external electrode is made of Ag, so-called solder erosion in which the solder erodes the electrode film is likely to occur. There is a problem. It is known that forming a plating film on the surface of the external electrode is effective for improving the solderability.
However, since the above-mentioned conventional sintered body is a semiconductor, there is a problem that the plating film adheres to the entire surface of the sintered body and the plating film cannot be formed only on the external electrode as it is.
【０００４】本発明は上記従来の状況に鑑みてなされた
もので、外部電極部分のみのメッキ膜形成を可能にして
表面実装する際の半田喰われを防止でき、半田付け性を
向上できる積層型正特性サーミスタを提供することを目
的としている。The present invention has been made in view of the above-mentioned conventional situation, and it is possible to form a plating film only on the external electrode portion, prevent solder erosion during surface mounting, and improve the solderability. The purpose is to provide a positive temperature coefficient thermistor.
【０００５】[0005]
【課題を解決するための手段】そこで本発明は、半導体
セラミックス層と内部電極とを交互に積層して一体焼結
し、該焼結体の両端面に上記内部電極の一端面が接続さ
れる外部電極を形成してなる積層型正特性サーミスタに
おいて、上記焼結体の外部電極を除く外表面にガラス膜
を被覆形成したことを特徴としている。Therefore, according to the present invention, semiconductor ceramic layers and internal electrodes are alternately laminated and integrally sintered, and one end face of the internal electrode is connected to both end faces of the sintered body. A laminated positive temperature coefficient thermistor formed with external electrodes is characterized in that a glass film is formed on the outer surface of the sintered body excluding the external electrodes.
【０００６】[0006]
【作用】本発明に係る積層型正特性サーミスタによれ
ば、焼結体の外部電極を除く外表面をガラス膜で覆った
ので、これに例えば電解メッキ処理を施せば、絶縁体で
あるガラス膜にはメッキ膜が成長することなく、外部電
極の表面のみにメッキ膜が形成されることとなる。その
結果、外部電極のみのメッキ膜形成が可能となって半田
喰われを防止でき、それだけ半田付け性を向上できる。According to the laminated positive temperature coefficient thermistor according to the present invention, the outer surface of the sintered body excluding the external electrodes is covered with the glass film. Therefore, the plating film does not grow and the plating film is formed only on the surface of the external electrode. As a result, it is possible to form a plating film only on the external electrodes, prevent solder erosion, and improve solderability.
【０００７】[0007]
【実施例】以下、本発明の実施例を説明する。図１ない
し図４は本発明の一実施例による積層型正特性サーミス
タを説明するための図である。図において、１は本実施
例の積層型正特性サーミスタである。この正特性サーミ
スタ１は直方体状のもので、ＢａＴｉＯ3 を主成分とす
る半導体セラミックス層２と、Ｐｔ−Ｐｄからなる内部
電極３とを交互に積層するとともに、最上部，最下部に
ダミーとしてセラミックス層８を重ねて積層体を形成
し、該積層体を一体焼結して焼結体４を形成して構成さ
れている。また上記各内部電極３の一端面３ａは焼結体
４の左, 右端面４ａ，４ｂに交互に露出されており、他
の端面はセラミックス層２の内側に位置して焼結体４内
に封入されている。EXAMPLES Examples of the present invention will be described below. 1 to 4 are views for explaining a laminated positive temperature coefficient thermistor according to an embodiment of the present invention. In the figure, reference numeral 1 is a laminated positive temperature coefficient thermistor of this embodiment. This positive temperature coefficient thermistor 1 is in the shape of a rectangular parallelepiped, and a semiconductor ceramic layer 2 containing BaTiO 3 as a main component and an internal electrode 3 made of Pt-Pd are alternately laminated, and ceramics are used as a dummy on the uppermost and lowermost portions. The layers 8 are stacked to form a laminated body, and the laminated body is integrally sintered to form a sintered body 4. In addition, one end surface 3a of each internal electrode 3 is alternately exposed to the left and right end surfaces 4a and 4b of the sintered body 4, and the other end surface is located inside the ceramic layer 2 and inside the sintered body 4. It is enclosed.
【０００８】そして、上記焼結体４の左, 右端面４ａ，
４ｂを除く各側面には本実施例の特徴をなすガラス膜６
が被覆形成されている。このガラス膜６はＳｉの酸化物
を主成分としたペーストを塗布し、これを焼き付けて形
成されたものである。The left and right end surfaces 4a of the sintered body 4 are
On each side except 4b, a glass film 6 which is the feature of this embodiment.
Are coated. The glass film 6 is formed by applying a paste containing Si oxide as a main component and baking it.
【０００９】また、上記焼結体４の左, 右端面４ａ，４
ｂにはＡｇからなる外部電極５が形成されており、該外
部電極５は上記内部電極３の一端面３ａに電気的に接続
されている。さらに、上記外部電極５の外表面には、配
線パターンとの半田付け性を向上させるためのメッキ膜
７が被覆形成されており、これは電解メッキにより形成
されたものである。このようにして本実施例の積層型正
特性サーミスタ１は、上記焼結体４の外部電極５，メッ
キ膜７が形成された左, 右端面４ａ，４ｂ以外の外表面
がガラス膜６で覆われた構造となっている。The left and right end faces 4a, 4 of the sintered body 4 are also
An external electrode 5 made of Ag is formed on b, and the external electrode 5 is electrically connected to one end face 3a of the internal electrode 3. Further, the outer surface of the external electrode 5 is coated with a plating film 7 for improving solderability with a wiring pattern, which is formed by electrolytic plating. In this way, in the laminated positive temperature coefficient thermistor 1 of the present embodiment, the outer surface of the sintered body 4 other than the left and right end surfaces 4a and 4b on which the external electrodes 5 and the plating film 7 are formed is covered with the glass film 6. It has a broken structure.
【００１０】次に本実施例の積層型正特性サーミスタ１
の製造方法について説明する。まず、ＢａＣＯ3 ，Ｔｉ
Ｏ2 ，ＳｒＣＯ3 ，Ｙ2 Ｏ3 を以下の組成となるよう調
合して原料を作成する。 （Ｂａ0.9458Ｓｒ0.05Ｙ0.004 ）ＴｉＯ3 ＋0.002 Ｍｎ＋0.007 ＳｉＯ2 上記原料を、純水，及びジルコニアボールとともにポ
リエチレン製ポットに入れて５時間粉砕混合した後、乾
燥させて1100℃で２時間仮焼成する。Next, the laminated positive temperature coefficient thermistor 1 of this embodiment
The manufacturing method of is explained. First, BaCO3, Ti
O2, SrCO3, Y2O3To make the following composition
Combine to create raw materials. (Ba0.9458Sr0.05Y0.004 ) TiO3+0.002 Mn +0.007 SiO2 The above raw materials were mixed with pure water and zirconia balls.
Put in a polyethylene pot, crush and mix for 5 hours, then dry.
Dry and calcinate at 1100 ° C for 2 hours.
【００１１】次いで、この仮焼成体を粉砕して仮焼成粉
を形成し、この仮焼成粉をポリエチレン製ポットに入
れ、これにジルコニアボール，可塑剤，溶液，有機バイ
ンダ及び分散剤を添加して16時間混合し、所定粘度のス
ラリーを得る。このスラリーをドクターブレード法によ
り、厚さ100 μm のセラミックスグリーンシートに成形
し、このグリーンシートを矩形状に打ち抜いて多数の半
導体セラミックス層２を形成する。Then, the calcined body is crushed to form a calcined powder, and the calcined powder is put into a polyethylene pot, to which zirconia balls, a plasticizer, a solution, an organic binder and a dispersant are added. Mix for 16 hours to obtain a slurry with a predetermined viscosity. This slurry is formed into a ceramic green sheet having a thickness of 100 μm by the doctor blade method, and this green sheet is punched into a rectangular shape to form a large number of semiconductor ceramic layers 2.
【００１２】次に、上記各セラミックス層２の上面に、
Ｐｔ−Ｐｄ合金からなるペーストをスクリーン印刷して
内部電極３を形成する。この場合、内部電極３の一端面
３ａのみがセラミックス層２の端縁まで延び、他の端面
は内側に位置するように形成する。Next, on the upper surface of each ceramic layer 2,
The internal electrode 3 is formed by screen-printing a paste made of a Pt-Pd alloy. In this case, only one end surface 3a of the internal electrode 3 extends to the end edge of the ceramic layer 2, and the other end surface is located inside.
【００１３】そして、図４に示すように、上記セラミッ
クス層２と内部電極３とが交互に重なり、かつ該内部電
極３の一端面３ａがセラミックス層２の左, 右端面に交
互に露出するよう積層し、これの上面，下面にダミーと
してのセラミックス層８，８を重ねる。次いで、これを
プレスで加圧，圧着して積層体を形成し、該積層体をカ
ッターで切断して所定寸法に仕上げる。これにより、上
記内部電極３の一端面３のみが積層体の左, 右端面に露
出し、残りの部分は積層体内に封入されることとなる。Then, as shown in FIG. 4, the ceramic layers 2 and the internal electrodes 3 are alternately overlapped with each other, and one end face 3a of the internal electrodes 3 is alternately exposed to the left and right end faces of the ceramic layer 2. The layers are laminated, and the ceramic layers 8, 8 as dummy are superposed on the upper and lower surfaces thereof. Next, this is pressed and pressure-bonded by a press to form a laminated body, and the laminated body is cut with a cutter to finish to a predetermined size. As a result, only one end face 3 of the internal electrode 3 is exposed on the left and right end faces of the laminated body, and the remaining portion is enclosed in the laminated body.
【００１４】次に、上記積層体を1350℃で１時間加熱焼
成し、焼結体４を得る。この焼結体４の内部電極３が露
出する左, 右端面４ａ，４ｂ以外の各側面にＳｉＯ2 を
主成分とするガラスペーストを塗布し、これを600 ℃で
焼き付けてガラス膜６を形成する。Next, the above laminated body is heated and baked at 1350 ° C. for 1 hour to obtain a sintered body 4. A glass paste containing SiO 2 as a main component is applied to each side surface of the sintered body 4 except the left and right end surfaces 4a and 4b where the internal electrodes 3 are exposed, and the glass paste is baked at 600 ° C. to form a glass film 6. ..
【００１５】次いで、上記焼結体４の左, 右端面４ａ，
４ｂにＡｇペーストを塗布した後、焼き付けて外部電極
５を形成する。ここで、図２に示すように、上記Ａｇペ
ーストを塗布する場合、外部電極５がガラス膜６の端縁
部に重なるように形成するのが望ましい。Next, the left and right end faces 4a of the sintered body 4 are
After coating the Ag paste on 4b, the external electrode 5 is formed by baking. Here, as shown in FIG. 2, when the Ag paste is applied, it is desirable that the external electrode 5 is formed so as to overlap the edge portion of the glass film 6.
【００１６】最後に、上記焼結体４に電解メッキを施
し、上記外部電極５の外表面にメッキ膜７を形成する。
この場合、上記焼結体４の外部電極５以外の部分はガラ
ス膜６で覆われていることから、メッキが成長すること
はない。これにより本実施例の積層型正特性サーミスタ
１が製造される。Finally, the sintered body 4 is electroplated to form a plating film 7 on the outer surface of the external electrode 5.
In this case, since the portion of the sintered body 4 other than the external electrode 5 is covered with the glass film 6, the plating does not grow. As a result, the laminated positive temperature coefficient thermistor 1 of this embodiment is manufactured.
【００１７】本実施例の積層型正特性サーミスタ１は、
プリント基板の配線パターン上に載置され、該パターン
にメッキ膜７を半田付け接続して表面実装される。この
場合、焼結体４の左, 右端面４ａ，４ｂを除く各側面に
ガラス膜６を形成したので、外部電極５にのみメッキ膜
７の形成が可能となって表面実装時における半田喰われ
を防止して半田付け性を向上できる。The laminated positive temperature coefficient thermistor 1 of this embodiment is
It is placed on the wiring pattern of the printed board, and the plating film 7 is soldered and connected to the pattern for surface mounting. In this case, since the glass film 6 is formed on each side surface of the sintered body 4 except the left and right end surfaces 4a and 4b, the plating film 7 can be formed only on the external electrode 5, and the solder is not consumed during surface mounting. Can be prevented and solderability can be improved.
【００１８】図５は、上記実施例により製造された積層
型正特性サーミスタ１の抵抗温度特性を示す特性図であ
る。この図からも明らかなように、本実施例の積層型正
特性サーミスタによれば、キュリー点で抵抗値が約５桁
上昇しており、実用上問題のない特性が得られているこ
とがわかる。FIG. 5 is a characteristic diagram showing the resistance-temperature characteristic of the laminated positive temperature coefficient thermistor 1 manufactured in the above embodiment. As is clear from this figure, according to the laminated positive temperature coefficient thermistor of this embodiment, the resistance value increased by about 5 digits at the Curie point, and it was found that the characteristics having no problem in practical use were obtained. ..
【００１９】[0019]
【発明の効果】以上のように本発明に係る積層型正特性
サーミスタによれば、焼結体の外部電極を除く外表面に
ガラス膜を形成したので、外部電極の表面のみのメッキ
形成が可能となり、その結果表面実装時における半田喰
われを防止して半田付け性を向上できる効果がある。As described above, according to the laminated positive temperature coefficient thermistor according to the present invention, since the glass film is formed on the outer surface of the sintered body excluding the external electrode, it is possible to form the plating only on the surface of the external electrode. As a result, solder leaching during surface mounting can be prevented and solderability can be improved.
【図１】本発明の一実施例による積層型正特性サーミス
タを説明するための断面図である。FIG. 1 is a sectional view illustrating a laminated positive temperature coefficient thermistor according to an embodiment of the present invention.
【図２】上記実施例の積層型正特性サーミスタの一部拡
大断面図である。FIG. 2 is a partially enlarged cross-sectional view of a laminated positive temperature coefficient thermistor of the above embodiment.
【図３】上記実施例の積層型正特性サーミスタの斜視図
である。FIG. 3 is a perspective view of a laminated positive temperature coefficient thermistor of the above embodiment.
【図４】上記実施例の積層型正特性サーミスタの製造方
法を説明するための分解斜視図である。FIG. 4 is an exploded perspective view for explaining a method of manufacturing the laminated positive temperature coefficient thermistor of the above embodiment.
【図５】上記実施例の効果を説明するための抵抗温度特
性を示す特性図である。FIG. 5 is a characteristic diagram showing resistance-temperature characteristics for explaining the effect of the above-described embodiment.
１ 積層型正特性サーミスタ ２ 半導体セラミックス層 ３ 内部電極 ３ａ 内部電極の一端面 ４ 焼結体 ４ａ，４ｂ 焼結体の両端面 ５ 外部電極 ６ ガラス膜 1 Laminated Positive Characteristic Thermistor 2 Semiconductor Ceramic Layer 3 Internal Electrode 3a One End Surface of Internal Electrode 4 Sintered Body 4a, 4b Both End Surfaces of Sintered Body 5 External Electrode 6 Glass Film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 坂部 行雄 京都府長岡京市天神２丁目26番10号 株式 会社村田製作所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Sakabe 2 26-10 Tenjin Tenjin, Nagaokakyo-shi, Kyoto Murata Manufacturing Co., Ltd.
Claims (1)
互に積層して一体焼結し、該焼結体の両端面に上記内部
電極の一端面が接続される外部電極を形成してなり、正
の抵抗温度特性を有する積層型正特性サーミスタにおい
て、上記焼結体の外部電極を除く外表面をガラス膜で覆
ったことを特徴とする積層型正特性サーミスタ。Claim: What is claimed is: 1. A semiconductor ceramic layer and an internal electrode are alternately laminated and integrally sintered, and an external electrode to which one end face of the internal electrode is connected to both end faces of the sintered body. A laminated positive temperature coefficient thermistor, which is formed and has a positive resistance temperature characteristic, characterized in that the outer surface of the sintered body excluding the external electrodes is covered with a glass film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21260591A JPH0536501A (en) | 1991-07-29 | 1991-07-29 | Laminated positive characteristic thermistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21260591A JPH0536501A (en) | 1991-07-29 | 1991-07-29 | Laminated positive characteristic thermistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0536501A true JPH0536501A (en) | 1993-02-12 |
Family
ID=16625462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21260591A Withdrawn JPH0536501A (en) | 1991-07-29 | 1991-07-29 | Laminated positive characteristic thermistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0536501A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997047017A1 (en) * | 1996-06-03 | 1997-12-11 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing varistor |
| JP2002141206A (en) * | 2001-09-17 | 2002-05-17 | Mitsubishi Materials Corp | Laminated chip thermistor |
| JP2012059786A (en) * | 2010-09-06 | 2012-03-22 | Tdk Corp | Ceramic multilayer ptc thermistor |
| KR101333258B1 (en) * | 2012-03-30 | 2013-11-26 | 주식회사 이노칩테크놀로지 | Variable Resistor Element And Fabrication Methods Thereof |
-
1991
- 1991-07-29 JP JP21260591A patent/JPH0536501A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997047017A1 (en) * | 1996-06-03 | 1997-12-11 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing varistor |
| US6260258B1 (en) | 1996-06-03 | 2001-07-17 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing varistor |
| JP2002141206A (en) * | 2001-09-17 | 2002-05-17 | Mitsubishi Materials Corp | Laminated chip thermistor |
| JP2012059786A (en) * | 2010-09-06 | 2012-03-22 | Tdk Corp | Ceramic multilayer ptc thermistor |
| CN102403077A (en) * | 2010-09-06 | 2012-04-04 | Tdk株式会社 | Multilayer PTC thermistor |
| US8339237B2 (en) | 2010-09-06 | 2012-12-25 | Tdk Corporation | Multilayer PTC thermistor |
| KR101333258B1 (en) * | 2012-03-30 | 2013-11-26 | 주식회사 이노칩테크놀로지 | Variable Resistor Element And Fabrication Methods Thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981008 |