JPH0536292A - Shift register circuit - Google Patents

Abstract

PURPOSE:To provide a shift register circuit in which the bit shift speed is fast and the number of elements is small. CONSTITUTION:For a bit part 10A, an input signal is latched by a latch part 1, a first latch signal SM1 is outputted, further, the negative OR of the latch signal SM1 and a clock signal phi0 is obtained by a NOR circuit NOR and a first bit output signal SA is outputted. For a bit part 10B, the latch signal SM1 from the latch part 1 is latched by a latch part 2, a second latch signal SM2 is outputted, further, the OR of the latch signal SM2 and the inverting signal in the same period of the clock signal is obtained by an AND circuit AND and a second bit output signal SB is outputted. Thus, for each period of the clock signal, the shifting of the data of 2 bits can be performed, the shifting speed is improved to two times as much as the conventional one and the number of elements is made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit used in a shift register, and more particularly to a shift register circuit in which the number of constituent elements is reduced and the shift speed is increased.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional shift register circuit. The shift register circuit 30 of this conventional example has the same circuit configuration and the transfer gate TG.
₁ and TG ₂ , and clocked inverter CI ₁
And the clock signals φ ₀ and φ ₁ supplied to CI _2.
By connecting two latch units 1 and 2 in which the (inverted signal of the clock signal φ ₀ ) is in the opposite phase to each other in cascade, the first bit output signal S _A is output from the first bit end T _A of the latch unit 2. It includes a bit portion 30A for outputting and a bit portion 30B for inputting the bit output signal S _A with the same circuit configuration and outputting the second bit output signal S _B from the bit end T _B.

The latch section 1 receives an input signal S _I at its input end and inputs clock signals φ ₀ and φ ₁ to its gate to input the input signal S _I to an inverter I ₁ and a clocked inverter C.
And a first transfer gate TG ₁ is transmitted to the input terminal of the inverter I ₁ reverse parallel circuit I _1.

FIG. 4 is a waveform diagram of signals at various parts for explaining the operation of the circuit of FIG. As shown in FIG. 4, when the input signal S _I and the clock signals φ ₀ and φ ₁ are input, the transfer gate TG ₂ of the latch unit ₂ becomes conductive at the first rising time t ₄ of the clock signal φ ₀ . It is turned on.), And the bit output signal S _A of the bit unit 30A becomes “H” (high) level.

Next, at the second rising time t ₅ of the clock signal φ ₀ , the bit output signal S _B of the bit unit 30B becomes "H" level. At this time, the output signal S _A of the bit unit 30A becomes “L” (low) level.

As described above, in the conventional shift register circuit 30, at the rising times t ₄ and t ₅ that occur every one cycle τ of the clock signal φ ₀ , the data is transferred to the upper bits, that is, the bit part 30A to the bit part. It was supposed to be transmitted to 30B.

[0007]

In the conventional shift register circuit described above, since the value of each bit changes and the data shifts to the upper bit at the rising time which occurs in each cycle of the clock signal φ ₀ , the shift speed is increased. There was a slow drawback.

Further, since two latch circuits are used for each bit, there is a drawback that the number of elements increases.

It is an object of the present invention to provide a shift register circuit having a high bit shift speed and a small number of elements by eliminating the above drawbacks.

[0010]

According to the present invention, there is provided a shift register comprising first and second bit parts for successively latching an input signal and outputting first and second bit outputs, respectively. The bit unit latches the input signal with a clock signal input thereto and outputs a first latch signal, and performs a logical operation of the first latch signal and the clock signal to perform the first operation. A first logic circuit for outputting a bit output signal of the second bit unit, and the second bit unit latches the first latch signal with the clock signal having an opposite phase and outputs a second latch signal. And a second logic circuit that performs a logical operation on the second latch signal and the clock signal and outputs the second bit output signal.

In the present invention, the first and second latch sections include a transfer gate for transferring an input signal, an inverter having an input connected to an output of the transfer gate and outputting a latch signal, and It may include an inverter and a clocked inverter connected in anti-parallel.

Further, according to the present invention, the first logic circuit may be a NOR circuit and the second logic circuit may be an AND circuit.

In the present invention, the first logic circuit may be a NAND circuit and the second logic circuit may be an OR circuit.

[0014]

When the input signal is a positive logic signal, by making the first logic circuit a NOR circuit and the second logic circuit an AND circuit, the first latch signal of the first bit portion is "L". When the level and the clock signal are "L" level, the NOR circuit outputs the first bit output signal, and when the clock signal subsequently becomes "H" level, the AND circuit outputs the second bit output signal.

That is, for each cycle of the clock signal,
The first and second bit output signals are output, resulting in a 2-bit shift, and the shift speed is double that of the conventional one. Furthermore, since a simple logic circuit may be provided instead of the other latch unit for each bit unit, which is conventionally required,
The number of elements can be reduced.

When the input signal is a negative logic signal, a NAND circuit may be used instead of the NOR circuit, and an OR circuit may be used instead of the AND circuit.

Further, the latch section can be easily constituted by a transfer gate, an inverter, and a clocked inverter connected in antiparallel with the inverter.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The shift register circuit 10 of the present embodiment has the same circuit configuration and is configured to transfer the transfer gates TG ₁ and TG ₂ of the latch units 1 and 2 and the clock signals φ ₀ and φ ₁ of the clocked inverters CI ₁ and CI ₂ . Two bit parts 10A whose phases are opposite to each other
And 10B are cascade-connected via the cascade output terminal T _M.

The output terminal T of the bit portion 10A
_A is a latch signal SM of the first latch unit 1 for one input
_The other input of ₁ is used as the output of the NOR circuit NOR connected to the clock signal φ ₀ , and this NOR output signal is used as the first bit output signal S _A.

On the other hand, the output terminal T _B of the bit section 10B is
An AND circuit AN which receives one input terminal from the output terminal of the second latch section 2 and receives the other input terminal from the clock signal φ ₀
The output terminal of D is used as the second bit output signal S _B. Further, an inverter I ₂ for outputting a clock signal phi ₁ receives the clock signal CK, and an inverter I ₃ for outputting a clock signal phi ₀ receives an output of the inverter I _2.

The feature of the present invention is that in FIG. 1, the first bit portion 10A latches the input signal S _I by the input clock signals φ ₀ and φ ₁ , and the first latch signal S 1
The first latch unit 1 that outputs _M and the first latch signal S
The second bit unit 10B includes a NOR circuit NOR as a first logic circuit that performs a NOR operation of _M1 and the clock signal φ ₀ and outputs the first bit output signal S _A.
The first latch signal S _M1 is used as the clock signals φ ₀ , φ of opposite phase.
A second latch unit 2 for outputting a second latch signal S _M2 latched by _1, the second latch signal S _M2 and the clock signal phi ₀ second bit output signal ANDs and S
AND circuit AND as a second logic circuit that outputs _B
Is included.

Next, the operation of this embodiment will be described with reference to the waveform diagrams of the signals at the respective parts in FIG.

When the input signal S _T and the clock signal φ ₀ are input to the shift register circuit 10 of FIG. 1, the input signal S _I is at the “H” level and the clock signal φ ₀ is at the “H” level to the “L” level. At the time point t _{1 at} which the output signal S _A is switched to, the output signal S _A of the bit portion 10A becomes the “H” level.

Next, at time t ₂ , the clock signal φ
_{Since 0} changes from the “L” level to the “H” level, the output signal S _A changes from the “H” level to the “L” level, the output signal S _B of the bit unit 10B changes to “H”, and the next clock signal It continues until time t ₃ when φ ₀ changes.

As described above, in the shift register circuit 10 shown in FIG. 1, not only at the rising time t ₂ of the clock signal φ ₀ but also at the falling time t ₁ , the data is transferred to the upper bits, that is, from the bit portion 10A. It is transmitted to the bit part 10B.

Therefore, by connecting a number of circuits of the shift register circuit 10 in cascade, data is transmitted to the upper bits at the rising and falling edges that occur every half cycle of the clock signal φ ₀ . In comparison with the conventional shift register circuit 30 shown in FIG. 3, the transmission speed is doubled when the clock signal φ _{0 has} the same frequency.

The shift register circuit 10 shown in FIG.
The number of elements per bit is 12 in the bit part 10A.
The number of elements is 14 in the bit unit 10B, and the number of elements can be reduced as compared with 16 in the conventional shift register circuit 30 shown in FIG.

However, the number of elements of the shift register circuit is calculated by assuming that there are two inverters, four clocked inverters, four 2-input NOR circuits, six 2-input AND circuits, and two transfer gates. There is.

In the above embodiment, the input signal is based on the positive logic. However, when the input signal is based on the negative logic, the NOR circuit may be replaced with a NAND circuit and the AND circuit may be replaced with an OR circuit. The operation of.

[0032]

As described above, according to the present invention, since the bit units whose logical output of the output signal of the latch unit and the clock signal are used as the bit output signals are connected in cascade, the input data is stored in the clock. Since 2 bits are shifted in a cycle, there is an effect that the shift speed is doubled.

Further, there is an effect that the number of elements per bit of the shift register circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of signals of respective parts for explaining the operation.

FIG. 3 is a circuit diagram showing an example of a conventional shift register circuit.

FIG. 4 is a waveform diagram of signals of respective parts for explaining the operation.

[Explanation of symbols]

1,2 latch portion 10, 30 shift register circuit 10A, 10B, 30A, 30B bit portion CI _1, CI ₂ clocked inverter CK, φ _0, φ ₁ clock signal I ₁ ~I ₄ inverter S _A, S _B bit output Signal S _I Input signal S _M1 , S _M2 Latch signal T _A , T _B , T _O Output terminal T _I input terminal TG ₁ , TG ₂ Transfer gate T _M Cascade output terminal

Claims (4)

[Claims] 1. A shift register comprising first and second bit parts for successively latching an input signal and outputting first and second bit outputs, respectively, wherein the first bit part outputs the input signal. A first latch unit that latches according to an input clock signal and outputs a first latch signal; and a first latch unit that performs a logical operation of the first latch signal and the clock signal and outputs the first bit output signal. A second logic unit, wherein the second bit unit latches the first latch signal with the clock signal having an opposite phase and outputs a second latch signal; And a second logic circuit for performing a logical operation of the latch signal and the clock signal to output the second bit output signal. 2. The first and second latch units include a transfer gate for transferring an input signal, an inverter having an input connected to an output of the transfer gate and outputting a latch signal, and an anti-parallel circuit for the inverter. The shift register circuit according to claim 1, further comprising a clocked inverter connected thereto. 3. The first logic circuit is a NOR circuit,
The shift register circuit according to claim 1, wherein the second logic circuit is an AND circuit. 4. The shift register circuit according to claim 1, wherein the first logic circuit is a NAND circuit, and the second logic circuit is an OR circuit.