JPH0536268A - Time-division switch - Google Patents

Abstract

PURPOSE:To decrease the switch area of the time-division switch and to reduce the power consumption by constituting a channel memory which constitutes the time-division switch for line switching by using a memory cell composed of a dynamic RAM. CONSTITUTION:A serial data signal from eight bit-multiplexed input lines 1 is converted by a serial-parallel converting circuit 7 into parallel data, which is written in the channel memory 3. In a read cycle, the contents of the channel memory 3 are converted in 8-bit units by a parallel-series converting circuit 8 into serial data according to the order that a control memory 4 specifies and the data is outputted to one of eight output lines 2. Thus, the channel memory which constitutes the time-division switch is composed of the memory cell of the dynamic RAM to decrease the number elements, thereby reducing the power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technique and a technique particularly effective when applied to a data holding circuit. For example, a technique effectively applied to a channel memory of a time division switch composed of a GaAs integrated circuit. Regarding

[0002]

2. Description of the Related Art In a high-speed and high-bandwidth communication network, it is necessary to provide high-speed bearer services such as moving images and high-definition images in addition to telephone calls, and high-speed switches for circuit switching are required to connect and connect these. Being developed. Conventionally, a space division method and a time division method have been considered as a high-speed switch for circuit switching. Among them, a time division high-speed switch and a switching system using the same are, for example, FIG. 3 and FIG. 4 has been proposed (Research Practical Report, Volume 37, No. 12 (1), published by NTT.
988) P821-P830, "Ultra-high-speed time-division switch configuration technology using GaAs devices").

That is, the system shown in FIG. 3 is an example applied to a high-definition TV switching system. The high-definition TV signal is band-compressed to 20 MHz by the TCM encoder T-ENC,
The signal is converted into a 400 Mb / s digital signal by the A / D conversion circuit ADC and sent to the multiplexer MUX. The multiplexer MUX bit-multiplexes the 4-channel digital signals and sends them to the time division switch TSW. The time-division switch TSW has one input / output highway and performs time-division exchange of 4 channels of multiplexed signals. The signal exchanged by the time division switch TSW is the demultiplexer DM.
Separated by UX D / A converter DAC, TCM decoder T
-Reproduced into a high definition TV terminal signal through DEC.

The time divisional switch TSW is, as shown in FIG. 4, an input shift register ISR as a serial-parallel conversion circuit, a data register IDR as a communication channel memory, and an output as a parallel-serial conversion circuit. The shift register OSR and the address shift register ACS as a control memory for designating the output order of the data held in the output shift register OSR and the NOR gate, and decodes the address held in the address shift register ACS It is composed of an address decoder A-DEC.

The input data A, B, C, D taken in the input shift register ISR are collectively latched in the data register IDR, and the address shift register ACS synchronizes with the output channel of the output shift register OSR. The data register ID is shifted to one of the flip-flops of the output shift register OSR.
L bit of 1-bit data is latched. The contents of the address shift register ACS can be rewritten through the flip-flop at the uppermost stage, whereby the output order of data can be changed.

[0006]

In the conventional time divisional switch TSW, the speech path memory has a selection switch MOSFE.
Since it is composed of a RAM or a register composed of 6-element static type memory cells as shown in FIG. 5 composed of T Qs1 and Qs2 and a latch circuit LT,
There are problems in that the number of elements is large, the area occupied by the circuit is large, and the power consumption is large.

An object of the present invention is to provide a time division switch which has a small number of elements, a small chip area, and low power consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the speech path memory that constitutes the time-division switch for circuit switching is configured by the memory cells of the dynamic RAM.

[0009]

According to the above-mentioned means, the memory cell forming the dynamic RAM has the static R as shown in FIG.
The number of elements is extremely smaller than that of the memory cells forming the AM. Moreover, since the speech path memory in the time divisional switch TSW only needs to hold data for an extremely short time, the dynamic RAM is not required to be refreshed and peripheral circuits are not required. Therefore, the chip area of the time divisional switch can be reduced and the power consumption can be reduced.

[0010]

FIG. 1 shows an embodiment in which the present invention is applied to a time divisional switch. Although not particularly limited, the time divisional switch of this embodiment has one GaA.
s formed on a substrate. In FIG. 1, reference numeral 3 denotes a call path memory composed of eight registers or eight memory frames, and reference numeral 4 denotes a control for holding an address for designating an output order of data held in the call path memory 3. Memory 5, 5 is an address decoder for decoding the address held in the control memory 4, and 6 is a control circuit for generating control signals such as synchronization signals.

The time divisional switch of this embodiment is provided with eight bit-multiplexed input lines 1, and a signal input as serial data is converted into parallel data in byte (8 bit) units by a serial-parallel conversion circuit 7. And is written into the speech path memory 3 in the order of input. When the writing is completed, the process shifts to the read cycle, and the contents of the communication path memory 3 are sent to the parallel-serial conversion circuit 8 in units of 8 bits in accordance with the order specified by the control memory 4, and are converted into serial data. Is output to any one of the output lines 2. As a result, the signals input from the eight input lines 1 are
According to the information in the control memory 4, the time sequence is changed and / or the output lines are changed (exchange function).

In this embodiment, the speech path memory 3 is
As shown in FIG. 2, switch MOSFET Q for selection
It is composed of a one-transistor / one-capacitor type memory cell MC consisting of s and an information charge storage capacitance Cm. The channel memory 3 does not require refreshing because the average time required from writing to reading is 300 nsec, which is very short. Therefore, even if the memory cell shown in FIG. 2 is used, a refresh control circuit such as a general dynamic RAM is unnecessary. However, the control memory 4 is
Since the time from writing to reading is on the order of minutes or hours, it is composed of a memory cell for static RAM as shown in FIG.

The time division switch of this embodiment controls the contents of the speech path memory 3 so that the output line can be switched according to the data such as the transfer destination address taken into the speech path memory 3. It is configured to be able to be transferred to the memory 4 for use. Although the eight input lines are provided in the above embodiment, the number of input lines is not limited to this and may be any number.

As described above, in the above embodiment, the speech path memory constituting the time division switch is dynamically RA.
Since the configuration is made up of M memory cells, the number of elements of the communication path memory is much smaller than that of the conventional time divisional switch composed of static RAM memory cells, so the chip area of the time divisional switch is reduced. The power consumption can be reduced as well as the power consumption can be reduced. By the way, the occupied area of the memory cell of the dynamic RAM as shown in FIG.
a [mu] m ^2, since the area occupied by the static memory cell is about 500 [mu] m ^2, the area occupied by the speech path memory becomes about one-half.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, although it has been described in the above embodiment that the time divisional switch is composed of GaAs LSI, it is also possible to apply it to a time divisional switch formed on a silicon substrate.

In the above explanation, the case where the invention made by the present inventor is mainly applied to the time division switch for circuit switching which is the field of application which is the background of the invention has been explained, but the present invention is not limited thereto. Instead, it can be used for general semiconductor integrated circuits including a latch circuit, a register, or a memory that holds data shorter than the refresh time.

[0017]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to realize a high-speed time division switch having a small number of elements, a small chip area, and low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a time divisional switch according to the present invention.

FIG. 2 is a circuit diagram showing a specific example of a cell of a speech path memory that constitutes the time divisional switch of FIG.

FIG. 3 is a block diagram showing a configuration example of a conventional exchange system using a time division high-speed switch.

4 is a circuit configuration diagram of a configuration example of a time divisional switch that constitutes the exchange system of FIG.

5 is a circuit diagram showing a specific example of a cell of a communication path memory which constitutes the time divisional switch of FIG.

[Explanation of symbols]

1 input line 2 output lines 3 speech path memory 7 Series-parallel conversion circuit 8 Parallel-serial conversion circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04Q 11/04

Claims (2)

[Claims] 1. A serial-parallel conversion circuit for converting a serial input signal into parallel data, a speech path memory for temporarily holding the converted input data, and serial data for holding the data held in this speech path memory. To a serial-to-serial conversion circuit for converting and outputting to a control memory, a control memory for designating the order of data output by the parallel-to-serial conversion circuit, and an address held in the control memory to decode the data. A time-division switch composed of a decoder for controlling the order of outputs, wherein the communication path memory is composed of a memory cell of one-transistor / one-capacitor type. 2. The control memory is configured so that input data taken in by a serial-parallel conversion circuit is transferred and the order of data output is controlled based on the data. The time divisional switch according to claim 1.