JPH0535893B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a data transfer system.

[Conventional technology]

The conventional data transfer method is as shown in Figure 3.
Input/output bus I/O, /O and data register DR
Controls the connection of the shift register output signal to the gate input signal of the transfer gate transistor
An AND signal of SRO and transfer gate control signal RE is used, and the data transfer valid period is only when these two signals are both at high potential.

FIG. 4 shows the operation timing of the circuit shown in FIG. The conventional data transfer method will be described below with reference to FIGS. 3 and 4.

In Figure 3, PIO is an input/output bus I/O,
I/O precharge signal, SRO _o is the output signal from the shift register, RE is the transfer gate control signal, AMP is the amplifier, DIN is the external input terminal, DouT is the external output terminal, T ₀₁ , T ₀₂ , Q ₀₁ ~
Q ₀₆ indicates a field effect transistor.

Now, the operation when transferring data from the input/output buses I/O and /O to the data register DR will be explained.

First, the input/output buses I/O, /O are precharged by the precharge signal PIO, and the input signal from the external terminal DIN is amplified by the amplifier AMP and guided to the input/output buses I/O, /O. The input/output buses I/O and /O become high potential and low potential, or low potential and high potential, and hold data.

Next, when the shift register output signal SRO _o and the transfer gate control signal RE become high potential at the same time, the transfer gate transistors T ₀₁ , T ₀₂
becomes active and input/output buses I/O, /O
and data register DR become conductive, and the input/output bus I/
Data in O and /O is transferred to data register DR. The valid data transfer period at this time is _t2 shown in FIG. Here SRO _o , RE, PIO, I/
Since the O and /O signals use an interleaved format, there is one cycle for every two cycles of the basic signal.

[Problem that the invention seeks to solve]

In the conventional method described above, the AND signal of the shift register output signal SRO _o and the transfer gate control signal RE is connected to the transfer gate transistor.
The circuit configuration is input to the gates of T ₀₁ and T ₀₂ ,
Since the transfer control signal RE is activated only for a part of the period when the basic signal is activated, the input/output buses I/O and /O are connected to the data register DR at _t2 shown in FIG. The disadvantage is that the valid period for data transfer is short.

In contrast to the conventional data transfer method described above, the data transfer method of the present invention uses input/output buses I/O, /O
It has the original content of being able to lengthen the valid period of data transfer, which had been a problem when transferring data from to data register DR.

[Means for solving problems]

In a method of interleaving data transfer between a data register and an input/output bus that operate at a cycle several times the cycle of the basic signal, the gate of the transfer gate transistor corresponding to the data register is It is characterized in that it is driven by a signal having a valid time.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is an operation timing chart of the circuit shown in FIG.

In Figure 1, transfer gate transistors T ₀₁ and T ₀₂ are shift register output signals.
It is designed to be driven directly by SRO _o . T ₀₁ , T ₀₂ and Q ₀₄ to _{Q 06} are enhancement type field effect transistors. In addition, although not shown in the figure, multiple data registers and transfer gate transistors are connected to the input/output buses I/O and /O, and data is transferred between the input and output buses I/O and /O in an interleaved manner. Transfer is now possible.

Now, if the data transfer direction is input/output bus I/O,
The case from I/O to data register DR will be explained.

First, the input/output buses I/O, /O are precharged by the precharge signal PIO, and the input signal from the external input terminal DIN is amplified by the amplifier AMP and guided to the input/output buses I/O, /O. As a result, the input/output buses I/O and /O become between a high potential and a low potential, or between a low potential and a high voltage, and hold data.

Next, when the shift register output signal SRO _o becomes high potential, the transfer gate transistor
T ₀₁ and T ₀₂ are activated, and the input/output bus I/O is activated.
O, /O and data register DR are made conductive, and data on input/output buses I/O, /O is transferred to the data register. At this time, the data transfer valid period is _t1 shown in FIG. Here SRO _o , PIO, I/
Since the O and /O signals use an interleave format, there is one cycle for every two cycles of the basic signal.

In the embodiment shown in FIG. 1, a data register DR and a transfer gate transistor T ₀₁ ,
A depletion field effect transistor may be inserted between T ₀₂ to function as a resistance element.

If such a configuration is adopted, the current value in the data transfer path is limited, so power consumption during data transfer can be reduced.

〔Effect of the invention〕

As explained above, the data transfer method of the present invention can extend the effective period of data transfer by using the output signal of the shift register as the gate input signal of the transfer gate transistor between the input/output bus and the data register. effective.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 shows a timing diagram showing the operation of the present embodiment, FIG. 3 shows a circuit diagram of the conventional example, and FIG. 4 shows a timing diagram showing the operation of the conventional example. DR……Data register, I/O, /O……
Input/output bus, DIN...external input terminal, DOT...
External output terminal, SRO _o ...Shift register output signal, RE...Transfer gate control signal,
PIO...precharge signal, AMP...amplifier,
T ₀₁ , T ₀₂ , Q ₀₁ to _{Q 06} ... field effect transistor,
N ₀₁ , N ₀₂ ... Contacts.

Claims (1)

[Claims] 1. In a method in which data is transferred in an interleaved format between a data register and an input/output bus that operate at a cycle several times the cycle of the basic signal, the gate of the transfer gate transistor corresponding to the data register is transferred during one cycle of the basic signal. A data transfer method characterized in that it is driven by a signal having a valid time of minutes.