JPS62299111A - Buffer device - Google Patents

Abstract

PURPOSE:To control the leading/trailing waveform and a transmission delay time of an output optionally by connecting inverters whose input/output response times have a difference in parallel. CONSTITUTION:An input signal from an input terminal 1 is given to the 1st and 2nd transfer gates 2, 3 and its threshold voltage causes a delay in an input/ output response in an output waveform of the 1st and 2nd inverters 4, 5. The leading/trailing of the waveform at an output terminal 6 are controlled by the gate width of the 1st and 2nd inverters 4, 5, and the input/output transmission delay time is controlled by the 1st and 2nd transfer gates 2, 3. The gate width of the 1st and 2nd inverters 4, 5 is selected as 1:2, and the Pch, Nch gate width of the 1st and 2nd transfer gates 2, 3 is selected as 50mum, then the leading/trailing slows down by 1.0 ns in comparison with a conventional circuit and the transmission delay is retarded by nearly 1.0 ns.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a buffer device, and particularly to the configuration of a buffer device in a complementary MO8 integrated circuit.

[Conventional technology]

Conventionally, this type of buffer device is composed of an inverter circuit as shown in FIG. Therefore, the rise and fall of the output waveform and the input/output transmission delay time are determined by the gate width of the MO8I-ra/register that constitutes the inverter.

[Problem that the invention seeks to solve]

Since the above-mentioned conventional buffer device is configured with only an inverter, the rise of the output waveform depends on the gate width of the MOS transistor that constitutes the inverter.9. There is a drawback that there is no degree of freedom in design because the fall time and input/output transmission delay time are determined.

[Means for solving problems]

The buffer device of the present invention has a plurality of pairs of a 14-volt type MO8) transistor and a reverse conductivity type MOS transistor connected between different power supply terminals, and each pair of transistors is connected in parallel, A special embodiment characterized in that a delay circuit is provided between the gates of some of the transistor pairs and the gates of the remaining transistor pairs.Next, the present invention will be described with reference to the drawings. I will explain.

FIG. 1 is an equivalent circuit diagram of a first embodiment of the present invention.

The first and second inverters 4 and 5 each include an N-channel transistor and a P-channel transistor.
The gate of the second inverter 5 is directly connected to the input terminal 1, and the gate of the first inverter 4 is connected to the first and second transfer gates 2, 3t-.
Connect to the input terminal via the A Pf mannel transistor (hereinafter Pc
h) is connected to the output terminal 6, and the Nch and Pch gates of the second transfer gate are connected to the output terminal and the input terminal, respectively.

The outputs of the first and second inverters are both connected to an output terminal.

The input signal from input terminal 1 is input to the first terminal. Through the second transfer gates 2 and 3, the threshold voltage thereof causes a delay in the input/output response of the output waveforms of the first and second inverters. The output terminal 60 waveform at this time is the 1st. The rise and fall times can be controlled by the gate width of the second inverter, and the gate width of the second inverter can be controlled. The input/output transmission delay time can be controlled by the second transfer gate. As a result of the simulation, the gate width of the first and second inverters was set to 1:2, and the Pc11. of the first and second transfer gates was set to 1:2. When the Nch gate width is 50 pm,
Compared to the conventional circuit, the rise time is υ and the fall time is 9. Qns is slow, the transmission delay is about 1. Ons is late.

FIG. 2 is an equivalent circuit diagram of a second embodiment of the present invention. Unlike FIG. 1, a resistor 7 is connected between the input terminal 1 and the gate 40 of the first inverter. The input/output transmission delay time can be controlled by this resistance value. Further, this embodiment has the advantage that the circuit configuration is simple and that it can be easily designed based on the buffer circuit currently in use. Simini V-Sho/
As a result, with a resistance of 500Ω and a gate width ratio of the first and second inverters of 1:2, the startup time was 9. 1 on the falling edge. Qns
One transmission delay resulted in a delay of approximately 1.5 ns.

〔Effect of the invention〕

As explained above, the present invention has the effect of arbitrarily controlling the output rise and fall waveforms and transmission delay time by connecting inverters in parallel with different input and output response times. In particular, one aspect of the present invention is the buffer system I
By installing it in the output stage of C or higher speed IC, it has the effect of solving problems such as ringing due to high drive capacity.

[Brief explanation of the drawing]

Fig. 1 is an equivalent circuit diagram showing a first embodiment of the present invention, Fig. 2 is an equivalent circuit diagram showing a second embodiment of the invention, and Fig. 3 is an equivalent circuit diagram of a conventional buffer device. It is. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...First transfer gate, 3...Second transfer gate, 4...First inverter, 5... ...
...Second inverter, 6... Output terminal, 7.
·····resistance. Agent Patent Attorney Susumu Uchihara Figure 1 Figure 2 Dark Figure 3

Claims (1)

[Claims] It has a plurality of pairs of one conductivity type MOS transistor and opposite conductivity type MOS transistor connected between different power supply terminals, each of the pairs of transistors are connected in parallel, and some of the transistors of the pair of transistors are connected in parallel. A buffer device comprising a delay circuit between the gates of the pair of transistors and the gates of the remaining transistor pairs.