JPH053554A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain images having no blur without increasing the cost of a solid-state image pickup device. CONSTITUTION:When signal read gates for the respective photo-detection sensors of a CCD 11 are simultaneously opened by the control of a CCD driver 15, signal charges are simultaneously read from the respective sensors to a vertical transfer part and outputted through a horizontal transfer part. Thus, the signal charges are read out, passed through a CDS circuit 17 or the like and converted to digital signal trains by an A/D converter 19 while keeping the arrangement of the photodetection sensors, namely, while alternately arranging lines in first and second fields. These signal trains are converted to luminance signals and color difference signals by a signal processing circuit 23 while keeping the arrangement and transferred to a buffer memory 24 while being separated into the first and second fields by a change-over switch. The buffer memory 24 respectively stores the luminance signals and the color difference signals in an interlace system arrangement and further, those signals are recorded in a memory card 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for obtaining an interlaced scanning video signal in, for example, a digital electronic still camera.

[0002]

2. Description of the Related Art In recent years, digital electronic still cameras have been actively developed, and in particular, electronic shutter type electronic still cameras have attracted attention. In this digital electronic still camera, the image can be reproduced on an ordinary TV receiver. On the other hand, since the display of an image on a normal TV receiver is performed by interlaced scanning in which one screen (one frame) is divided into two fields and scanned, the image signal output from the digital electronic still camera is also interlaced scanned. Must be adapted.

Therefore, in a conventional digital electronic still camera, a field accumulation type solid-state image pickup device is used, and one frame screen is divided into two fields for time-division photography, and this is output in an interlace system. Was becoming. However, in this method, since there is a difference of about 1/60 seconds between the shooting times of the video signal of the first field and the video signal of the second field, when a moving subject is shot and played back, Image blurring,
The image is unsightly.

In order to solve this problem, for example, Japanese Patent Laid-Open No.
Japanese Patent Laid-Open No. 4-51776 proposes a method of simultaneously reading out signal charges for one frame from each sensor of a solid-state image sensor to a vertical transfer unit. In this method, the signal charges read simultaneously to the vertical transfer unit are switched at high speed by the first changeover switch to be distributed to the charge accumulation sequence for the first field and the charge accumulation sequence for the second field, and the charge accumulation sequence is further divided into the second field. By switching with the change-over switch of No. 2, the signal arrangement conforming to the interlace system is transferred to the horizontal transfer unit.

According to such a method, there is no time difference between the first field and the second field, and it is possible to prevent image blurring.

[0006]

However, according to this method, the solid-state image pickup device chip is provided with the charge storage columns twice as many as the vertical transfer units and the corresponding additional circuits such as the first and second changeover switches. Since it has to be integrated into the chip, the chip circuit becomes complicated and the chip area also becomes large. Therefore, the cost of the solid-state imaging device chip, which has been a problem in the past, is further increased, and there is a problem in mounting.

Therefore, there is a problem that the above problems must be solved.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a solid-state image pickup device capable of obtaining an image without blurring without increasing the cost of the solid-state image pickup element. ..

[0009]

A solid-state image pickup device according to the present invention includes a plurality of light-receiving sensors arranged in a matrix for accumulating a number of signal charges corresponding to the number of pixels of one frame screen, and each light-receiving sensor. Discharging means for simultaneously discharging the accumulated charges, a vertical transfer portion for accumulating signal charges for one frame pixel and vertically transferring the signal charges, and simultaneously reading out the signal charges accumulated in each light receiving sensor to the vertical transfer portion. A read gate, a horizontal transfer unit that horizontally transfers the signal charges transferred from the vertical transfer unit, an analog-digital converter that converts the signal charges transferred from the horizontal transfer unit into a digital signal, and this analog-digital converter And a rearrangement unit for rearranging the digital signal sequence converted by.

[0010]

According to the present invention, the image signals for one frame are simultaneously read from the solid-state image pickup device to eliminate the time difference between the first field and the second field, and the read signal train is processed by the processing circuit in the subsequent stage to the first field and the first field. The signal sequence is divided into two field signal sequences and converted into a signal sequence having an array suitable for the interlace system.

[0011]

EXAMPLES Examples will be described below with reference to the drawings.

FIG. 1 shows a digital electronic still camera to which a solid-state image pickup device according to an embodiment of the present invention is applied. Here, first, the outline of the configuration and operation of the entire apparatus will be described, and then the operation of each unit will be described in detail.

Configuration and Operation of Entire Device This device includes a CCD (Charge Coupled Device) 1 as a solid-state image pickup device.
1 is provided, and a subject image condensed by the taking lens 12 is formed on an image sensor constituting the image sensor 1. A diaphragm 13 is provided between the taking lens 12 and the CCD 11, and is driven by a diaphragm driving circuit 14. CCD 11 is CCD driver 15
The analog video signal is output based on the drive signal from the. At this time, as will be described later, the analog video signals output from the CCD 11 are output not in the so-called interlace system but in the order according to the geometrical arrangement of the subject image.

The CCD driver 15 outputs a drive signal in synchronization with the timing signal supplied from the timing generator 16.

The analog video signal output from the CCD 11 is correlated double sampling (CDS).
uble Sampling) circuit 17 performs correlated double sampling to remove reset noise, and then automatic gain control (A
It is amplified to a predetermined level by a GC: Automatic Gain Control (GC) circuit 18, and is converted into an analog-digital (A / D) converter 19
Entered in. The correlated double sampling circuit 17,
The automatic gain control circuit 18 and the A / D converter 19 operate based on the timing signal supplied from the timing generator 16.

The A / D converter 19 quantizes the inputted analog signal into 256 gradations and converts it into a digital signal having an 8-bit width and supplies it to the signal processing circuit 23. The signal processing circuit 23 converts the supplied digital signal into a luminance signal Y and color difference signals RY and BY by performing a predetermined calculation. Then, these luminance signal Y and color difference signals RY, B
-Y is temporarily stored in the buffer memory 24 and then sequentially recorded in the memory card 25.

The central processing unit (CPU) 26 controls circuits such as the diaphragm drive circuit 14, the correlated double sampling circuit 17, the automatic gain control circuit 18, the timing generator 16, the signal processing circuit 23, and the buffer memory 24. Is supposed to work under.

Next, the structure and operation of the CCD 11 will be described in detail.

Description of Configuration and Operation of CCD 11 FIGS. 2 and 3 show the schematic configuration and operation of the CCD 11, respectively. The CCD 11 has a number of light receiving sensors 31, 3 corresponding to the number of pixels of the frame screen.
2 are arranged in a matrix. These light receiving sensors are composed of photodiodes. Among them, the light receiving sensor 31 stores the signal charge corresponding to the first field of the frame scanning, and the light receiving sensor 32 stores the signal charge corresponding to the second field.
On the front surface of these light receiving sensors, for example, G vertical stripes, R and B checkered color filters for obtaining the G, R and B primary color luminance signals are arranged as shown in the figure.

A signal read gate (readout gate) 34 is provided between each light receiving sensor and the vertical transfer unit 33. These signal read gates 34 are
The gates are opened all together at the timing of the read pulse (FIG. 5c) input from the D driver 15 (FIG. 1), and the signal charges accumulated in the light receiving sensors 31 and 32 are transferred to the vertical transfer unit 33. There is.

The signal charges transferred to the vertical transfer unit 33 are
Vertical drive pulse φV supplied from CCD driver 15
_The signals are sequentially transferred in the vertical direction (downward in the figure) by _{1 to} φV ₃ and enter the horizontal transfer unit 35. The signal charges that have entered the horizontal transfer unit 35 are further sequentially transferred in the horizontal direction (left side in the drawing) by the horizontal drive pulses φH ₂ and φH ₂ supplied from the CCD driver 15, and are passed through the floating diffusion amplifier 36. Correlation double sampling circuit 17
(Fig. 1).

The operation of the CCD 11 having the above configuration will be described with reference to FIGS. 3, 4 and 5.

FIG. 3A is a sectional view showing the structure of the CCD 11 in detail, and FIG. 3B is a potential diagram corresponding to each part. 4A is a plan view showing the structure of the CCD 11 in detail, and FIG. 4B is a potential diagram corresponding to each part of FIG. 4A. FIG. 5 shows the operation timing of the CCD 11.

As shown in FIG. 3A, this CCD has a so-called vertical overflow drain structure that discharges excess charges in the depth direction of the image pickup device chip.

When the release button for starting photographing is operated, surplus charges in the CCD 11 are first swept away. That is, the timing generator 16 (FIG. 1) to which the vertical synchronizing signal as shown in FIG. 5A is given gives the first read pulse P _R1 (FIG. 1C) to the CCD driver 15. At this timing, the CCD driver 15 sets the CCD
A high-speed charge sweep pulse P _S as shown in FIG. This charge sweep pulse P _S is the CCD
It is applied to the substrate 42 via 11 substrate terminals 41 (FIG. 3A). As a result, the overdrain voltage changes from V _a to V _b and the channel stopper 44
The barrier potential becomes low, and the surplus charges 43 (FIGS. 3B and 5d) accumulated in the light receiving sensor 31 and the like are immediately discharged to the substrate 42. These surplus charges are charges accumulated in the light receiving sensor 31 or the like by the light input during non-photographing or remaining in the previous signal charge reading.

In this embodiment, by adopting such a vertical overflow drain structure, the excess charges of each light receiving sensor are swept away in parallel in the substrate (substrate) direction, so that high-speed initialization is possible. ..

The charge sweep pulse P _S is applied from the end of the blanking period T _VB of the vertical synchronizing signal to the horizontal blanking period, and the accumulated charge of each light receiving sensor is discharged each time. The state of the accumulated charge of each light receiving sensor during this period changes in a sawtooth manner as shown in the state A of FIG.

When the electric charge sweeping pulse P _S is stopped at time t ₁ , from this time point until the second read pulse P _R2 is input (hereinafter referred to as signal charge accumulation time), each light receiving sensor is exposed. Accumulates signal charges proportional to the intensity of incident light.

When the time T _V (1/30 second) for one frame has passed and the next vertical synchronizing signal arrives, the timing generator 16 outputs a second read pulse P _R2 to the CCD driver 15. As a result, the potential barrier of the signal read gate 34 in FIG. 4B is lowered, and the signal charge 48 accumulated in all the light receiving sensors 31 and 32 is reduced.
Are simultaneously transferred to the vertical transfer register 47 which constitutes the vertical transfer unit 33 (FIG. 2). Then, as described above, the signal charge transferred to each vertical transfer register 47 is
Sequentially horizontal transfer section by a vertical driving pulse φV ₁ ~φV _{3 3}
5 and further sequentially transferred in the horizontal direction by the horizontal drive pulses φH ₁ and φH _{2 and} output from the imager via the floating diffusion amplifier 36 (FIG. 5e).
Will be output as.

Here, the vertical transfer unit 33 in the present embodiment.
Of the vertical drive pulse φ.
It is a three-phase drive with V _{1 to} φV ₃ . This is 3
This is because the phase drive prevents the admixture of adjacent signal charges in the vertical transfer unit 33. That is,
In this embodiment, the signal charges are transferred from all the light receiving sensors 31 and 32 to the corresponding vertical register 47 of the vertical transfer unit 33 all at once. Therefore, signal charges are stored in every two vertical registers 47. When the signal charge is transferred, the energy barrier between the vertical register 47 below which the charge is stored and the vertical register 47 below is lowered, and the signal charge is transferred to the vertical register 47 one below. At the time of this transfer, one vertical register 47 not involved in the transfer is interposed between two vertical registers 47 involved in the transfer. Therefore, it is possible to prevent adjacent signal charges from being mixed during vertical transfer.

In the above control, the charge sweep pulse P _S
From the stop time t ₁ to the second read pulse P _R2 , that is, if the signal charge storage time T _INT is changed according to the illuminance of the subject, an appropriate exposure time can be obtained. A shutter is realized. According to this control method, in principle, the shutter time control from the period 1/30 sec of the vertical synchronizing signal to the period 1/157550 sec of the horizontal synchronizing signal becomes possible purely electronically.

In this way, all the light receiving sensors 31, 3
Since the reading of the signal charge from 2 is performed at the same timing, the analog signal output from the CCD 11 is as shown in FIG.
As shown in, the signal for the first field and the signal for the second field alternate by one line. Therefore, the signal processing circuit 23 of FIG. 1 does not use the interlace method in which the signal of the first field continues for a predetermined line and then the signal of the second field continues for a predetermined line. In this order, the signal of the first field and the signal of the second field are alternately input line by line. The operation of the signal processing circuit 23 will be described below.

Description of Configuration and Operation of Signal Processing Circuit 23 FIG. 7 shows the signal processing circuit 23 and the buffer memory 24 in detail. The circuit is provided with an input terminal 51 for inputting an 8-bit width digital signal from the A / D converter 19 (FIG. 1), and a 1-line delay for delaying a digital signal for 1 line of horizontal scanning. Buffer 5
2, connected to a second 1-pixel delay buffer 53 that delays a digital signal for 1 pixel, and a fourth input terminal I ₄ of the matrix circuit 55. This matrix circuit 5
As will be described later, reference numeral 5 denotes signals Y _L , Y _H , and a signal (R−Y) _H , based on the A / D-converted digital signals of R, G, and B output from the light receiving sensors of the CCD 11. (B-
Y) It is designed to calculate _H.

The output side of the 1-line delay buffer 52 is branched into two, which are respectively connected to the first 1-pixel delay buffer 54 and the second input terminal I ₂ of the matrix circuit 55. First and second 1-pixel delay buffers 54, 53
The output side of is connected to the first input terminal I ₁ and the third input terminal I ₃ of the matrix circuit 55, respectively.

The first output terminal O of the matrix circuit 55
₁ is connected to a subtractor 57, and further connected to an adder 59 via a low pass filter (LPF) 58. The second output terminal O ₂ of the matrix circuit 55 is connected to the adder 59 and the subtractor 57. Adder 5
The output side of 9 is connected to the first switch 61.

Third output terminal O of matrix circuit 55
₃ and the fourth output terminal O ₄ are connected to the second and third switching devices 64, 64 via low-pass filters 62, 63, respectively.
Connected to 65.

The first switch 61 has two output contacts a and b.
, And selectively switches between the common contact c. These output contacts a and b are respectively connected to the first field video memory 67 and the second field video memory 68 provided in the buffer memory 24. Similarly, the output contacts a and b of the second switch 64 are connected to the first field video memory 71 and the second field video memory 72, respectively, and the output contacts a and b of the third switch 65 are connected. Are respectively connected to the first field video memory 73 and the second field video memory 74. The output sides of these video memories are circuits 75 to 77, respectively.
Are connected to the output terminals 81 to 83 via.

The pixel data is converted into a signal corresponding to a luminance signal and a color difference signal by a matrix circuit. As will be described later, the Y _L signal which is an output signal thereof is a low band luminance having a low frequency component in the image. It mainly contains signals.

On the other hand, the Y _H signal contains a wide range luminance signal having a high frequency component in the image.

As will be described later, the Y _H signal is subtracted from the Y _L signal (same function as adding by changing the 180 ° phase of the Y _H signal) and is represented by the following equation.

Low frequency component of (Y _L −Y _H ) = Low frequency component of Y _L −Low frequency component of Y _H Among these, the low frequency component of YL indicates a low frequency luminance signal component and is proportional to the luminance of the object. Represents a luminance signal to be displayed.

That is, Y = 0.30R + 0.59G + 0.11B is shown.

[0043] When adding the low-frequency component and a Y _H signal of the signal, that is (Y _L -Y _H), the low-frequency component of the Y _H Y-phase and the low frequency component of the _H signal is the same amplitude with 180 ° Therefore, they cancel each other out.

Therefore, the output is the output signal of the adding circuit,
That is, the Y signal becomes a composite signal of the low frequency component of the Y _L signal and the wide frequency component of the Y _H signal.

The wide area component of the Y _H signal represents a high spatial frequency component such as a detail of the subject. Such signal processing has an effect of suppressing a false color signal generated due to a difference in the resolution of the green component G and the respective resolutions of the red component R and the blue component B.

The operations of the signal processing circuit 23 and the buffer memory 24 having the above configurations will be described. Here, the first
The luminance signal and the color difference signal corresponding to the first line of the field are obtained from the primary color signals of the line pair 84 in FIG. 6, and the luminance signal and the color difference signal corresponding to the first line of the second field are the primary colors of the line pair 85. Obtain from the signal. Similarly, a luminance signal and a color difference signal corresponding to the second line of the first field are obtained from the line pair 86, and a luminance signal and a color difference signal corresponding to the second line of the second field are obtained from the line pair 87. The same applies to combinations after the third line.

Now, at the input terminal 51 of the signal processing circuit 23 (FIG. 7), the data of the first line of the first field shown in FIG. 6 is synchronized with the clock signal (not shown) G ₁₁ and R.
₁₁ , G ₁₁ , B ₁₁ , ... are input in this order, and then the data of the first line of the second field is G ₂₁ , R ₂₁ , G ₂₁ , B ₂₁ ,
Entered in the order of ……. Here, the four data G ₁₁ , R
Focusing on the data set 88 consisting of ₁₁ , G ₂₁ , and B ₂₁ , these data are phase-aligned by the 1-line delay buffer 52 and the first and second 1-pixel delay buffers 54 and 53, and the matrix circuit 55. Input terminal I ₁
Are input to I ₄ at the same time. The matrix circuit 55 performs the following calculations on these data.

Generally, the relationship between the primary color signals (R, G, B) and the luminance signal Y is given by the following equation (1).

Y = 0.3R + 0.59G + 0.11B (1) The data set 88 is substituted into the following equation (2) which is a modification of the data set 88.

Y = 0.3 (R−G) +0.11 (B−G) + G (2) As a result, the following formula (3) is obtained.

Y _L = 0.3 (R ₁₁ −G ₁₁ ) +0.11 (B ₂₁ −G ₂₁ ) + G ₁₁ (3) On the other hand, the average value of each light receiving sensor is given by the following equation (4). Be done.

Y _H = (G ₁₁ + R ₁₁ + G ₂₁ + B ₂₁ ) / 4 (4) Generally, the primary color signals (R, G, B) and the color difference signal RY
The relationship between and is given by the following equation (5).

RY = 0.7R-0.59G-0.11B (5) The data set 88 is substituted into the following equation (6) which is a modification of this.

RY = 0.7 (R−G) −0.11 (B−G) (6) From this, the following formula (7) is obtained.

(R−Y) _H = 0.7 (R ₁₁ −G ₁₁ ) −0.11 (B ₂₁ −G ₂₁ ) ... (7) Further, in general, the primary color signals (R, G, B) and Color difference signal B-
The relationship with Y is given by the following equation (8).

B−Y = −0.3R−0.59G + 0.89B (8) The data set 88 is substituted into the following equation (9) which is a modification of the data set 88.

B−Y = −0.3 (R−G) +0.89 (B−G) (9) From this, the following formula (10) is obtained.

(B−Y) _H = −0.3 (R ₁₁ −G ₁₁ ) +0.89 (B ₂₁ −G ₂₁ ) ... (10) The signals Y _L , Y _H and the signal thus obtained (R
_{-Y) H, (B-Y} ) H are outputted from the first to fourth output terminals O ₁ ~ O ₄ matrix circuit 55.

Of these signals, the signals Y _L and Y _H are input to the subtractor 57 and output as signals having frequency characteristics as shown in FIG. 8 (A). Furthermore, this signal is a low pass filter 5
The high frequency band is cut by 8 to obtain the frequency characteristic as shown in FIG. 8B, which is input to the adder 59. This signal is added by the adder 59 to the luminance signal Y _H from the _second output terminal O ₂ of the matrix circuit 55. As a result, the low frequency band of the Y _H signal is canceled out, and the low frequency band of Y _L and the high frequency band of Y _H are combined, as shown in FIG.
The luminance signal Y having the frequency characteristic as shown in (D) is input to the first switch 61.

The arithmetic processing as described above is also performed on the next data set 89 in FIG. 6, and the obtained luminance signal Y is input to the first switch 61. In the same manner, the data sets are sequentially selected and processed in the horizontal direction of the line pair 84.

During the horizontal scanning period corresponding to the line pair 84 in FIG. 6, the common contact c of the first switch 61 is switched to the contact a side. As a result, the luminance signal corresponding to the first line of the first field generated from the line pair 84 is stored in the first field video memory 67.

Similarly, the luminance signal corresponding to the first line of the second field is obtained from the line pair 85 and input to the first switch 61, but during the horizontal scanning period, the first
The common contact c of the switch 61 is switched to the contact b side, and the luminance signal corresponding to the first line of the second field is stored in the second field video memory 68.

Thus, as shown in FIG. 9, the first field video memory 67 and the second field video memory 68 store the line data of the first field and the second field for one frame, respectively. Become.

On the other hand, the third and fourth matrix circuits 55
The output terminals O _3, output from the O ₄ (R-Y) _H signal and (B-Y) _H signal, respectively, the high frequency is cut by the low-pass filter 62 and 63, the color difference signals R
-Y and BY signals as second and third switch 6
4, 65 are input.

Of these, the second switching device 64 is arranged so that the luminance signal Y
In the same manner as in the above case, the color difference signal RY in which the first field and the second field are alternately arranged one line at a time is divided and the color difference signal of the first field is stored in the video memory 71.
Then, the color difference signal of the second field is stored in the video memory 72. As a result, as shown in FIG. 10, the video memories 71 and 72 store the color difference signals RY of the first field and the second field for one frame, respectively.

Similarly, the third switch 65 separates the color difference signal BY in the state where the first field and the second field are alternately arranged by one line, and separates the color difference signal of the first field from the video memory 73. Then, the color difference signal of the second field is stored in the video memory 74.

As a result, as shown in FIG. 11, the color difference signals BY of the first field and the second field are stored in the video memories 73 and 74 for one frame, respectively.

In this way, the luminance signal Y stored in the video memories 67 and 68, the color difference signal RY stored in the video memories 71 and 72, and the video memories 73 and 74.
The color difference signals BY stored in the memory card are read out via the memory path control circuits 75 to 77 and the output terminals 81 to 83 under the control of the CPU 26, respectively, and the memory card is kept in the arrangement shown in FIGS. 9 to 11. It is recorded in a predetermined area of 25 (FIG. 1).

When the thus recorded memory card 25 is set in a reproducing device (not shown) and a predetermined operation is performed, the reproducing device performs the normal interline scanning to obtain the brightness recorded in the memory card 25. The signals and the color difference signals are read out simultaneously, and the image of the subject obtained from the CCD 11 (FIG. 1) is displayed on the display screen. There is no blur in this reproduced image.

In the above description, the first and third input terminals I ₁ , I of the matrix circuit 55 (FIG. 7) are used.
₃ is always the primary color signals G ₁₁ and G ₂₁ during one horizontal period.
Is given, the second and fourth input terminals I ₂ ,
As shown below, R and B are alternately applied to I ₄ within one horizontal period.

I ₂ : R ₁₁ , B ₁₁ , R ₁₁ , B ₁₁ ,
_{R 11, ...... I 4: B} 21, R 21, B 21, R 21, B 21, ...... Thus, the inner matrix circuit 55 is provided a switching circuit which operates in synchronization with the input clock, input terminal I ₂ , I
_The signals input from ₄ are alternately divided and input to an arithmetic circuit (not shown). As a result, the arithmetic circuit can accurately execute the arithmetic operations of the expressions (3), (4), (7) and (10) without exchanging data.

[0072]

As described above, according to the present invention, the image signals for one frame are simultaneously read from the solid-state image pickup device to eliminate the time difference between the first field and the second field, and the read signal sequence is output to the subsequent stage. The processing circuit described above divides the signal sequence into the signal sequence of the first field and the second field and converts the signal sequence into the signal sequence of the array conforming to the interlace system. Therefore, the interlace array conventionally provided in the solid-state imaging device is used. A conversion circuit for Therefore, there is an effect that the structure of the solid-state image pickup device can be simplified, the chip can be made small, and the cost can be largely reduced. Further, according to the present invention, the unnecessary charges accumulated in the respective light receiving sensors of the solid-state image sensor are simultaneously discharged to the discharging portion, so that there is an effect that the processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital electronic still camera to which a solid-state imaging device according to an embodiment of the present invention is applied.

2 is a CC of the digital electronic still camera of FIG.
It is a block diagram which shows the structure of D.

FIG. 3 is a sectional view showing the structure of a CCD in detail and a potential diagram corresponding to each part.

FIG. 4 is a plan view showing the structure of a CCD in detail and a potential diagram corresponding to each part.

FIG. 5 is a timing chart for explaining the operation of the CCD.

FIG. 6 is an explanatory diagram showing an array of primary color signals output from a CCD.

7 is a block diagram showing in detail a signal processing circuit in the digital electronic still camera of FIG.

8 is a characteristic diagram showing characteristics of various signals in the signal processing circuit of FIG.

9 is an explanatory diagram showing contents of a video memory for a luminance signal Y in a buffer memory in the digital electronic still camera of FIG.

FIG. 10 is an explanatory diagram showing contents of a video memory for color difference signals RY in this buffer memory.

FIG. 11 is an explanatory diagram showing contents of a video memory for color difference signals BY in the buffer memory.

[Explanation of symbols]

11 CCD 12 Photographing Lens 15 CCD Driver 19 A / D Converter 23 Signal Processing Circuit 24 Buffer Memory 25 Memory Card 26 CPU 31 First Field Light-Reception Sensor 32 Second Field Light-Reception Sensor 33 Vertical Transfer Section 34 Signal Readout Gate 35 Horizontal Transfer unit 52 1-line delay buffer 53 Second 1-pixel delay buffer 54 First 1-pixel delay buffer 55 Matrix circuit 61 First switch 64 Second switch 65 Third switch 67 First field video Memory (for luminance signal Y) 68 Video memory for second field (for luminance signal Y) 71 Video memory for first field (color difference signal RY
72 Video memory for second field (color difference signal RY
73 Video memory for the first field (color difference signal BY
74 Video memory for second field (color difference signal BY)
for)

Claims (1)

Claim: What is claimed is: 1. A plurality of light receiving sensors arranged in a matrix for storing a number of signal charges corresponding to the number of pixels of one frame screen, and the charges accumulated in each light receiving sensor are discharged at the same time. And a vertical transfer unit that stores the signal charges for one frame pixel and vertically transfers the signal charges, a read gate that simultaneously reads out the signal charges accumulated in each light receiving sensor to the vertical transfer unit, and a vertical transfer unit. From the horizontal transfer section that transfers the signal charge transferred from the horizontal direction, an analog-digital converter that converts the signal charge transferred from the horizontal transfer section to a digital signal, and a digital signal string converted by this analog-digital converter And a rearrangement unit that rearranges the solid-state image pickup device.