JPH0535375A - Low energy consumption device for lsi - Google Patents

Abstract

PURPOSE:To suppress energy consumption to a minimum when providing a switch for setting a mode at an LSI concerning the low energy consumption device for the LSI to reduce the energy consumption of the LSI. CONSTITUTION:This device is equipped with an LSI 3 provided with an inside register 1, to which a mode setting signal is inputted, and an input buffer 2 with a pull-up resistor for inputting the mode setting signal to the inside register 1, switch 4 for setting the mode to control the mode setting signal, and output buffer 5 to output a signal at a high level to the switch 4 for setting the mode normally so that a current can flow to the switch 4 for setting the mode only when the mode setting signal of the inside register 1 is read by a CPU, and to output a signal at a low level to the switch 4 for setting the mode only when the mode setting signal of the inside register 1 is read by the CPU.

Description

Detailed Description of the Invention

[0001]

This invention relates to an LSI (Large)
Scale Integrated circuit
(t: large-scale integrated circuit) The present invention relates to a low power consumption device for an LSI, in which the current of a mode setting switch is controlled by an output signal of the LSI to reduce the power consumption of the LSI.

[0002]

2. Description of the Related Art Miniaturization of computer systems in recent years,
With the demand for lighter weight, lower power consumption of LSI is required. Therefore, the power consumption of the LSI itself has been reduced.
Regardless of the state, the current always flows, which hinders low power consumption. Therefore, it is necessary to control the current of the mode setting switch by the LSI.

[0003]

That is, the conventional LS
In I, since the current is always passed through the mode setting switch, even if the LSI is designed to have low power consumption,
Power is consumed at the mode setting switch.

FIG. 3 is a structural explanatory view showing the structure of a mode setting switch used in a conventional LSI, and in FIG.
1 is an LSI, 32 is an input buffer with a pull-up resistor,
Reference numeral 33 is an internal register, and 34 is a mode setting switch. As shown in this figure, in the conventional mode setting switch 34, current always flows where the mode setting switch 34 is turned on. Therefore,
In spite of using an LSI with low power consumption, there is a problem that the mode setting switch 34 consumes more power than necessary in practice.

The present invention has been made in consideration of such circumstances, and an object thereof is to minimize power consumption when a mode setting switch is provided in an LSI.

[0006]

FIG. 1 is a diagram for explaining the principle of the present invention. As shown in the figure, a low power consumption device for an LSI according to the present invention is provided with an input port and a C
An internal register 1 to which the mode setting signal read by the PU is input, and an input buffer 2 with a pull-up resistor that inputs the mode setting signal to the input port of the internal register 1.
And a mode setting switch 4 for controlling a mode setting signal input from the input buffer 2 with a pull-up resistor to the input port of the internal register 1, and the mode setting signal of the internal register 1 is read by the CPU. When the mode setting signal of the internal register 1 is not read by the CPU, a high level signal is output to the mode setting switch 4 so that the current flows only in the mode setting switch 4, and the mode setting signal of the internal register 1 is output. Is read by the CPU, the output buffer 5 outputs a low level signal to the mode setting switch 4.

[0007]

According to the present invention, since a high level signal is normally output from the output buffer 5 to the mode setting switch 4, even if the mode setting switch 4 is on, the input buffer with pull-up resistor is provided. 2 does not flow in the mode setting switch 4 and only when a low level signal is output from the output buffer 5 to the mode setting switch 4, the mode setting switch 4 is connected to the mode setting switch 4 with the pull-up resistor for mode setting. A current flows through the switch 4 to the output buffer 5 side.

Therefore, even if the mode setting switch 4 is used, the power consumption of the LSI 3 can be minimized.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. The present invention is not limited to this.

FIG. 2 is a structural explanatory view showing the structure of an embodiment of the present invention, and shows a device in which a CPU (Central Micro Processing Unit) reads the contents of a mode setting switch of an LSI. In the figure, 10 is an LSI,
11 is an input buffer with a pull-up resistor, 12 is an output buffer, 13 is an internal register, 14 is an address decoder, 15 is an input / output buffer, 16 is a mode setting switch, 17 is an access signal line, 18 is a CPU, and 19 is data. A bus, 20 is an R / W (read / write) signal line, and 21 is an address bus.

The internal register 13 has an input port, and a mode setting signal read by the CPU 18 is input from the input port. The input buffer 11 with a pull-up resistor inputs a mode setting signal to the input port of the internal register 13 with a voltage of 5V.

The mode setting switch 16 controls the mode setting signal input from the input buffer 11 with pull-up resistor to the input port of the internal register 13.

The output buffer 12 outputs a high level signal to the mode setting switch 16 when the mode setting signal of the internal register 13 is not read by the CPU 18, and the mode setting signal of the internal register 13 is output to the CPU.
When it is read by 18, the low level signal is output to the mode setting switch 16 so that the current flows through the mode setting switch 16 only when the mode setting signal of the internal register 13 is read by the CPU 18. To

The operation in such a configuration will be described below. The CPU 18 reads the contents of the mode setting switch 16 from the LSI 10 in order to read the contents of the R / W signal line 2
An R / W signal and an address signal are output via 0 and the address bus 21, respectively. The LSI 10 uses the address decoder 14 to generate and output an access signal (asserted at the'L 'level).

This access signal causes a current to flow in the mode setting switch 16, and at the same time, the input / output buffer 15 is opened to output the state of the switch on the data bus 19, and the CPU 18 reads the contents of the mode setting switch 16. You can lead.

At this time, the access signal is shared by both the current control signal of the mode setting switch 16 and the read signal of the data bus 19, so that the circuit can be downsized. .. Further, in order to reduce the pulse width of the access signal to the minimum, the pulse width of the access signal is set to be the same as the pulse width of the read signal, so that the power consumption of the LSI 10 can be further reduced.

[0017]

As described above, according to the present invention, L
Even if a mode setting switch is used for SI, current does not normally flow, and when the CPU comes to read the contents of the mode setting switch, the current is made to flow for only a short time, so the LSI consumes less power. It is effective in reducing power consumption and largely contributes to reduction in power consumption of computer systems.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a structural explanatory view showing the structure of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a configuration of a conventional technique.

[Explanation of symbols]

 10 LSI 11 Input Buffer with Pull-up Resistor 12 Output Buffer 13 Internal Register 14 Address Decoder 15 Input / Output Buffer 16 Mode Setting Switch 17 Access Signal Line 18 CPU 19 Data Bus 20 R / W Signal Line 21 Address Bus

Claims (1)

Claim: What is claimed is: 1. An input port is provided, and C is provided from the input port.
An LSI (3) having an internal register (1) to which a mode setting signal read by a PU is input, and an input buffer (2) with a pull-up resistor that inputs the mode setting signal to an input port of the internal register (1) And a mode setting switch (4) for controlling the mode setting signal input from the input buffer with pull-up resistor (2) to the input port of the internal register (1), and the mode setting signal of the internal register (1) is the CPU. A high level signal is output to the mode setting switch (4) when the mode setting signal of the internal register (1) is not read by the CPU so that the current flows through the mode setting switch (4) only when it is read by the CPU. When the mode setting signal of the internal register (1) is read by the CPU, the mode setting switch (4) is set. An output buffer for outputting a signal Reberu (5), consisting comprise L
SI low power consumption device.