JPH0535219A - Multi-bit driving semiconductor and semiconductor device for display driving - Google Patents

Abstract

PURPOSE:To realize a small-sized display substrate which is packaged in high density by increasing the degree of freedom of wiring on the substrate and realizing more efficient arranged as to the multi-bit driving semiconductor device which drives a liquid crystal display, etc. CONSTITUTION:As for the driver IC1 for the liquid crystal display, a shift register 11 which converts a scanning signal Dc into a parallel signal is divided into two bilateral shift registers 31a and 31b and a control circuit part 40 which selects their transfer directions and input signals is provided. This IC 1 changes the transfer direction of a scanning signal according to the combination of select signals SC1 and SC2 to increase the degree of freedom of wiring for connecting the scanning signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-bit drive semiconductor device having a function of converting serially input serial signals into parallel to output them in parallel, and particularly used for a liquid crystal display, a plasma display, a printer and the like. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art FIG. 7 shows an outline of a drive circuit for a general liquid crystal panel. The liquid crystal panel 2 shown here uses 5 × 8 dots (1 dot out of 8 dots is a cursor) to display one character, and can display a total of 20 digits × 2 lines. That is, this panel 2 has 10
A liquid crystal panel of 0 × 16 dots, a segment control signal 5 for controlling horizontal dots arranged from left to right in the drawing, and a scan control signal for controlling vertical dots arranged from top to bottom in the drawing. Controlled by 4. The segment control signal 5 and the scan control signal 4 are supplied from the control driver IC1, and the segment output terminals S1 to S100 of the driver IC1 and the segment input terminals SEG1 to SEG100 of the panel 2 are connected to each other. . Also, the scan output terminal C1 of the driver IC1
To C16 and the scan input terminals COM1 to COM of the panel 2
16 are also connected to each.

In the driver IC 1, a scanning signal Dc for controlling vertical bits is input to the shift register 11 as a serial serial signal. Then, in the shift register 11, the serial scanning signals are converted into parallel signals so as to become parallel signals for each bit. The parallel-converted scan signal is synchronized in the latch circuit 12 and selected by the selection switch 13.
Scan output terminals C1 to C converted into a voltage according to the selection
16 is output. Similarly to the above, the segment signal Ds is also parallel-converted by the shift register 14, then synchronized by the latch circuit 15, voltage-converted by the selection switch 16, and the segment output terminal S
Appears in 1 to S100.

FIG. 8 shows the driver IC 1 shown in FIG.
An outline of mounting the liquid crystal panel 2 on a printed circuit board 20 is shown. The driver IC 1 used for mounting has a substantially rectangular shape,
It is mounted on the substrate 20 using the carrier film 17. The segment output terminals S1 to S100 for outputting the segment signals are arranged in a line on one of the long sides 17a of the film 17, and the scan output terminals C1 to C16 for outputting the scanning signals are arranged on the other one of the long sides 17b. Lined up. Two
The liquid crystal panel 2 that displays 0 columns x 2 rows is also a substantially rectangular shape,
On one of the long sides 18a, scan input terminals COM1 to COM8 to which the scan signals of the first row are input are arranged in a line. Then, on the other long side 18b, segment input terminals SEG1 to SEG100 to which a segment signal is input are input.
And a scan input terminal CO to which the scan signal of the second row is input.
M9 to COM16 are arranged in a line. These terminals are the segment output terminals S1 to S100 and the segment input terminals SEG1 to SE prepared on the printed circuit board 20.
Segment signal wiring 21 for connecting G100, scan output terminals C1 to C8 and input terminals COM1 to COM8 of the first row
Are connected to each other by a first scanning signal wiring 22 which connects the scanning output terminals C9 to C16 of the second row and a second scanning signal wiring 23 which connects the input terminals COM9 to COM16.

[0005]

When arranging the liquid crystal panel 2 and the driver IC 1, it is necessary to design the signal wirings 21, 22 and 23 so as to be compact and not to have a complicated arrangement. This is important in reducing and reducing the area of the substrate 20 to produce a small-sized and high-density liquid crystal module. For this reason, it is general that the layout design is performed centering on the segment signal wiring 21 having a very large number of terminals. In the layout of the liquid crystal panel 2 and the driver IC 1, the segment input terminal S of the liquid crystal panel 2 is arranged.
The side 18b on which the EGs 1 to 100 are arranged and the driver IC
Side 1 on which the segment output terminals S1 to S100 of 1 are arranged
It is desirable to arrange them so as to face 7a.

However, with such an arrangement,
A problem occurs in the second scanning signal wiring 23 that connects the scanning signals of the second row. That is, since the scan input terminals COM9 to 16 and the scan output terminals C9 to 16 arranged with the driver IC 1 interposed therebetween have the same direction, the driver IC
If the wiring is carried out while avoiding the wiring No. 1, a cross-under in which the wirings are overlapped with each other occurs, and the wiring cannot be processed by the wiring using one surface of the substrate. Therefore, in the conventional device, without avoiding the driver IC1,
Wiring is provided in the region 24 of the substrate 20 on which the driver IC 1 is mounted to prevent the occurrence of cross under.

This area 24 is an area which is shielded from the driver IC 1 through the carrier film 17,
In a conventional device, there is no problem even if it is used as a wiring region. However, in recent years, with high integration and miniaturization of driver ICs, interference between terminals and wiring has become a problem. That is, with the miniaturization and high integration, I
The area of C is decreasing, while the number of terminals is increasing. For this reason, terminals are arranged almost all around the IC, and when wiring is performed using the back surface on which the IC is mounted as described above, interference between the wiring and other terminals becomes a problem. . For example, when wiring is performed using the back surface side of the IC 1 like the area 24, if the terminals are present in the direction in which the wiring is extended, that is, in the direction of the edge 17d of the driver IC, the wiring may be arranged. It will be impossible. There is also a method of arranging the wiring using the back surface of the substrate 20, but in general, other circuits are mounted on the back surface of the substrate, which significantly impairs the degree of freedom in designing the circuit. As a result, the substrate area cannot be effectively used, the substrate layout becomes complicated, the area also increases, and the price of the liquid crystal panel module increases.

Therefore, in view of the above problems, an object of the present invention is to make it possible to change the output order at the terminals of the driver IC so that the wiring on the substrate can be efficiently performed. It is to realize a driver IC that can increase the degree of freedom in wiring design between panels.

[0009]

In order to solve the above-mentioned problems, in the present invention, the shift register section of the multi-bit driving device is constituted by a bidirectional shift register section capable of switching a plurality of transfer directions, and The transfer directions of these bidirectional shift register units are controlled so that the input data input to the bidirectional shift register unit is selected based on the transfer direction. That is, the multi-bit driving semiconductor device having the function of converting a serial signal to parallel according to the present invention is provided with a plurality of bidirectional shift register units capable of switching the transfer direction of internal data for shifting a plurality of bits. Transfer direction selecting means for controlling the transfer direction of the bidirectional shift register section, and the input data input to the bidirectional shift register section based on the selection of the transfer direction selecting means is the serial signal and another bidirectional shift register section. And at least input data selecting means for selecting from any of the output data of the above.

A display driving signal can be used as the serial signal. Then, in a multi-bit driving semiconductor device for driving a display, which has a scanning side driver section for supplying a scanning signal to a scanning electrode of a display and a signal side driver section for supplying an image signal to a signal electrode of the display, a scanning side driver is provided. Section and / or the signal side driver section has a plurality of bidirectional shift register sections in which the transfer directions of the internal data for shifting a plurality of bits can be switched. Transfer direction selecting means to be controlled, and input data for selecting input data to be inputted to the bidirectional shift register section from image data or output data of another bidirectional shift register section based on the selection of the transfer direction selecting means. It suffices to have at least selection means.

[0011]

As described above, by configuring the shift register section of the multi-bit driving semiconductor device by a plurality of bidirectional shift register sections capable of switching the transfer directions, the bidirectional shift register section can change the data shift direction. It becomes possible to control. Therefore, the transfer direction of the drive signal of the bit converted in parallel by the bidirectional shift register section can be changed based on the shift direction. Therefore, in such a multi-bit drive semiconductor device, it is possible to freely change the transfer direction of the drive signal at the output terminal, and it is possible to change the wiring order connected to the output terminal.

The signal input to the bidirectional shift register section is selected from the output signals of other bidirectional shift register sections based on the transfer direction set by the transfer direction selection means, thereby shifting the multi-bit driving semiconductor device. A serial signal such as a series of image data input to the register unit can be converted into parallel signals. Among these bidirectional shift register units, depending on the selected transfer direction, the bidirectional shift register unit that forms the end of the shift register unit to which the serial signal is input is the other bidirectional shift register unit. By adopting the input data selecting means capable of selecting either the unit or the serial signal, it is possible to input the serial signal and perform parallel conversion even when the transfer direction is changed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 shows a schematic configuration of a driver IC 1 of a liquid crystal panel according to Embodiment 1 of the present invention. The driver IC 1 of this example is a driver IC that drives a liquid crystal panel of 20 columns × 2 rows, like the conventional driver IC described above. Therefore, this driver IC1
The shift register 14 for converting the segment signal Ds into parallel, the latch circuit 15, the selection switch 16, and the shift register 11 for converting the scanning signal Dc into parallel, the latch circuit 12, and the selection switch 13 are mainly configured. The function of each circuit is the same as that of the conventional driver I described above.
The description is omitted because it is similar to C.

A point to be noted in the driver IC 1 of this example is that the shift register 11 for converting the scanning signal Dc into parallel is composed of two bidirectional shift registers 31a, 31b capable of changing the shift direction of the internal data. Is. Furthermore, a control circuit unit 40 for controlling these bidirectional shift registers 31a and 31b is added. The control circuit unit 40 is provided in the bidirectional shift register 3
Direction control circuit 41 for controlling the shift directions of 1a and 31b
And input signal selection circuits 42a and 42b for selecting signals input to the bidirectional shift registers 31a and 31b, respectively.

The bidirectional shift registers 31a and 31b used in the driver IC 1 of this example are serially transferred to two transmission gates 51a and 51b connected in parallel as shown in FIG. A register 50 in which clocked inverters 52a, b and inverters 53a, 53b for discriminating signals are alternately connected in series.
Are connected in parallel. Therefore,
When the signal L controlling the transmission gates 51a and 51b is at the high level (1) and the signal R is at the low level (0),
The transmission gate 51a is opened, and the output of the left register, Ol, is input to the register 50.
On the contrary, when the signal L is 0 and the signal R is 1, the transmission gate 51b is opened and the output of the right register, Or, is input. Thus, the directions of the signals input to the register 50 can be controlled by the signals L and R. Therefore, in the bidirectional shift registers 31a and 31b composed of a plurality of registers 50, the shift direction of each internal data can be controlled by the signals R1, L1, R2 and L2.

These signals R1, L1, R2, L2 are
It is formed by the direction control circuit 41 that constitutes the control circuit unit 40. In this direction control circuit 41, signals R1, L1, R2 and L2 as shown in Table 1 are obtained by combining direction selection signals SC1 and SC2 supplied from the outside of IC1.
Is created.

[0018]

[Table 1]

In the direction control circuit 41 of this example, Table 1
In order to realize the truth value shown in, the output of the inverter 43a that inverts the selection signal SC1 and the inverter 44 that inverts the output from the inverter 43b that inverts the signal SC2.
The output of b is input to the NAND gate 45a, and its output is input to the terminal L1 of the bidirectional shift register 31a. Then, the signal input to the terminal L1 is inverted by the inverter 46a and input to the terminal R1. On the other hand, the signal input to the terminal R2 of the bidirectional shift register 31b is created by the NAND gate 45b input to the inverter 43a and the inverter 43b. Then, the signal input to the terminal R2 is inverted by the inverter 46b and input to the terminal L2. Further, the terminals 47a and b to which the signals SC1 and SC2 are input are n-channel pull-down transistors 48a and 48b to which a high level gate signal is applied.
Are mounted, and 0 is selected as the default value for both signals SC1 and SC2.

In the input signal selection circuit 42a for selecting the input signal of the bidirectional shift register 31a, first, the inverters 44a and 44b are input to the NAND gate 61a. Further, this output is output together with a signal obtained by inverting the output of the ninth register which is the leftmost register of the bidirectional shift register 31b by the inverter 62a.
It is input to the R gate 63a. Further, the output signal of the NAND gate 61a is inverted by the inverter 65a and then inverted by the inverter 66a to generate the scanning signal Dc.
It is also input to the OR gate 64a. And O
The R gates 63a and 64a are input to the NAND gate 65a, and the output of the NAND gate 65a is
It is input to the input D1 of the first register which is the leftmost register of the shift register 31a.

On the other hand, the input signal selection circuit 42b for selecting the input signal of the bidirectional shift register 31a has the same structure as 42a, and the outputs of the inverters 43a and 43b are input to the NAND gate 61b. And
The output of the NAND gate 61b and the shift register 31a
Output O8 of the 8th register which is the rightmost register of
The signal inverted by the inverter 62b is input to the OR gate 63b. On the other hand, the signal obtained by inverting the output of the NAND gate 61b by the inverter 65b and the scanning signal Dc inverted by the inverter 66b are input to the OR gate 64b. The outputs of the OR gates 63b and 64b are the NAND gate 67
The output of the NAND gate 67b is the rightmost register of the bidirectional shift register 31b.
It is input to the input D16 of the sixth register. Further, the output O9 of the ninth register of the shift register 31b is connected to the input D8 of the eighth register of the bidirectional shift register 31a, and conversely to the input D9 of the ninth register of the shift register 31b. Is connected to the output O8 of the eighth register of the shift register 31a.

The input signal selection circuit 42a having such a configuration
And 42b, in the case 1 and 2 of Table 1, the input D of the first register of the shift register 31a
1, the scan signal Dc is input to 1 and the input D of the 16th register of the shift register 31b in cases 3 and 4
The scanning signal Dc is input to 16. In the cases 1 and 2, the output O8 of the eighth register which is the last register of the shift register 31a appears at the input D16. However, in case 1, since the shift register 31b shifts the data from the left side, the output O
Input D9 of the 9th register in which 8 is input at the same time
The data shift starts from. The same applies to the signal at the input D1 in Cases 3 and 4, and the output O9 of the shift register 31b appearing at the input D1 in Case 4 is read. In case 3, output O9 is input D1.
However, since the shift direction of the shift register 31a is from the right side, the shift starts from the output O9 connected to the input O8 of the eighth register. In addition,
The input signal selection circuits 42a and 42b may be any circuits that fulfill the above functions, such as an OR gate and a NAN as in this example.
It can be realized by various circuits such as a circuit in which a transmission gate is combined in addition to a circuit in which a D gate is combined.

FIG. 3 shows a data transfer state of the bidirectional shift registers 31a and 31b controlled by the direction control circuit 41 and the input signal selection circuits 42a and 42b. In Table 1, in the case 1 in which the signals SC1 and SC2 are both 0, the signals L1, R1, and L supplied to the bidirectional shift registers 31a and 31b by the direction control circuit 41.
2, R2 becomes 1, 0, 1, 0. Therefore, the shift directions of the shift registers 31a and 31b are set from left to right. Then, the input signal selection circuit 42a causes the input D1
The scanning signal Dc is supplied to. Further, although the signal of the output O8 appears at the input D16 by the input signal selection circuit 42b, since the shift direction of the shift register 31b is from left to right, the output O8 appearing at the input D9 is the shift register 3b.
Read in 1b. Thus, when the signals SC1 and SC2 are both 0, the shift registers 31a and 31b shift data from left to right, like one shift register. As a result, the drive signal from the driver IC1 is
The signals are transferred in the direction of the outputs O1 to O16, that is, in the direction of the scan signal output terminals C1 to C16.

In case 2, the signal SC1 is 0, SC
Since 2 is 1, the signals L1, R1, L2, R2 are 1,
It becomes 0, 0, 1. Therefore, the shift direction of the shift register 31a is from left to right, and the shift direction of the shift register 31b is from right to left. Therefore, the scanning signal Dc input from the input D1 is input from the rightmost output O8 of the shift register 31a to the rightmost input D16 of the shift register 31b. And the shift register 3
In 1b, the data is shifted from right to left. As a result, the drive signals output from this driver IC1 are output from O1 to O8 from left to right and output O9.
From 0 to O16 are transferred from right to left.

Therefore, the scanning signal is output from the output terminals C1 to C.
8 and is output as a signal transferred from C16 to C9. Thus, signals SC1 and SC2
The scanning signal transfer direction can be freely changed only by changing the.

The same applies to the cases 3 and 4 as well. In case 3, the scanning signal Dc is supplied to the input D16 of the shift register 31b, and the shift register 31b is supplied.
Shifted from right to left in b. Then, it is input to the input D8 of the shift register 31a, and the shift register 31a
Shift from right to left. That is, in this case 3, the shift registers 31a and 31b perform the same operation as the shift register in which data is shifted from one right side to the left side. Further, in Case 4, the scanning signal Dc input to the input D16 of the shift register 31b shifts from right to left in the shift register 31b and is supplied to the input D1 of the shift register 31a. Then, the shift register 31a is shifted from left to right. Therefore, in case 3, the scanning signal is output as if it was transferred from the terminal C16 to C1.
In case 4, the data is output as transferred from the terminals C16 to C9 and the terminals C1 to C8.
Thus, in the driver IC of this example, the signal SC
Depending on the values of 1 and SC2, the directionality and the order of the terminals that output the scanning signal can be changed according to the arrangement of the printed circuit board.

FIG. 4 shows a state in which the liquid crystal panel 2 is arranged on the printed circuit board 20 using the driver IC 1 of this example. The type of terminals of the liquid crystal panel 2 and the driver IC 1,
For the layout and the wiring that connects these terminals,
Since it is the same as the conventional one described above, the same numbers are assigned and the description thereof is omitted. In this example, in the driver IC1,
Input terminals for the signals SC1 and SC2 that can select the transfer direction of the output terminals C1 to 16 of the scanning signal are provided.
When the signals SC1 and SC2 are set to 0 and 1, the scan signal is output from the terminals C1 to C8 and from C16 to C9 as described above. Therefore, the scan input terminals COM9 to 16 to which the scan signals of the second row of the liquid crystal panel are input, correspond to the terminals C16 to C9, that is, the terminals COM9 and C1.
6, COM10 and C15, COM9 and C14, and so on. Therefore, the terminals COM9 to 1
Unlike the conventional wiring described above, the wiring 23 connecting 6 and the terminals C9 to C16 can be a wiring that does not cause a cross-under even if it is arranged so as to avoid the IC1. As a result, the wiring 23 is connected to the IC 1 and the substrate 20.
Wiring design is facilitated since there is no need to place it between the two. Further, in order to secure the wiring area of the wiring 23 in the related art, it becomes possible to install a terminal also on the short side 17d of the IC 1 which cannot be used. And this driver I
A memory chip 70 storing image data in parallel with C1
It is also possible to connect the memory chip 70 and the driver IC 1 by the wiring 71. Of course, even if this memory chip 70 is arranged, the wiring region of the wiring 23 is not obstructed.

As described above, by using the driver IC of this example capable of changing the transfer direction of the terminals, I
The degree of freedom in arranging C, wiring, etc. on the board is improved, the area of the board is effectively utilized, and the size is small and the density is high.
It is possible to create a substrate that can be easily mounted.

[Second Embodiment] In the first embodiment, the shift register for converting the scanning signal Dc into parallel is composed of two bidirectional shift registers 31a and 31b. It is also possible to configure with two bidirectional shift registers 81a and 81b.

FIG. 5 shows two shift registers for converting the scanning signal Dc and the segment signal Ds into parallel signals.
Two bidirectional shift registers 31a, b and 81a, b
The schematic configuration of the driver IC 1 configured by is shown. Since the configuration of processing the scanning signal Dc and outputting it to the outputs C1 to 16 is the same as that of the first embodiment, the same numbers are assigned and the description thereof is omitted.

The bidirectional shift registers 81a and 81b for performing parallel conversion of the segment signal Ds each include 50 registers, and each register is a register that can be bidirectionally shifted as shown in FIG. Therefore, regarding the segment signal Ds, in the processing of the scanning signal Dc described in the first embodiment, the input D8 is the input D50, the output O8 is the output O50, the input D9 is the input D51, and the output O9.
Is replaced with the output O51, the input D16 is replaced with the input D100, and the output O16 is replaced with the output O100.
Further, a segment control circuit section 80 for selecting the direction of the bidirectional shift registers 81a, 81b and an input signal is formed, and this control circuit section 80 is controlled by the control signals SS1 and SS2.
It is controlled by. The configuration of the control circuit section 80 and the relationship with the control signals SS1 and SS2 are the same as the configuration of the control circuit section 40 and the control signal SC in the first embodiment.
The description is omitted because it is the same as that of 1 and SC2.

FIG. 6 shows an arrangement example using the driver IC of this example. The driver IC 1 is on the right side of the liquid crystal panel 2.
Are arranged, in order to avoid cross-under of wiring, output terminals S1 to S100 of the segment signal of IC1
And the segment input terminals SEG1-10 of the liquid crystal panel 2
It is desirable that the wirings 21 are connected to each other in the order opposite to 0. That is, the terminal S1 and the terminal SEG1
00, terminals S2 and terminals SEG99, etc., may be connected so as to be connected to each other. On the other hand, in the scan signal, the input terminals COM1 to COM8 are output from the output terminals C9 to 16
Also, the input terminals COM9 to 16 are connected to the output terminals C1 to
8 is preferably connected. Also in this connection, the wirings 22, so that the order of each terminal is reversed,
By connecting with 23, cross-under can be avoided. That is, the terminal COM1 and the terminal C1
6, terminal COM2 and terminal C15, and terminal COM16
The terminals C8 and the terminals COM15 and C7 may be connected so that the terminals are connected.

In order to perform display using the driver IC 1 and the liquid crystal panel 2 connected in this way, the scanning signal Dc
Must be transferred from COM1 to COM16. Therefore, in the output of the driver IC1,
A signal may be output so as to be transferred to the terminals C16 to C9 and further to the terminals C1 to C8. Since this transfer direction corresponds to case 4 shown in FIG. 3, the selection signal SC
This can be achieved by setting both 1 and SC2 to 1. On the other hand, regarding the segment signal Cs, SEG1
Must be transferred from the SEG100 to the SEG100.
The signal may be output so as to be transferred from S1 to S1. Since this transfer direction corresponds to case 3 shown in FIG. 3, the selection signals SS1 and SS2 may be set to 1 and 0, respectively.

As described above, various wiring arrangements can be adopted by dividing the segment signal and the scanning signal in the driver IC and changing the transfer direction for each division. Therefore, by using the driver IC of this example, the degree of freedom of wiring arrangement for connecting the driver IC to the liquid crystal panel is improved in the board arrangement changed according to the display device, and the board area can be effectively used. It becomes possible to do. Therefore, it becomes easy to reduce the size or increase the integration of the liquid crystal module in which the liquid crystal panel is mounted.

The semiconductor device in which the transfer direction can be changed for each division by using the bidirectional shift register as described above is not limited to the image signal processing of the liquid crystal panel, and a multi-bit such as a plasma display or a printer can be used. By using it in a driving device, it is possible to improve the flexibility of the substrate arrangement, and it is possible to realize a small-sized and high-performance device.

Although an example using two bidirectional shift registers has been described above, the number of bidirectional shift registers is not limited to two, and some bidirectional shift registers may be used to transfer directions. It is also easy to increase the number of controllable bit divisions. Also, it is not necessary that the number of bits handled in the bidirectional shift register be the same, and it goes without saying that there are various division methods. Furthermore, the connection direction of each bidirectional shift register can be changed in various ways.
→ 8 → 9 → 16, 1 → 8 → 16 → 9, 16 → 9 → 8 →
4 cases of 1, 16 → 9 → 1 → 8 are explained, but 8
→ 1 → 16 → 9, 8 → 1 → 9 → 16, 9 → 16 → 1 →
It is of course possible to adopt transfer directions such as 8, 9 → 16 → 8 → 1.

[0037]

As described above, in the multi-bit driving semiconductor device according to the present invention, a control for selecting a plurality of bidirectional shift registers, a transfer direction of the shift registers and an input signal input to the shift register. It is characterized by having a circuit section. Therefore, the transfer directions of the plurality of bidirectional shift registers can be controlled, and the input signal can be selected based on the transfer directions. For this reason,
It is possible to freely change the transfer direction of the drive signal that is parallel-converted and output by these bidirectional shift registers, and increase the degree of freedom of wiring arrangement for connecting the multi-bit drive semiconductor device and the driven device. Can be achieved. Since the boards on which these devices are mounted can be efficiently arranged, it is possible to reduce the size and the density of the boards.

Further, also in the multi-bit driving semiconductor device itself, the degree of freedom of the wiring connected to the terminal is increased, so that the degree of freedom of the terminal arrangement, which is limited in consideration of the wiring, is also increased. Therefore, it is possible to adopt a terminal arrangement that enables efficient mounting,
It is also possible to maintain the terminal spacing, which tends to decrease as the size and density increase.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a driver IC according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an example of a register that constitutes a bidirectional shift register.

FIG. 3 is an explanatory diagram illustrating a transfer direction of a scanning signal in the driver IC shown in FIG.

FIG. 4 is a layout view of a liquid crystal module arranged using the driver IC according to the first embodiment.

FIG. 5 is an explanatory diagram showing a configuration of a driver IC according to a second embodiment of the invention.

FIG. 6 is a layout view of a liquid crystal module arranged by using a driver IC according to a second embodiment.

FIG. 7 is an explanatory diagram showing a configuration of a conventional driver IC.

FIG. 8 is a layout view of a liquid crystal module arranged using a conventional driver IC.

[Explanation of symbols]

1 ... Driver IC 2 ... Liquid crystal panel 4 ... Scan control signal 5 ... Segment control signal 11, 14 ... Shift register 12, 14 ... Latch circuit 13, 16 ... Selection switch 17 ... Carrier film 20 ... Printed circuit boards 21-23, 71 ... Printed wiring 31a, 31b, 81a, 81b ... Bidirectional shift register 40, 80 ... Control circuit part 41 ... Direction Control circuit 42a, b ... Input signal selection circuit 43, 44, 46, 52, 53, 62, 65, 66
.. Inverters 45, 61, 67 ... NAND gate 51 ... Transmission gates 63, 64 ... OR gate 70 ... Image memory chip Dc ... Scan signal Ds ... Segment signals C1-16. .... Scanning signal output terminals S1 to 100 of driver IC ... Segment signal output terminals COM1 to 16 of driver IC ... Scan signal input terminals SEG1 to 100 of liquid crystal panel ... Segment signal input terminals of liquid crystal panel

Claims (3)

[Claims] 1. A multi-bit driving semiconductor device having at least a function of converting a serial signal into a parallel signal is provided with a plurality of bidirectional shift register sections capable of switching a transfer direction of internal data for shifting a plurality of bits. Transfer direction selecting means for controlling the transfer direction of the bidirectional shift register section, and input data input to the bidirectional shift register section based on the selection by the transfer direction selecting section is the serial signal and the other bidirectional shift register. A multi-bit driving semiconductor device, comprising at least input data selecting means for selecting any of the output data of the unit. 2. The multi-bit drive semiconductor device according to claim 1, wherein the serial signal is a display drive signal. 3. A display driving semiconductor device having a scanning side driver section for supplying a scanning signal to a scanning electrode of a display and a signal side driver section for supplying an image signal to a signal electrode of the display, wherein the scanning side driver is provided. Section and / or the signal side driver section has a plurality of bidirectional shift register sections in which the transfer directions of the internal data for shifting a plurality of bits can be switched. Transfer direction selecting means to be controlled, and input data input to the bidirectional shift register section is selected from image data and output data of the other bidirectional shift register section based on the selection of the transfer direction selecting means. Display driving semiconductor having at least input data selecting means apparatus.