JPH0535196A - Display controller - Google Patents

Abstract

PURPOSE:To prolong the life of a display unit and to enable proper driving control corresponding to the use state of the device by effectively utilizing the maintainability of the display state of the display unit which has ferroelectric liquid crystal(FLC) as a display element. CONSTITUTION:An access monitoring means 6 is provided to monitor the time of no access to a video memory 3 from a display data supply means 2 and a display driving control means 4 stops a display unit driving means 5 from driving the FLC panel 1 unless there is access for a certain time, namely, when current display contents are not altered. Further, the standstill time is made settable according to a difference of application software, the skillfulness of an operator, etc., so that the driving can properly be stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
More specifically, the present invention relates to a display control device for a display device that includes a display element that can maintain a display state updated by applying an electric field or the like using a ferroelectric liquid crystal as an operation medium for display update.

[0002]

2. Description of the Related Art Generally, a display device is connected to an information processing system or the like as an information display means for performing a visual display function of information. A CRT has been widely used as such a display device, but since the CRT requires a certain length in the thickness direction of the display screen, the volume of the CRT becomes large as a whole, and it is difficult to downsize the entire display device. . Further, this impairs the degree of freedom in using the information processing system using such a CRT as a display, that is, the degree of freedom in installation location, portability and the like.

A liquid crystal display (hereinafter referred to as an LCD) can be used to supplement this point. That is,
According to LCD, downsizing of the entire display device (especially thinness)
Can be achieved. Among such LCDs, a ferroelectric liquid crystal (hereinafter, referred to as FLC: Ferroelectric
There is a display (hereinafter referred to as FLCD: FLC display) using a liquid crystal cell (Liquid Crystal), and one of the features is that the liquid crystal cell has a storage state of a display state against the application of an electric field. is there.
Therefore, when driving the FLCD, unlike the CRT and other liquid crystal displays, there is a time margin in the cycle of continuous refresh driving of the display screen, and in addition to the continuous refresh driving, Partial rewriting drive for updating the display state of only the part corresponding to the change on the display screen becomes possible. Therefore, such an FLCD can be used as a large-screen display as compared with other liquid crystal displays.

Here, in the FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field. , The respective alignment state is maintained even when the electric field is cut off. Due to the bistability of the FLC molecule, F
The LCD has a memory property. Such FLC and FL
Details of the CD are described, for example, in JP-A-63-243919.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display control device which can effectively utilize the storage property of the display state of an FLCD or the like and can prolong the life of the display panel of the FLCD or the like. .

Another object of the present invention is to make it possible to obtain an appropriate drive stop state of the display according to the use state of the device.

[0007]

To this end, the present invention provides
A display control device for a display device having a display screen in which a plurality of display elements capable of holding an updated display state are arranged, comprising a monitoring means for monitoring supply of display data from a display data supply source. The monitoring means is capable of setting a time, and stops driving the display element in the display device when the supply is stopped for a set time or longer.

[0008]

According to the present invention, the monitor means is provided to monitor the access of the display data by the display data supply means, and if there is no access for a certain time or more, that is, if there is no change in the current display content, the display element of the display device is not changed. Stop driving.
Since the display state can be stored in the display device such as FLC, the inconvenience such as disappearance of the display does not occur. Further, by obtaining such a non-driving state, the deterioration of the display element can be delayed and the life can be extended.

Further, by making it possible to set the time until the driving is stopped, it becomes possible to perform control corresponding to the usage state of the system (difference in application, proficiency level of operator, etc.).

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(1) First Embodiment (1.1) Outline FIG. 1 is an explanatory view showing an outline of the first embodiment of the present invention.
Here, a display data supply unit (for example, an information processing system as shown in FIG. 2) forming a host device can be used for the display (FLC panel) 1 configured by using the FLC element, but the present invention is not limited to this. 2) accesses the video memory 3 for displaying, erasing, updating, etc. of data. The display drive control means 4 drives (partially rewrites or refreshes) the FLC panel 1 with respect to the contents of the video memory 3 via the display drive means 5. One of the features of this example is that the access monitoring means 6 is provided to monitor the non-access time of the video memory 3 by the display data supplying means 2, and if there is no access for a certain time or more, that is, the current display content is changed. If not, the display drive control means 4 prohibits the display drive means 5 from driving the FLC panel 1. As described above, since the FLC element retains one orientation state even when the driving is stopped, the FLC element
Inconvenience such as disappearance of display data on panel 1 does not occur,
As long as a light source such as a so-called backlight is secured, the visibility of the operator will not be impaired.

By obtaining the state in which the driving of the FLC panel 1 is stopped (hereinafter, that state is referred to as the static mode), the deterioration of the FLC element due to the continuous driving can be delayed and the life of the FLC panel can be extended, Moreover, the power consumption can be reduced. Further, in the static mode, flicker due to refreshing does not occur, and it is expected that the degree of fatigue of the eyes of the operator can be reduced.

The time until the transition to the static mode can be made variable according to the usage state of the information processing system, for example, the difference in application and the skill level of the operator. In other words, depending on the application being used, or if the operator's skill level is high, the display contents may be updated frequently.Therefore, set a long time before switching to the static mode to update the display contents quickly. To be able to deal with. On the contrary, when the display contents are not frequently changed or the operator's skill level is low, the static mode is obtained relatively quickly by setting a short time until the static mode is entered.

(1.2) Information Processing System FIG. 2 is a block diagram of the entire information processing system incorporating the display control device according to one embodiment of the present invention.

In the figure, 11 is a CPU for controlling the entire information processing system, 12 is a system bus consisting of an address bus, a control bus and a data bus, 13 is a main memory used for storing programs and as a work area, and 14 is a main memory. A DMA controller (Dire) that transfers data between the memory and the I / O device without going through the CPU 11.
ct Memory Access Control
er, hereafter called DMAC, 15 is Ethernet (X
LAN interface with a LAN (local network) 16 such as (by EROX), 17 is RO
An I / O device for connecting I / O equipment including an interface of M, SRAM, RS232C specifications, 18 is a hard disk device, 19 is a floppy disk device, 20 is a disk interface for the hard disk device 18 and the floppy disk device 19, Reference numeral 21 is a high-resolution printer such as a laser beam printer or inkjet printer, 22 is a printer interface for the printer 21, 23 is a keyboard for inputting characters such as letters and numbers, and a mouse is a pointing device. 25 is a keyboard 23 and a mouse 2
4, an FLCD (FLC display) 26 which can be constructed by using the display disclosed in Japanese Patent Laid-Open No. 63-243993 by the present applicant, and 27 is an FLCD interface for the FLCD 26.

(1.3) FLCD Interface FIG. 3 shows an FLCD as an embodiment of the display control device of the present invention.
3 is a block diagram showing a configuration example of an interface 27. FIG.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, 4
Reference numeral 4 is a data bus driver. The address data from the CPU 11 is given from the address bus driver 31 to one input portion of the memory controller 40 and the address selector 35, and selectively given to the FIFO type memory 36 or 37 by switching the first switch S1. Stored and stored. That is, these memories 36 and 37 (hereinafter, also referred to as FIFO (A) and FIFO (B), respectively) read out data in the order in which they are written in (FIFO (First In First)).
Out) memory, these memories 36 and 3
The address data written in 7 is the second switch S
It is selectively read out by switching of 2.

Address data read from the memory 36 or 37 and an address counter 3 described later.
The address data from 8 is selectively applied to the other input section of the address selector 35 by switching the third switch S3. The address counter 38 generates address data for line-sequentially refreshing the entire screen, and the generation timing of the address data is controlled by the synchronization control circuit 39. The synchronization control circuit 39 is provided with the switches S1, S2 and S3.
Switching control signal and memory controller 40 described later
It also generates a data transfer request signal to.

The control signal from the CPU 11 is sent from the control bus driver 32 to the memory controller 4
0, the memory controller 40 generates a control signal for the sampling counter 34, the address selector 10, and a control signal for the video memory 41 described later. The sampling counter 34 performs a counting operation based on the step signal from the memory controller 40 and generates a control signal for the synchronization control circuit 39. Further, the address selector 35 selects one of the two address data given to the input part of the address selector 35 based on the control signal from the memory controller 40 and gives it to the video memory 41.

The video memory 41 stores display data, is composed of a dual port DRAM (dynamic RAM), and has the data bus driver 3 described above.
Writing and reading of display data are performed via 3. The display data written in the video memory 41 is transferred to the FLCD 26 via the driver receiver 42 and displayed. Further, the driver receiver 42 is the FLCD 2
The sync signal from 6 is applied to the sync control circuit 39. FLC
D26 is a temperature sensor 26a that detects the temperature of the FLC.
Is built in.

Further, setting data, which will be described later, from the CPU 11 is sent to the synchronization control circuit 39 via the data bus driver 43.
Given to. Further, the output signal of the temperature sensor 26a is transferred to the CPU 11 via the data bus driver 44. Reference numeral 46 is a timer, and in this example, the clock time can be set by the CPU 11 via the bus driver 47. The timer 46 is reset / restarted by the access signal A generated by the memory controller 40 each time it is accessed by the CPU 11, and generates the time-up signal D when the set time is counted from the time when the access signal is input.

(1.4) Display Update Operation With the above configuration, when the CPU 11 changes the display, the video memory 4 corresponding to the rewriting of the desired data.
The address signal of 1 is given to the memory controller 40 via the address bus driver 31, and here the CPU 11
The memory access request signal and the data transfer request signal from the synchronous control circuit 39 are arbitrated. When the CPU access side obtains the right, the memory controller 40 switches the address selector 35 so that the address accessed by the CPU is selected as the address given to the memory 41. At the same time, a control signal for the video memory 41 is generated from the memory controller 40, and data is read / written via the data bus driver 33. At this time, CPU access address 2
0 is FIFO (A) 36 or F via switch S1
It is stored in the IFO (B) 37 and is used when the display data described later is transferred. In this way, the display data access method seen from the CPU 11 is no different from that of the CRT.

When data is read from the video memory 41 and transferred to the FLCD 26, a data transfer request is issued from the synchronization control circuit 39 to the memory controller 40, and the address counter 38 or the FIFO side address is used as an address for the video memory 41. The control signal for data transfer is generated by the memory controller 40 while being selected by the selector 35, whereby the data of the corresponding address is transferred from the memory cell to the shift register and is output to the driver 42 by the control signal of the serial port. It

The sync control circuit 39 has a cycle in which the entire screen is line-sequentially refreshed in units of a plurality of lines based on the horizontal sync signal HSYNC from the FLCD 26, and a partial rewrite cycle in which the line accessed by the CPU 11 is rewritten. The timing for alternately generating is generated. Here, the full refresh cycle is to rewrite sequentially from the top line (top line) on the display screen downward, and when it reaches the bottom line, it returns to the top line again and rewrites. It repeats itself. Further, the access line rewriting cycle is to rewrite the line accessed by the CPU 11 within a predetermined time immediately before the cycle.

As described above, in the present example, basically, the CPU 11 performs the operation of sequentially refreshing the entire screen of the FLC display 26 and changing the display content.
The operation of rewriting the line accessed by is performed alternately in a time-sharing manner. Furthermore, the repetitive synchronization of these operations and the time ratio of those operations within one cycle can be set, and line rewriting (partial rewriting) is performed. The operation period of) is adjusted according to the number of lines accessed by the CPU 11 and the like.

Here, the basic operation of this example in which the refresh operation and the line rewriting operation are alternately performed in a time division manner will be described with reference to FIG. Here, an example is shown in which the refresh cycle is performed in units of four lines and the access line rewriting cycle is performed in units of three lines.

In FIG. 4, REF / inverted ACS is a timing at which a full refresh cycle and an access line rewrite cycle are alternately generated. The full refresh cycle is "1" and the full refresh cycle is "0". Indicates that the access line is rewritten. In addition, T _a represents the time of the full refresh cycle, and T _b represents the time of the access line rewrite cycle. In this example, T _a : T _b = 4: 3, but an optimum value can be selected depending on the required refresh rate and the like. That is, the refresh rate can be increased by increasing the ratio of T _a , and the responsiveness of partial change can be improved by increasing the ratio of T _b . This aspect will be described later.

FIFO (A) 36 and FIFO (B)
In order to explain the state of 37, the switch S1 is a FIFO.
(A) When connected to the 36 side (state A / inversion B = 1),
The address of the line accessed by the CPU 11 is FIFO
(A) 36 is sampled and stored. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side (A /
Inversion B = 0), the line address accessed by the CPU 11 is stored in the FIFO (B) 37. When the switch S2 is connected to the FIFO (A) 36 side (A / inversion B = 1), the address stored in the FIFO (A) 36 is output, and the switch S2 is connected to the FIFO (B) 37 side. When this is done (A / inversion B = 0), the address stored in the FIFO (B) 37 is output.

Once the entire screen has been refreshed,
When the FLCD 26 outputs a vertical synchronizing signal or when a carry occurs in the address counter 38, the address counter 38 is cleared and the line output in the next full refresh cycle returns to the 0th line.
6, the horizontal sync signal HSYNC given via the sync control circuit 39 is sequentially incremented to "1", "2", "3". During this time, the CPU 11 causes the line L1,
When the addresses L2 and L3 are accessed, the switch S
1 is connected to the FIFO (A) 36, L1,
The addresses of L2 and L3 are stored here, and when the switch S2 is subsequently connected to the FIFO (A) 36, L1,
The addresses of L2 and L3 are output from here, and L1, L2 and L3 are selected as output lines. Here, the switching signal of the switch S3 is given as REF / inverted ACS from the synchronous control circuit 39, and in the line access cycle, FIFO (A) and FIFO are used as output line addresses.
It is switched to the (B) side.

At this time, the switch S1 is a FIFO
(B) Since it is connected to the 37 side, the FIFO (B) 37
The access address is stored on the side. REF / reversed AC
When S becomes "1", the switch S3 is switched to the address counter 38 side, and the refresh operation is performed from the line following the previous cycle. In FIG. 4, after the line output of L3, “4”, “5”, which is a continuation of the previous cycle,
The lines "6" and "7" are output. The above operation is repeated in the same manner, but two FIFOs are prepared so that the memory-accessed address is sampled on the one hand and the sampled address is simultaneously output on the other hand without any inconsistency. This is because That is, the address sampling period is the other F
From the start of the output of the IFO access line to the end of the full refresh cycle, and after the end of the full refresh cycle, at the same time as entering the access line rewriting cycle that outputs the address sampled in the previous sampling period, the address of the other FIFO The sampling period will start.

[0031] As described above, in the basic operation of the present embodiment repeatedly alternating with cycles of the refresh cycle and the line rewriting, T _a in FIG. 4 the repetition period of seven lines as a unit: T _b = 4: 3 However, in this example, the ratio between T _a and T _b is further determined by the refresh rate required according to the environmental conditions such as temperature, the type of data to be displayed, or the difference in the display device material of the FLCD. Can be changed. That is, the ratio of T _a (corresponding to the number M of lines in one refresh cycle.
_The refresh rate can be improved by increasing _a = M × (the cycle of HSYNC).
A good display state can be obtained even when the response of the LC element is low or when an image is displayed. On the contrary, _if the ratio of T _b (corresponding to the number N of lines in one partial rewriting cycle, that is, T _b = N × (the cycle of HSYNC)) is increased, the response of the partial display change is increased. Therefore, it is possible to cope with the case where the refresh rate does not need to be high, such as when the temperature is high or when characters such as characters are displayed.

Further, in this embodiment, the number of lines of the repeating cycle can be set, so that the refresh cycle and the partial rewriting rate can be changed more finely, and finer optimization can be achieved. . For example, you have to give priority to the refresh rate,
Or, if you want to give priority, set the number of lines in the repeat cycle to 4
If 0 lines are set and T _a : T _b = 4: 1, the entire surface refresh can be performed for 32 lines and the access lines can be rewritten for 8 lines. Further, if partial rewriting can be given priority, or if it is desired to give priority, if the number of lines in the repetition cycle is 10 and T _a : T _b = 3: 2, then full refresh is performed for 6 lines to rewrite the access line. You can do the line.

Further, within the range of the number of lines for partial rewriting thus set, the actual number P of partial rewriting lines performed during the refresh cycle is adjusted according to the number of lines accessed by the CPU 11 and the line access state. You can also choose to do so. That is, CP
Dynamically T _b according to the number of lines accessed by U 11
By adjusting the time, for example, a wasteful line rewriting cycle when the CPU 11 is not frequently accessed is omitted, and the refresh rate is improved. As a result, it becomes possible to dynamically optimize the relationship between the followability of the operation and the refresh rate. These are disclosed in Japanese Patent Application No. 2-105626 by the present applicant.

(1.5) Structure of FLCD 26 FIG. 5 shows a structure example of the FLCD 26. Here, 261 is an FLC panel, for example, Japanese Patent Laid-Open No. 63-243919.
As disclosed in Japanese Patent Laid-Open No. 2000-242242, it is composed of a pair of upper and lower glass substrates with a deflector in which FLC is sealed, a transparent electrode wiring group provided on the upper and lower glass substrates, and the like. The wiring directions of the wiring group on the upper glass substrate and the wiring group on the lower glass substrate are orthogonal to each other, and the number of wirings can be appropriately determined according to the size and resolution of the display screen. In this example, the density of 4 pels is 960 in the horizontal scanning direction.
Since there are 1312 lines in the vertical scanning direction and the polarity and strength of the electric field generated at the intersection of the lines can change the alignment state of the FLC in that part, the FLC panel of this example can be changed. The number of display pixels is 1312 x 9
It becomes 60.

In the present example, 1312 extending in the horizontal scanning direction
The wiring group of the book is called a common side wiring, and the above-mentioned sequential line addresses are assigned to these. A group of 960 wires extending in the vertical scanning direction is called a segment-side wire, and when a certain common-side wire (line) is selected and driven, the segment-side wire group is driven to drive that line. Displayed, deleted, and updated.

In FIG. 5, reference numerals 263 and 265 respectively denote drive units (common drive unit and segment drive unit) for driving the common side wiring group and the segment side wiring, respectively, which are suitable for display data. Each wiring is driven by a waveform voltage signal. The waveform and the like are disclosed, for example, in JP-A-63-243919.

The display data signal is related to a display line, a part indicating the line address and a data group (9
It is input from the video memory 41 as a serial signal Address / Data composed of 60 dots of data). Further, in order to distinguish the address portion and the data group of the signal, an identification signal AH / DL that is H in the address portion and L in the data group portion is supplied. The data conversion unit 267 separates the address (line address) Address and the data group Data from the display data signal Address / Data based on the identification signal AH / DL, and sets them in the common driving unit 263 and the segment driving unit 265, respectively. In addition, the horizontal scanning signal HSY
The NC is sent to the FLCD interface side by this data conversion unit 267.

Further, 269 is a control unit, which is a timer 4
6 is input as the static mode instruction signal ST, and at the time of the input, the FL signal is input to the common drive unit 263 and the segment drive unit 265.
Stop driving the C panel. Various methods are conceivable for this driving stop, but for example, both drive units can be made to hold the output voltage at a constant value. In this case, since there is no potential difference between the common line and the segment line, the FLC element is not driven, and thus the long life, which is the main object of the present invention, can be achieved. Also,
If the output voltage at that time is low, power saving can be achieved. Even if the driving is stopped in this way, the FLC
Since the alignment state does not change due to the characteristics of the element, the display function is not hindered. Rather, since the display is not updated (refreshed) by setting the non-driving state, a display state without flicker can be obtained.

(1.6) Static Mode In this example, the time until the transition to the static mode is variable by changing the time set in the timer 46. The time setting to the timer 46 can be executed by the procedure as shown in FIG. That is, first, in step S1, the condition for setting the time is determined, and in step S3, the CPU 11 is determined via the bus driver 47 based on this.
Is to set the timer.

Here, various modes can be considered as the condition determination in step S1. For example, if the system is provided with a volume, a switch, or the like for instructing a time change, or if a predetermined key operation can be accepted, the operation state is determined according to the operation. It can be Also, since the frequency of updating the displayed contents varies depending on the application,
It may be possible to determine the application currently used. Furthermore, a graphic event such as cursor movement may be determined. in addition,
Since the speeds of key operations and mouse operations for updating the display contents differ depending on the skill level of the operator, it is possible to determine the display updating interval and the like. Alternatively, it is possible to adopt the above combination.

Then, the timer set values can be made into a table on a predetermined memory in accordance with the above conditions, and an appropriate value can be set in the timer 46 in step S3.

The procedure shown in FIG. 6 can be appropriately activated in response to an operator's operation, periodically, or in response to a change in application.

FIGS. 7 and 8 are a flow chart and a timing chart for explaining the operation in the static mode, respectively. That is, if there is an access from the CPU 11 into the display area (operation OP
1), stop the time counting operation from the previous access, start the time counting from the present time, and deactivate the static command signal (operation OP3).

On the contrary, if there is no access, the timing operation is continued (operation OP5). When the time T set in step S3 has elapsed (operation OP7), the FLCD 26 is notified of the shift to the static mode (operation OP9).

Specifically, these operations are performed as the operations of the memory controller 40 and the timer 46 in FIG. That is, the memory controller 40
Notifies the access of the video memory 41 by the CPU 11 to the timer 46, and the timer 46 resets the time counting time and restarts the time counting operation in response to the notification, and outputs this as the signal D with the time up of the set time. The FLCD 26 is notified. Even in the static mode, if the CPU 11 accesses the video memory 41, the timer is reset / restarted, the signal D is deenergized, and the static mode of the FLCD 26 is released.

(2) Second Embodiment In the first embodiment, the static mode is set by sending the signal ST instructing the static mode transition to the FLCD.
LCD interface FL horizontal sync signal HSYNC
In addition to sending to the CD, the HSY
The transition to the static mode is performed using the NC signal. That is, the FLCD in this example is a known LCD for a host or FLCD interface.
Like a CRT or CRT, it functions as a passive device that operates by receiving the HSYNC signal, and uses part of that function to FL
The non-driving state of the C panel is obtained.

FIG. 9 shows the configuration of the FLCD interface in this example. Here, with respect to each unit that can be configured in the same way as in FIG.

The synchronization control circuit 139 in this example is similar to that shown in FIG.
The synchronization control circuit 39 is substantially the same as the synchronization control circuit 39, except that it further includes an oscillator for generating an HSYNC signal, a frequency divider, etc.
It is supplied to the LCD 126. Then, the supply of the HSYNC signal is stopped in response to the time-up signal D generated by the timer 46. In order to stop the HSYNC signal, a logic gate that deactivates the HSYNC signal according to the signal D may be added.

FIG. 10 shows an example of the configuration of the FLCD 126 in this example, which is an FLC panel 261, a common drive section 263.
The segment drive section 265 has the same configuration as that of the first embodiment shown in FIG. Data converter 1
267 and the control unit 1269 are the same as the respective units 267 and 269 in FIG. 5, respectively, but the data conversion unit 1267 of this example has an Addr of the display data signal according to the HSYNC signal supplied from the FLCD interface side.
A distribution operation between the ss signal section and the Data signal is performed. The control unit 1269 also controls the common drive unit 263 and the segment drive unit 2 when the supply of the HSYNC signal is stopped.
The driving of the FLC panel 261 is stopped for 65. This shifts to the static mode.

Also in this example, the time until the transition to the static mode can be made variable by changing the time set in the timer 46. And the timer 46
The time setting to can be performed in the same manner as described with reference to FIG.

FIG. 11 and FIG. 12 are a flow chart and a timing chart for explaining the operation in the static mode in this example, respectively. That is,
When there is an access from the CPU 11 into the display area (operation OP11), stop of the time counting operation from the time of the previous access, start of the time counting from the present time, deactivation of the signal D for the static mode transition, and HSYNC. The generation is restarted (operation OP13).

On the contrary, if there is no access, the timing operation is continued (operation OP15). When the set time T elapses as in step S3 of FIG.
17) Energize the signal D for shifting to the static mode to stop the generation of the HSYNC signal (operation O
P19).

Specifically, these operations are performed as the operations of the memory controller 40, the timer 46, and the synchronization control circuit 139 in FIG. That is,
The memory controller 40 notifies the access of the video memory 41 by the CPU 11 to the timer 46, and the timer 46 resets the time counting time and restarts the time counting operation according to the notification, and when the set time is up, this is notified. The signal D is sent to the synchronization control circuit 139. In response to this, the synchronous control circuit 139 stops the supply of the HSYNC signal to the FLCD 126, and accordingly, the driving of the FLC panel 26 is stopped. If the CPU 11 accesses the video memory 41 even in the static mode, the timer is reset / restarted to deactivate the signal D, and the supply of the HSYNC signal is restarted to release the static mode of the FLCD 26. Of course it will be done.

In this example, the same effect as in the above-described first example can be obtained, but in this example, a special signal to be supplied to the FLCD side in order to further obtain the static mode is unnecessary, so that the structure of the connecting portion is formed. Can be simplified. Also, HSY
Since the NC signal is generated on the FLCD interface side, H on the FLCD interface or the host side
It becomes unnecessary to monitor the SYNC signal and the generation circuit of the HSYNC signal on the FLCD side, and to use a well-known LCD or CRT.
It is also possible to promote standardization of the interface with. Further, the Address / Data signal in FIG. 10 is set to Data.
If only the signals are used and the access method of the FLC panel is, for example, only fixed interlace scanning, the interface can be shared with a known LCD.

[0055]

As described above, according to the present invention,
The display storability in the display panel such as the FLCD is effectively used, and the drive of the display panel is stopped when the display is not updated, so that the life of the display panel can be extended.

Further, by making it possible to set the time until the driving is stopped, it becomes possible to perform the driving stop control corresponding to the usage state of the system (difference in application, operator's proficiency level, etc.).

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an outline of an embodiment.

FIG. 2 is a block diagram of the entire information processing apparatus in which the display control apparatus according to the embodiment of the present invention is incorporated.

FIG. 3 is a block diagram showing a configuration of an FLCD interface as one embodiment of the present invention.

FIG. 4 is a timing chart for explaining a basic operation of the FLCD interface shown in FIG.

FIG. 5 is a block diagram showing a configuration example of an FLCD in one embodiment of the present invention.

FIG. 6 is a flowchart showing an example of a procedure for setting a static mode transition time.

FIG. 7 is a flow chart for explaining the operation of the embodiment of the present invention.

FIG. 8 is a timing chart of the same.

FIG. 9 is a block diagram showing a configuration of an FLCD interface as another embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration example of an FLCD in another embodiment of the present invention.

FIG. 11 is a flowchart for explaining the operation of another embodiment of the present invention.

FIG. 12 is a timing chart of the same.

[Explanation of symbols]

1,261 FLC panel 2 Display data supply means 3 video memory 4 Display drive control means 5 Display drive means 6 Access monitoring means 11 CPU 12 address bus 13 system bus 14 DMA controller 15 LAN interface 16 LAN 17 I / O device 18 Hard disk drive 19 Floppy disk drive 20 disk interface 21 Printer 22 Printer interface 23 keyboard 24 mice 25 key interface 26,126 FLCD (FLCD display) 26a Temperature sensor 27 FLCD interface 31 Address driver 32 control bus driver 33,43,44 data bus driver 34 Sampling counter 35 address selector 36 FIFO (A) memory 37 FIFO (B) memory 38 address counter 39,139 Synchronous control circuit 40 memory controller 41 video memory 42 driver receiver 46 timer 263 common drive 265 segment drive 267, 1267 Data converter 269, 1269 Control unit S1, S2, S3 switches

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kenzo Ina             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation

Claims (3)

[Claims] 1. A display control device for a display device comprising a display screen in which a plurality of display elements capable of holding an updated display state are arranged, wherein supply of display data from a display data supply source is monitored. A display control device comprising: a monitoring unit, wherein the monitoring unit can set a time, and stops driving of a display element in the display device when the supply is stopped for a set time or longer. 2. A video memory corresponding to the display screen, wherein the monitoring means detects an access of the display data supply source to the video memory, and resets / resets the clocking operation in response to the detection. The display control device according to claim 1, further comprising a timer that counts the set time that can be started. 3. The display control device according to claim 1, wherein the display element is a ferroelectric liquid crystal element.